Searched refs:gen7 (Results 1 – 25 of 41) sorted by relevance
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| /third_party/mesa3d/docs/ |
| D | features.txt | 114 GL 4.0, GLSL 4.00 --- all DONE: i965/gen7+, nvc0, r600, radeonsi, llvmpipe, virgl, zink
117 …GL_ARB_draw_indirect DONE (freedreno, i965/gen7+, softpipe, swr, …
118 GL_ARB_gpu_shader5 DONE (i965/gen7+)
131 GL_ARB_gpu_shader_fp64 DONE (i965/gen7+, softpipe, swr)
134 GL_ARB_tessellation_shader DONE (freedreno/a6xx, i965/gen7+, swr)
140 …GL_ARB_transform_feedback3 DONE (freedreno/a3xx+, i965/gen7+, softpipe,…
143 GL 4.1, GLSL 4.10 --- all DONE: i965/gen7+, nvc0, r600, radeonsi, llvmpipe, virgl, zink
148 …GL_ARB_shader_precision DONE (i965/gen7+, all drivers that support G…
149 GL_ARB_vertex_attrib_64bit DONE (i965/gen7+, softpipe, swr)
153 GL 4.2, GLSL 4.20 -- all DONE: i965/gen7+, nvc0, r600, radeonsi, llvmpipe, virgl, zink
[all …]
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| /third_party/libdrm/intel/ |
| D | meson.build | 86 'gen7-3d.batch',
87 find_program('tests/gen7-3d.batch.sh'),
91 'gen7-2d-copy.batch',
92 find_program('tests/gen7-2d-copy.batch.sh'),
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| /third_party/jerryscript/tests/jerry/es2015/ |
| D | generator.js | 192 function* gen7() { generator
196 f = gen7()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 19.1.4.rst | 138 - anv: Disable transform feedback on gen7
142 - intel/fs: Implement quad_swap_horizontal with a swizzle on gen7
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| D | 10.2.rst | 39 - GL_ARB_texture_view on i965/gen7
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| D | 9.1.3.rst | 118 - i965/fs: Do CSE on gen7's varying-index pull constant loads.
120 - i965/gen7: Skip resetting SOL offsets at batch start with HW
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| D | 19.0.3.rst | 76 - anv/pipeline: Fix MEDIA_VFE_STATE::PerThreadScratchSpace on gen7
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| D | 19.0.7.rst | 81 - anv: Set STATE_BASE_ADDRESS upper bounds on gen7
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| D | 17.0.7.rst | 102 - intel/isl/gen7: Use stencil vertical alignment of 8 instead of 4
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| D | 19.1.1.rst | 82 - anv: Set STATE_BASE_ADDRESS upper bounds on gen7
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| D | 17.1.7.rst | 102 - anv/formats: Allow sampling on depth-only formats on gen7
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| D | 8.0.1.rst | 106 - i965/fs: Enable register spilling on gen7 too.
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| D | 17.1.1.rst | 128 - intel/isl/gen7: Use stencil vertical alignment of 8 instead of 4
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| D | 19.1.2.rst | 158 - anv/cmd_buffer: Reuse gen8 Cmd{Set, Reset}Event on gen7
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| D | 13.0.2.rst | 112 - anv: Implement a depth stall restriction on gen7
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| D | 10.0.5.rst | 147 - i965/gen7: Prefer vertical alignment of 4 when possible.
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| D | 10.3.rst | 38 - GL_ARB_gpu_shader5 on i965/gen7, nvc0
45 - GL_ARB_texture_compression_bptc on i965/gen7+, nvc0, r600/evergreen+,
53 - GL_AMD_vertex_shader_viewport_index on i965/gen7+, r600
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| D | 11.2.2.rst | 165 - i965/blorp/gen7: Prepare re-using for gen8
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| D | 17.1.4.rst | 63 - i965: Add and initialize l3_banks field for gen7+
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| D | 17.0.1.rst | 119 - i965/sampler_state: Clamp min/max LOD to 14 on gen7+
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| D | 12.0.2.rst | 217 - anv/pipeline: Unify blend state setup between gen7 and gen8
218 - anv: Enable independentBlend on gen7
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| D | 13.0.5.rst | 146 - anv: Flush render cache before STATE_BASE_ADDRESS on gen7
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| D | 9.1.2.rst | 136 - i965: Add definitions for gen7+ data cache messages.
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| D | 13.0.0.rst | 50 - GL_OES_primitive_bounding_box on i965/gen7+, nvc0, radeonsi
52 - GL_OES_tessellation_shader on i965/gen7+, nvc0, radeonsi
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| /third_party/mesa3d/src/intel/genxml/ |
| D | meson.build | 26 'gen7.xml',
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