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Searched refs:is_haswell (Results 1 – 25 of 35) sorted by relevance

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/third_party/mesa3d/src/intel/compiler/
Dbrw_ir_performance.cpp370 } else if (devinfo->is_haswell) { in instruction_desc()
395 } else if (devinfo->is_haswell) { in instruction_desc()
425 else if (devinfo->is_haswell) in instruction_desc()
445 } else if (devinfo->is_haswell) { in instruction_desc()
475 else if (devinfo->is_haswell) in instruction_desc()
491 else if (devinfo->is_haswell) in instruction_desc()
527 else if (devinfo->is_haswell) in instruction_desc()
538 else if (devinfo->is_haswell) in instruction_desc()
606 else if (devinfo->is_haswell) in instruction_desc()
617 else if (devinfo->is_haswell) in instruction_desc()
[all …]
Dbrw_schedule_instructions.cpp68 void set_latency_gfx7(bool is_haswell);
158 schedule_node::set_latency_gfx7(bool is_haswell) in set_latency_gfx7() argument
184 latency = is_haswell ? 16 : 18; in set_latency_gfx7()
229 latency = is_haswell ? 14 : 16; in set_latency_gfx7()
240 latency = is_haswell ? 22 : 24; in set_latency_gfx7()
380 latency = is_haswell ? 300 : 600; in set_latency_gfx7()
407 assert(!is_haswell); in set_latency_gfx7()
413 assert(!is_haswell); in set_latency_gfx7()
469 assert(!is_haswell); in set_latency_gfx7()
488 assert(!is_haswell); in set_latency_gfx7()
[all …]
Dbrw_vec4_surface_builder.cpp166 const bool has_simd4x2 = bld.shader->devinfo->is_haswell; in emit_untyped_write()
187 const bool has_simd4x2 = bld.shader->devinfo->is_haswell; in emit_untyped_atomic()
Dbrw_vec4_generator.cpp133 assert(devinfo->is_haswell); in generate_tex()
2191 assert(devinfo->is_haswell); in generate_code()
/third_party/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_pipe_control.c307 if (devinfo->is_haswell) { in brw_emit_end_of_pipe_sync()
411 devinfo->is_haswell ? gfx75_emit_raw_pipe_control in brw_init_pipe_control()
Dhsw_sol.c202 if (devinfo->is_haswell) { in hsw_pause_transform_feedback()
232 if (devinfo->is_haswell) { in hsw_resume_transform_feedback()
Dbrw_wm.c259 devinfo->is_haswell ? t->Attrib._Swizzle : key->swizzles[s]; in brw_populate_sampler_prog_key_data()
274 if (!devinfo->is_haswell) in brw_populate_sampler_prog_key_data()
Dgfx7_l3_state.c151 OUT_BATCH((devinfo->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT : in setup_l3_config()
Dbrw_screen.c2105 if (screen->cmd_parser_version >= (devinfo->is_haswell ? 7 : 2)) in brw_detect_pipelined_so()
2422 if (screen->devinfo.is_haswell && can_do_compute_dispatch(screen)) in set_max_gl_versions()
2424 if (screen->devinfo.is_haswell && can_do_mi_math_and_lrr(screen)) in set_max_gl_versions()
2429 dri_screen->max_gl_es2_version = screen->devinfo.is_haswell ? 31 : 30; in set_max_gl_versions()
2737 if (devinfo->is_haswell && screen->cmd_parser_version >= 4) { in brw_init_screen()
2747 (devinfo->is_haswell && screen->cmd_parser_version >= 7)) { in brw_init_screen()
Dgfx6_queryobj.c299 if (devinfo->ver == 8 || devinfo->is_haswell) in gfx6_queryobj_get_results()
Dhsw_queryobj.c340 if (devinfo->ver == 8 || devinfo->is_haswell) in hsw_result_to_gpr0()
Dbrw_extensions.c149 else if (devinfo->is_haswell && can_do_pipelined_register_writes(brw->screen)) in brw_init_extensions()
Dbrw_state_upload.c320 else if (devinfo->is_haswell) in brw_init_state()
Dbrw_batch.c636 if (devinfo->is_haswell) { in brw_finish_batch()
Dbrw_wm_surface_state.c538 need_green_to_blue = devinfo->is_haswell; in brw_update_texture_surface()
/third_party/mesa3d/src/intel/dev/
Dintel_device_info.h61 bool is_haswell; member
Dintel_device_info.c313 .is_haswell = true, \
1498 } else if (devinfo->is_haswell) { in init_max_scratch_ids()
/third_party/mesa3d/src/intel/perf/
Dintel_perf_mdapi.c47 assert(devinfo->is_haswell); in intel_perf_query_result_write_mdapi()
167 if (devinfo->is_haswell || devinfo->ver == 8) { in intel_perf_register_mdapi_statistic_query()
Dintel_perf.c419 if (devinfo->is_haswell) in get_register_queries_function()
552 if (devinfo->is_haswell || devinfo->ver == 8) { in load_pipeline_statistic_metrics()
716 if (devinfo->is_haswell) in oa_metrics_available()
/third_party/mesa3d/src/gallium/drivers/crocus/
Dcrocus_pipe_control.c192 if (batch->screen->devinfo.is_haswell) { in crocus_emit_end_of_pipe_sync()
Dcrocus_batch.c70 #define BATCH_RESERVED(devinfo) ((devinfo)->is_haswell ? 32 : 16)
/third_party/mesa3d/src/intel/vulkan/
DgenX_query.c517 if ((device->info.ver == 8 || device->info.is_haswell) && in genX()
1420 cmd_buffer->device->info.is_haswell) && in genX()
/third_party/mesa3d/src/intel/isl/
Disl.h84 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
Disl.c141 if (dev->info->is_haswell) { in isl_device_setup_mocs()
3202 if (devinfo->is_haswell) { in isl_swizzle_supports_rendering()
/third_party/mesa3d/src/intel/common/tests/
Dmi_builder_test.cpp197 if (devinfo.ver != GFX_VER || devinfo.is_haswell != (GFX_VERx10 == 75)) { in SetUp()

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