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Searched refs:swizzle_mode (Results 1 – 25 of 37) sorted by relevance

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/third_party/mesa3d/src/amd/common/
Dac_surface_meta_address_test.c198 unsigned swizzle_mode, bool pipe_aligned, bool rb_aligned, in one_dcc_address_test() argument
217 xin.swizzleMode = in.swizzleMode = din.swizzleMode = swizzle_mode; in one_dcc_address_test()
321 unsigned swizzle_mode = info->chip_class == GFX9 ? ADDR_SW_64KB_S_X : ADDR_SW_64KB_R_X; in run_dcc_address_test() local
363 … bpp, swizzle_mode, pipe_aligned, rb_aligned, mrt_index, in run_dcc_address_test()
405 unsigned bpp, unsigned swizzle_mode, in one_htile_address_test() argument
424 hin.swizzleMode = in.swizzleMode = xin.swizzleMode = swizzle_mode; in one_htile_address_test()
544 unsigned bpp, unsigned swizzle_mode, in one_cmask_address_test() argument
557 cin.swizzleMode = xin.swizzleMode = in.swizzleMode = swizzle_mode; in one_cmask_address_test()
640 unsigned swizzle_mode = info->chip_class == GFX9 ? ADDR_SW_64KB_S_X : ADDR_SW_64KB_Z_X; in run_cmask_address_test() local
664 swizzle_mode, in run_cmask_address_test()
Dac_surface_modifier_test.c78 din.swizzleMode = surf->u.gfx9.swizzle_mode; in get_addr_from_coord_base()
95 dcc_input.swizzleMode = surf->u.gfx9.swizzle_mode; in get_addr_from_coord_base()
133 input.swizzleMode = surf->u.gfx9.swizzle_mode; in generate_hash()
Dac_surface.c1356 AddrSwizzleMode *swizzle_mode) in gfx9_get_preferred_swizzle_mode() argument
1429 *swizzle_mode = sout.swizzleMode; in gfx9_get_preferred_swizzle_mode()
1672 surf->u.gfx9.swizzle_mode = in->swizzleMode; in gfx9_compute_miptree()
1679 surf->u.gfx9.color.fmask_swizzle_mode = surf->u.gfx9.swizzle_mode & ~0x3; in gfx9_compute_miptree()
1690 surf->u.gfx9.swizzle_mode == ADDR_SW_LINEAR) { in gfx9_compute_miptree()
2199 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.swizzle_mode; in gfx9_compute_surface()
2264 surf->is_linear = surf->u.gfx9.swizzle_mode == ADDR_SW_LINEAR; in gfx9_compute_surface()
2270 r = Addr2IsValidDisplaySwizzleMode(addrlib->handle, surf->u.gfx9.swizzle_mode, in gfx9_compute_surface()
2293 assert(is_dcc_supported_by_CB(info, surf->u.gfx9.swizzle_mode)); in gfx9_compute_surface()
2325 switch (surf->u.gfx9.swizzle_mode) { in gfx9_compute_surface()
[all …]
Dac_surface.h232 uint8_t swizzle_mode; /* color or depth */ member
/third_party/mesa3d/src/amd/vulkan/
Dradv_meta_dcc_retile.c172 &vk_pipeline_info, NULL, &device->meta_state.dcc_retile.pipeline[surf->u.gfx9.swizzle_mode]); in radv_device_init_meta_dcc_retile_state()
198 unsigned swizzle_mode = image->planes[0].surface.u.gfx9.swizzle_mode; in radv_retile_dcc() local
201 if (!cmd_buffer->device->meta_state.dcc_retile.pipeline[swizzle_mode]) { in radv_retile_dcc()
215 device->meta_state.dcc_retile.pipeline[swizzle_mode]); in radv_retile_dcc()
Dradv_image.c423 if (md->u.gfx9.swizzle_mode > 0) in radv_patch_surface_from_metadata()
428 surface->u.gfx9.swizzle_mode = md->u.gfx9.swizzle_mode; in radv_patch_surface_from_metadata()
773 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.swizzle_mode); in si_set_mutable_tex_desc_fields()
803 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.swizzle_mode); in si_set_mutable_tex_desc_fields()
1268 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.swizzle_mode; in radv_init_metadata()
Dradv_radeon_winsys.h145 unsigned swizzle_mode : 5; member
Dradv_meta_resolve.c362 return dst_image->planes[0].surface.u.gfx9.swizzle_mode == in image_hw_resolve_compat()
363 src_image->planes[0].surface.u.gfx9.swizzle_mode; in image_hw_resolve_compat()
/third_party/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_bufmgr.h168 uint32_t swizzle_mode; member
323 uint32_t *swizzle_mode);
Dbrw_bufmgr.c655 bo->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; in bo_alloc_internal()
835 bo->swizzle_mode = get_tiling.swizzle_mode; in brw_bo_gem_create_from_name()
1456 bo->swizzle_mode = set_tiling.swizzle_mode; in bo_set_tiling_internal()
1463 uint32_t *swizzle_mode) in brw_bo_get_tiling() argument
1466 *swizzle_mode = bo->swizzle_mode; in brw_bo_get_tiling()
1533 bo->swizzle_mode = get_tiling.swizzle_mode; in brw_bo_gem_create_from_prime_internal()
/third_party/mesa3d/src/gallium/drivers/crocus/
Dcrocus_bufmgr.h106 uint32_t swizzle_mode; member
266 uint32_t *swizzle_mode);
Dcrocus_bufmgr.c368 bo->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; in alloc_fresh_bo()
584 bo->swizzle_mode = get_tiling.swizzle_mode; in crocus_bo_gem_create_from_name()
1196 bo->swizzle_mode = set_tiling.swizzle_mode; in bo_set_tiling_internal()
1203 uint32_t *swizzle_mode) in crocus_bo_get_tiling() argument
1206 *swizzle_mode = bo->swizzle_mode; in crocus_bo_get_tiling()
Dcrocus_screen.c726 uint32_t swizzle_mode = 0; in crocus_detect_swizzling() local
733 crocus_bo_get_tiling(buffer, &tiling, &swizzle_mode); in crocus_detect_swizzling()
736 return swizzle_mode != I915_BIT_6_SWIZZLE_NONE; in crocus_detect_swizzling()
/third_party/libdrm/intel/
Dintel_bufmgr.c251 uint32_t * swizzle_mode) in drm_intel_bo_get_tiling() argument
254 return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode); in drm_intel_bo_get_tiling()
257 *swizzle_mode = I915_BIT_6_SWIZZLE_NONE; in drm_intel_bo_get_tiling()
Dintel_bufmgr_gem.c192 uint32_t swizzle_mode; member
294 uint32_t * swizzle_mode);
822 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; in drm_intel_gem_bo_alloc_internal()
983 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; in drm_intel_gem_bo_alloc_userptr()
1075 uint32_t *swizzle_mode) in get_tiling_mode() argument
1089 *swizzle_mode = get_tiling.swizzle_mode; in get_tiling_mode()
1171 &bo_gem->tiling_mode, &bo_gem->swizzle_mode); in drm_intel_bo_gem_create_from_name()
2590 bo_gem->swizzle_mode = set_tiling.swizzle_mode; in drm_intel_gem_bo_set_tiling_internal()
2625 uint32_t * swizzle_mode) in drm_intel_gem_bo_get_tiling() argument
2630 *swizzle_mode = bo_gem->swizzle_mode; in drm_intel_gem_bo_get_tiling()
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Dintel_bufmgr_priv.h241 uint32_t * swizzle_mode);
Dintel_bufmgr.h163 uint32_t * swizzle_mode);
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_clear.c379 assert(tex->surface.u.gfx9.swizzle_mode >= 4); in si_set_optimal_micro_tile_mode()
389 assert(tex->surface.u.gfx9.swizzle_mode % 4 != 0); in si_set_optimal_micro_tile_mode()
393 tex->surface.u.gfx9.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
394 tex->surface.u.gfx9.swizzle_mode += 2; /* D */ in si_set_optimal_micro_tile_mode()
397 tex->surface.u.gfx9.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
398 tex->surface.u.gfx9.swizzle_mode += 1; /* S */ in si_set_optimal_micro_tile_mode()
401 tex->surface.u.gfx9.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
402 tex->surface.u.gfx9.swizzle_mode += 3; /* R */ in si_set_optimal_micro_tile_mode()
Dsi_test_blit.c124 switch (surf->u.gfx9.swizzle_mode) { in array_mode_to_string()
138 printf("Unhandled swizzle mode = %u\n", surf->u.gfx9.swizzle_mode); in array_mode_to_string()
Dsi_compute_blit.c623 void **shader = &sctx->cs_dcc_retile[tex->surface.u.gfx9.swizzle_mode]; in si_retile_dcc()
667 unsigned swizzle_mode = tex->surface.u.gfx9.swizzle_mode; in gfx9_clear_dcc_msaa() local
672 …void **shader = &sctx->cs_clear_dcc_msaa[swizzle_mode][bpe_log2][fragments8][log2_samples - 2][is_… in gfx9_clear_dcc_msaa()
/third_party/libdrm/include/drm/
Di915_drm.h1275 __u32 swizzle_mode; member
1292 __u32 swizzle_mode; member
/third_party/mesa3d/src/gallium/drivers/radeon/
Dradeon_vcn_enc_2_0.c448 enc->enc_pic.ctx_buf.swizzle_mode = 0; in radeon_enc_ctx()
472 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode); in radeon_enc_ctx()
Dradeon_uvd_enc.h296 uint32_t swizzle_mode; member
Dradeon_vcn_enc_1_2.c1050 enc->enc_pic.ctx_buf.swizzle_mode = 0; in radeon_enc_ctx()
1057 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode); in radeon_enc_ctx()
1158 enc->enc_pic.enc_params.input_pic_swizzle_mode = enc->luma->u.gfx9.swizzle_mode; in radeon_enc_encode_params()
1208 enc->enc_pic.enc_params.input_pic_swizzle_mode = enc->luma->u.gfx9.swizzle_mode; in radeon_enc_encode_params_hevc()
/third_party/mesa3d/include/drm-uapi/
Di915_drm.h1566 __u32 swizzle_mode; member
1583 __u32 swizzle_mode; member

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