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/third_party/mesa3d/src/intel/isl/
Disl_drm.c35 isl_tiling_to_i915_tiling(enum isl_tiling tiling) in isl_tiling_to_i915_tiling() argument
37 switch (tiling) { in isl_tiling_to_i915_tiling()
62 isl_tiling_from_i915_tiling(uint32_t tiling) in isl_tiling_from_i915_tiling() argument
64 switch (tiling) { in isl_tiling_from_i915_tiling()
84 .tiling = ISL_TILING_LINEAR,
89 .tiling = ISL_TILING_X,
94 .tiling = ISL_TILING_Y0,
99 .tiling = ISL_TILING_Y0,
106 .tiling = ISL_TILING_Y0,
113 .tiling = ISL_TILING_Y0,
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Disl_gfx9.c35 enum isl_tiling tiling, in gfx9_calc_std_image_alignment_sa() argument
41 assert(isl_tiling_is_std_y(tiling)); in gfx9_calc_std_image_alignment_sa()
44 const uint32_t is_Ys = tiling == ISL_TILING_Ys; in gfx9_calc_std_image_alignment_sa()
102 enum isl_tiling tiling, in isl_gfx9_choose_image_alignment_el() argument
168 if (isl_tiling_is_std_y(tiling)) { in isl_gfx9_choose_image_alignment_el()
170 gfx9_calc_std_image_alignment_sa(dev, info, tiling, msaa_layout, in isl_gfx9_choose_image_alignment_el()
199 isl_gfx8_choose_image_alignment_el(dev, info, tiling, dim_layout, in isl_gfx9_choose_image_alignment_el()
Disl.c45 enum isl_tiling tiling, in isl_memcpy_linear_to_tiled() argument
52 tiling, copy_type); in isl_memcpy_linear_to_tiled()
59 tiling, copy_type); in isl_memcpy_linear_to_tiled()
68 enum isl_tiling tiling, in isl_memcpy_tiled_to_linear() argument
75 tiling, copy_type); in isl_memcpy_tiled_to_linear()
82 tiling, copy_type); in isl_memcpy_tiled_to_linear()
335 isl_tiling_get_info(enum isl_tiling tiling, in isl_tiling_get_info() argument
346 if (tiling != ISL_TILING_LINEAR && !isl_is_pow2(format_bpb)) { in isl_tiling_get_info()
352 assert(tiling == ISL_TILING_X || tiling == ISL_TILING_Y0 || in isl_tiling_get_info()
353 tiling == ISL_TILING_4); in isl_tiling_get_info()
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Disl_gfx12.c89 enum isl_tiling tiling, in isl_gfx125_choose_image_alignment_el() argument
96 if (tiling == ISL_TILING_64) { in isl_gfx125_choose_image_alignment_el()
112 isl_tiling_get_info(tiling, info->dim, msaa_layout, fmtl->bpb, in isl_gfx125_choose_image_alignment_el()
157 *image_align_el = tiling == ISL_TILING_LINEAR ? in isl_gfx125_choose_image_alignment_el()
181 enum isl_tiling tiling, in isl_gfx12_choose_image_alignment_el() argument
219 isl_gfx9_choose_image_alignment_el(dev, info, tiling, dim_layout, in isl_gfx12_choose_image_alignment_el()
Disl_tiled_memcpy_normal.c41 enum isl_tiling tiling, in _isl_memcpy_linear_to_tiled() argument
45 has_swizzling, tiling, copy_type); in _isl_memcpy_linear_to_tiled()
54 enum isl_tiling tiling, in _isl_memcpy_tiled_to_linear() argument
58 has_swizzling, tiling, copy_type); in _isl_memcpy_tiled_to_linear()
Disl_tiled_memcpy_sse41.c42 enum isl_tiling tiling, in _isl_memcpy_linear_to_tiled_sse41() argument
46 has_swizzling, tiling, copy_type); in _isl_memcpy_linear_to_tiled_sse41()
55 enum isl_tiling tiling, in _isl_memcpy_tiled_to_linear_sse41() argument
59 has_swizzling, tiling, copy_type); in _isl_memcpy_tiled_to_linear_sse41()
Disl_gfx8.c30 enum isl_tiling tiling, in isl_gfx8_choose_msaa_layout() argument
93 enum isl_tiling tiling, in isl_gfx8_choose_image_alignment_el() argument
101 assert(!isl_tiling_is_std_y(tiling)); in isl_gfx8_choose_image_alignment_el()
176 if (ISL_GFX_VER(dev) >= 11 && isl_tiling_is_any_y(tiling) && in isl_gfx8_choose_image_alignment_el()
Disl_storage_image.c268 switch (surf->tiling) { in isl_surf_fill_image_param()
275 param->tiling[0] = isl_log2u(512 / cpp); in isl_surf_fill_image_param()
276 param->tiling[1] = isl_log2u(8); in isl_surf_fill_image_param()
293 param->tiling[0] = isl_log2u(16 / cpp); in isl_surf_fill_image_param()
294 param->tiling[1] = isl_log2u(32); in isl_surf_fill_image_param()
314 param->tiling[2] = (ISL_GFX_VER(dev) < 9 && surf->dim == ISL_SURF_DIM_3D ? in isl_surf_fill_image_param()
Disl_gfx6.c30 enum isl_tiling tiling, in isl_gfx6_choose_msaa_layout() argument
59 if (tiling == ISL_TILING_LINEAR) in isl_gfx6_choose_msaa_layout()
71 enum isl_tiling tiling, in isl_gfx6_choose_image_alignment_el() argument
Disl_gfx4.c30 enum isl_tiling tiling, in isl_gfx4_choose_msaa_layout() argument
86 enum isl_tiling tiling, in isl_gfx4_choose_image_alignment_el() argument
93 assert(!isl_tiling_is_std_y(tiling)); in isl_gfx4_choose_image_alignment_el()
/third_party/mesa3d/src/mesa/drivers/dri/i915/
Dintel_regions.c59 uint32_t tiling, drm_intel_bo *buffer) in intel_region_alloc_internal() argument
73 region->tiling = tiling; in intel_region_alloc_internal()
81 uint32_t tiling, in intel_region_alloc() argument
95 &tiling, &aligned_pitch, flags); in intel_region_alloc()
100 aligned_pitch, tiling, buffer); in intel_region_alloc()
131 uint32_t bit_6_swizzle, tiling; in intel_region_alloc_for_handle() local
136 ret = drm_intel_bo_get_tiling(buffer, &tiling, &bit_6_swizzle); in intel_region_alloc_for_handle()
145 width, height, pitch, tiling, buffer); in intel_region_alloc_for_handle()
166 uint32_t bit_6_swizzle, tiling; in intel_region_alloc_for_fd() local
171 ret = drm_intel_bo_get_tiling(buffer, &tiling, &bit_6_swizzle); in intel_region_alloc_for_fd()
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/third_party/boost/boost/graph/distributed/
Dfruchterman_reingold.hpp142 Point extent, simple_tiling tiling) in neighboring_tiles_force_pairs() argument
143 : position(position), origin(origin), extent(extent), tiling(tiling) in neighboring_tiles_force_pairs()
151 if (tiling.columns == 1 && tiling.rows == 1) in operator ()()
174 std::pair<int, int> my_tile = tiling(process_id(pg)); in operator ()()
177 neighbors[left] = tiling(my_tile.first - 1, my_tile.second); in operator ()()
179 neighbors[top] = tiling(my_tile.first, my_tile.second - 1); in operator ()()
180 if (my_tile.first < tiling.columns - 1) in operator ()()
181 neighbors[right] = tiling(my_tile.first + 1, my_tile.second); in operator ()()
182 if (my_tile.second < tiling.rows - 1) in operator ()()
183 neighbors[bottom] = tiling(my_tile.first, my_tile.second + 1); in operator ()()
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/third_party/mesa3d/src/broadcom/vulkan/
Dv3dv_formats.c94 VkImageTiling tiling) in image_format_features() argument
125 tiling == VK_IMAGE_TILING_OPTIMAL) { in image_format_features()
288 VkImageTiling tiling, in get_image_format_properties() argument
294 image_format_features(physical_device, info->format, v3dv_format, tiling); in get_image_format_properties()
416 if (tiling != VK_IMAGE_TILING_LINEAR && in get_image_format_properties()
424 if (tiling == VK_IMAGE_TILING_LINEAR) in get_image_format_properties()
459 VkImageTiling tiling, in v3dv_GetPhysicalDeviceImageFormatProperties() argument
471 .tiling = tiling, in v3dv_GetPhysicalDeviceImageFormatProperties()
476 return get_image_format_properties(physical_device, &info, tiling, in v3dv_GetPhysicalDeviceImageFormatProperties()
489 VkImageTiling tiling = base_info->tiling; in v3dv_GetPhysicalDeviceImageFormatProperties2() local
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Dv3dvx_meta_common.c45 const struct v3dv_frame_tiling *tiling = &job->frame_tiling; in emit_rcl_prologue() local
49 tiling->layers * 256 * in emit_rcl_prologue()
56 config.image_width_pixels = tiling->width; in emit_rcl_prologue()
57 config.image_height_pixels = tiling->height; in emit_rcl_prologue()
59 config.multisample_mode_4x = tiling->msaa; in emit_rcl_prologue()
60 config.maximum_bpp_of_all_render_targets = tiling->internal_bpp; in emit_rcl_prologue()
70 if (slice->tiling == V3D_TILING_UIF_NO_XOR || in emit_rcl_prologue()
71 slice->tiling == V3D_TILING_UIF_XOR) { in emit_rcl_prologue()
75 align(tiling->height, uif_block_height) / uif_block_height; in emit_rcl_prologue()
91 if (tiling->internal_bpp >= V3D_INTERNAL_BPP_64) { in emit_rcl_prologue()
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Dv3dv_image.c137 slice->tiling = V3D_TILING_RASTER; in v3d_setup_slices()
143 slice->tiling = V3D_TILING_LINEARTILE; in v3d_setup_slices()
147 slice->tiling = V3D_TILING_UBLINEAR_1_COLUMN; in v3d_setup_slices()
151 slice->tiling = V3D_TILING_UBLINEAR_2_COLUMN; in v3d_setup_slices()
170 slice->tiling = V3D_TILING_UIF_XOR; in v3d_setup_slices()
172 slice->tiling = V3D_TILING_UIF_NO_XOR; in v3d_setup_slices()
180 if (slice->tiling == V3D_TILING_UIF_NO_XOR || in v3d_setup_slices()
181 slice->tiling == V3D_TILING_UIF_XOR) { in v3d_setup_slices()
267 VkImageTiling tiling = pCreateInfo->tiling; in create_image() local
269 if (tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) { in create_image()
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/third_party/mesa3d/src/gallium/drivers/crocus/
Dcrocus_blt.c55 if (dst->surf.tiling != ISL_TILING_LINEAR) in blt_set_alpha_to_one()
72 isl_tiling_get_intratile_offset_el(dst->surf.tiling, dst->surf.dim, in blt_set_alpha_to_one()
84 xyblt.TilingEnable = dst->surf.tiling != ISL_TILING_LINEAR; in blt_set_alpha_to_one()
137 if (res->surf.tiling != ISL_TILING_LINEAR) in crocus_resource_blt_pitch()
166 isl_get_tile_dims(src->surf.tiling, cpp, &src_tile_w, &src_tile_h); in emit_copy_blt()
167 isl_get_tile_dims(dst->surf.tiling, cpp, &dst_tile_w, &dst_tile_h); in emit_copy_blt()
173 assert(src->surf.tiling == ISL_TILING_LINEAR || (src_pitch % src_tile_w) == 0); in emit_copy_blt()
174 assert(dst->surf.tiling == ISL_TILING_LINEAR || (dst_pitch % dst_tile_w) == 0); in emit_copy_blt()
204 if (dst->surf.tiling != ISL_TILING_LINEAR) in emit_copy_blt()
207 if (src->surf.tiling != ISL_TILING_LINEAR) in emit_copy_blt()
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/third_party/vk-gl-cts/external/vulkancts/modules/vulkan/ycbcr/
DvktYCbCrFormatTests.cpp74 VkImageTiling tiling, in createTestImage() argument
89 tiling, in createTestImage()
227 VkImageTiling tiling; member
242 , tiling (tiling_) in TestParameters()
252 , tiling (VK_IMAGE_TILING_OPTIMAL) in TestParameters()
287 checkImageSupport(context, params.format, params.flags, params.tiling); in checkSupport()
295 …params.format, VK_IMAGE_TYPE_2D, params.tiling, VK_IMAGE_USAGE_TRANSFER_DST_BIT | VK_IMAGE_USAGE_S… in checkSupport()
324 const VkImageTiling tiling = params.tiling; in testFormat() local
329 …> image (createTestImage(vkd, device, format, size, createFlags, tiling, mappedMemory ? VK… in testFormat()
389 params.tiling, in testFormat()
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/third_party/mesa3d/docs/isl/
Dtiling.rst31 .. image:: tiling-basic.svg
42 Intel graphics has several different tiling formats that we'll discuss in
44 chapter is Y-tiling. In all tiling formats the basic principal is the same:
54 on top of the tiling format. This has been removed starting with Broadwell
75 The structure of any given tiling format is represented by ISL using the
105 this is not at all correct. Some tiling formats have logical and physical
107 easiest case study for this is W-tiling. From the Sky Lake PRM Vol. 2d,
121 consider this as its own tiling format or as a modification of Y-tiling. The
124 Y-tiling in connection with stencil buffers and they are always W-tiled. This
128 X-tiling
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/third_party/vk-gl-cts/external/vulkancts/modules/vulkan/api/
DvktApiBufferAndImageAllocationUtil.cpp111 VkImageTiling tiling) const in createTestImage()
128 tiling, // VkImageTiling tiling; in createTestImage()
129 …(vk::VkImageUsageFlags)((tiling == VK_IMAGE_TILING_LINEAR) ? VK_IMAGE_USAGE_TRANSFER_SRC_BIT | VK_… in createTestImage()
149 VkImageTiling tiling) const in createTestImage()
172 tiling, // VkImageTiling tiling; in createTestImage()
173 …(vk::VkImageUsageFlags)((tiling == VK_IMAGE_TILING_LINEAR) ? VK_IMAGE_USAGE_TRANSFER_SRC_BIT | VK_… in createTestImage()
/third_party/libdrm/tegra/
Dtegra.c282 struct drm_tegra_bo_tiling *tiling) in drm_tegra_bo_get_tiling() argument
299 if (tiling) { in drm_tegra_bo_get_tiling()
300 tiling->mode = args.mode; in drm_tegra_bo_get_tiling()
301 tiling->value = args.value; in drm_tegra_bo_get_tiling()
308 const struct drm_tegra_bo_tiling *tiling) in drm_tegra_bo_set_tiling() argument
319 args.mode = tiling->mode; in drm_tegra_bo_set_tiling()
320 args.value = tiling->value; in drm_tegra_bo_set_tiling()
/third_party/gstreamer/gstplugins_bad/gst-libs/gst/vulkan/
Dgstvkimagebufferpool.c109 VkImageTiling tiling = VK_IMAGE_TILING_OPTIMAL; in gst_vulkan_image_buffer_pool_set_config() local
117 tiling = VK_IMAGE_TILING_LINEAR; in gst_vulkan_image_buffer_pool_set_config()
121 height, tiling, in gst_vulkan_image_buffer_pool_set_config()
175 VkImageTiling tiling = VK_IMAGE_TILING_OPTIMAL; in gst_vulkan_image_buffer_pool_alloc() local
181 tiling = VK_IMAGE_TILING_LINEAR; in gst_vulkan_image_buffer_pool_alloc()
185 GST_VIDEO_INFO_COMP_HEIGHT (&priv->v_info, i), tiling, in gst_vulkan_image_buffer_pool_alloc()
Dgstvkimagememory.c131 gsize height, VkImageTiling tiling, VkImageUsageFlags usage) in _create_info_from_args() argument
146 .tiling = tiling, in _create_info_from_args()
210 VkImageTiling tiling, VkImageUsageFlags usage, in _vk_image_mem_new_alloc() argument
224 if (!_create_info_from_args (&image_info, format, width, height, tiling, in _vk_image_mem_new_alloc()
244 tiling, usage, 0, &mem->format_properties); in _vk_image_mem_new_alloc()
289 gsize height, VkImageTiling tiling, VkImageUsageFlags usage, in _vk_image_mem_new_wrapped() argument
310 if (!_create_info_from_args (&mem->create_info, format, width, height, tiling, in _vk_image_mem_new_wrapped()
317 tiling, usage, 0, &mem->format_properties); in _vk_image_mem_new_wrapped()
455 gsize width, gsize height, VkImageTiling tiling, VkImageUsageFlags usage, in gst_vulkan_image_memory_alloc() argument
461 format, width, height, tiling, usage, mem_prop_flags, NULL, NULL); in gst_vulkan_image_memory_alloc()
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/third_party/mesa3d/src/vulkan/util/
Dvk_physical_device.c180 VkImageTiling tiling, in vk_common_GetPhysicalDeviceImageFormatProperties() argument
191 .tiling = tiling, in vk_common_GetPhysicalDeviceImageFormatProperties()
215 VkImageTiling tiling, in vk_common_GetPhysicalDeviceSparseImageFormatProperties() argument
227 .tiling = tiling in vk_common_GetPhysicalDeviceSparseImageFormatProperties()
/third_party/skia/third_party/externals/opengl-registry/extensions/QCOM/
DQCOM_tiled_rendering.txt86 optimization might be to reduce the number of passes needed in the tiling
93 to as "application tiling"), leaving all other portions of the render target
102 and without application tiling within a single frame. Rendering without
103 application tiling ("normal" rendering) is most efficient when all of the
106 a prior resolve, or via application tiling), then that resolve becomes much
111 tiling and normal rendering within a single frame. If both rendering
114 application tiling. An implicit resolve will occur (if needed) at the start
115 of application tiling, so any pending normal rendering operations will be
116 flushed at the time application tiling is initiated. This extension
118 or not rendering done with application tiling depends on the existing
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/third_party/openGLES/extensions/QCOM/
DQCOM_tiled_rendering.txt86 optimization might be to reduce the number of passes needed in the tiling
93 to as "application tiling"), leaving all other portions of the render target
102 and without application tiling within a single frame. Rendering without
103 application tiling ("normal" rendering) is most efficient when all of the
106 a prior resolve, or via application tiling), then that resolve becomes much
111 tiling and normal rendering within a single frame. If both rendering
114 application tiling. An implicit resolve will occur (if needed) at the start
115 of application tiling, so any pending normal rendering operations will be
116 flushed at the time application tiling is initiated. This extension
118 or not rendering done with application tiling depends on the existing
[all …]

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