1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright 2014 Carlo Caione <carlo@caione.org> 4 */ 5 6#include <dt-bindings/clock/meson8-ddr-clkc.h> 7#include <dt-bindings/clock/meson8b-clkc.h> 8#include <dt-bindings/gpio/meson8-gpio.h> 9#include <dt-bindings/power/meson8-power.h> 10#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> 11#include <dt-bindings/reset/amlogic,meson8b-reset.h> 12#include "meson.dtsi" 13 14/ { 15 model = "Amlogic Meson8 SoC"; 16 compatible = "amlogic,meson8"; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: cpu@200 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-a9"; 25 next-level-cache = <&L2>; 26 reg = <0x200>; 27 enable-method = "amlogic,meson8-smp"; 28 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; 29 operating-points-v2 = <&cpu_opp_table>; 30 clocks = <&clkc CLKID_CPUCLK>; 31 }; 32 33 cpu1: cpu@201 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a9"; 36 next-level-cache = <&L2>; 37 reg = <0x201>; 38 enable-method = "amlogic,meson8-smp"; 39 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; 40 operating-points-v2 = <&cpu_opp_table>; 41 clocks = <&clkc CLKID_CPUCLK>; 42 }; 43 44 cpu2: cpu@202 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a9"; 47 next-level-cache = <&L2>; 48 reg = <0x202>; 49 enable-method = "amlogic,meson8-smp"; 50 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; 51 operating-points-v2 = <&cpu_opp_table>; 52 clocks = <&clkc CLKID_CPUCLK>; 53 }; 54 55 cpu3: cpu@203 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a9"; 58 next-level-cache = <&L2>; 59 reg = <0x203>; 60 enable-method = "amlogic,meson8-smp"; 61 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; 62 operating-points-v2 = <&cpu_opp_table>; 63 clocks = <&clkc CLKID_CPUCLK>; 64 }; 65 }; 66 67 cpu_opp_table: opp-table { 68 compatible = "operating-points-v2"; 69 opp-shared; 70 71 opp-96000000 { 72 opp-hz = /bits/ 64 <96000000>; 73 opp-microvolt = <825000>; 74 }; 75 opp-192000000 { 76 opp-hz = /bits/ 64 <192000000>; 77 opp-microvolt = <825000>; 78 }; 79 opp-312000000 { 80 opp-hz = /bits/ 64 <312000000>; 81 opp-microvolt = <825000>; 82 }; 83 opp-408000000 { 84 opp-hz = /bits/ 64 <408000000>; 85 opp-microvolt = <825000>; 86 }; 87 opp-504000000 { 88 opp-hz = /bits/ 64 <504000000>; 89 opp-microvolt = <825000>; 90 }; 91 opp-600000000 { 92 opp-hz = /bits/ 64 <600000000>; 93 opp-microvolt = <850000>; 94 }; 95 opp-720000000 { 96 opp-hz = /bits/ 64 <720000000>; 97 opp-microvolt = <850000>; 98 }; 99 opp-816000000 { 100 opp-hz = /bits/ 64 <816000000>; 101 opp-microvolt = <875000>; 102 }; 103 opp-1008000000 { 104 opp-hz = /bits/ 64 <1008000000>; 105 opp-microvolt = <925000>; 106 }; 107 opp-1200000000 { 108 opp-hz = /bits/ 64 <1200000000>; 109 opp-microvolt = <975000>; 110 }; 111 opp-1416000000 { 112 opp-hz = /bits/ 64 <1416000000>; 113 opp-microvolt = <1025000>; 114 }; 115 opp-1608000000 { 116 opp-hz = /bits/ 64 <1608000000>; 117 opp-microvolt = <1100000>; 118 }; 119 opp-1800000000 { 120 status = "disabled"; 121 opp-hz = /bits/ 64 <1800000000>; 122 opp-microvolt = <1125000>; 123 }; 124 opp-1992000000 { 125 status = "disabled"; 126 opp-hz = /bits/ 64 <1992000000>; 127 opp-microvolt = <1150000>; 128 }; 129 }; 130 131 gpu_opp_table: gpu-opp-table { 132 compatible = "operating-points-v2"; 133 134 opp-182142857 { 135 opp-hz = /bits/ 64 <182142857>; 136 opp-microvolt = <1150000>; 137 }; 138 opp-318750000 { 139 opp-hz = /bits/ 64 <318750000>; 140 opp-microvolt = <1150000>; 141 }; 142 opp-425000000 { 143 opp-hz = /bits/ 64 <425000000>; 144 opp-microvolt = <1150000>; 145 }; 146 opp-510000000 { 147 opp-hz = /bits/ 64 <510000000>; 148 opp-microvolt = <1150000>; 149 }; 150 opp-637500000 { 151 opp-hz = /bits/ 64 <637500000>; 152 opp-microvolt = <1150000>; 153 turbo-mode; 154 }; 155 }; 156 157 pmu { 158 compatible = "arm,cortex-a9-pmu"; 159 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 163 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 164 }; 165 166 reserved-memory { 167 #address-cells = <1>; 168 #size-cells = <1>; 169 ranges; 170 171 /* 2 MiB reserved for Hardware ROM Firmware? */ 172 hwrom@0 { 173 reg = <0x0 0x200000>; 174 no-map; 175 }; 176 177 /* 178 * 1 MiB reserved for the "ARM Power Firmware": this is ARM 179 * code which is responsible for system suspend. It loads a 180 * piece of ARC code ("arc_power" in the vendor u-boot tree) 181 * into SRAM, executes that and shuts down the (last) ARM core. 182 * The arc_power firmware then checks various wakeup sources 183 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or 184 * simply the power key) and re-starts the ARM core once it 185 * detects a wakeup request. 186 */ 187 power-firmware@4f00000 { 188 reg = <0x4f00000 0x100000>; 189 no-map; 190 }; 191 }; 192 193 mmcbus: bus@c8000000 { 194 compatible = "simple-bus"; 195 reg = <0xc8000000 0x8000>; 196 #address-cells = <1>; 197 #size-cells = <1>; 198 ranges = <0x0 0xc8000000 0x8000>; 199 200 ddr_clkc: clock-controller@400 { 201 compatible = "amlogic,meson8-ddr-clkc"; 202 reg = <0x400 0x20>; 203 clocks = <&xtal>; 204 clock-names = "xtal"; 205 #clock-cells = <1>; 206 }; 207 208 dmcbus: bus@6000 { 209 compatible = "simple-bus"; 210 reg = <0x6000 0x400>; 211 #address-cells = <1>; 212 #size-cells = <1>; 213 ranges = <0x0 0x6000 0x400>; 214 215 canvas: video-lut@20 { 216 compatible = "amlogic,meson8-canvas", 217 "amlogic,canvas"; 218 reg = <0x20 0x14>; 219 }; 220 }; 221 }; 222 223 apb: bus@d0000000 { 224 compatible = "simple-bus"; 225 reg = <0xd0000000 0x200000>; 226 #address-cells = <1>; 227 #size-cells = <1>; 228 ranges = <0x0 0xd0000000 0x200000>; 229 230 mali: gpu@c0000 { 231 compatible = "amlogic,meson8-mali", "arm,mali-450"; 232 reg = <0xc0000 0x40000>; 233 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 249 interrupt-names = "gp", "gpmmu", "pp", "pmu", 250 "pp0", "ppmmu0", "pp1", "ppmmu1", 251 "pp2", "ppmmu2", "pp4", "ppmmu4", 252 "pp5", "ppmmu5", "pp6", "ppmmu6"; 253 resets = <&reset RESET_MALI>; 254 255 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; 256 clock-names = "bus", "core"; 257 258 assigned-clocks = <&clkc CLKID_MALI>; 259 assigned-clock-rates = <318750000>; 260 261 operating-points-v2 = <&gpu_opp_table>; 262 }; 263 }; 264}; /* end of / */ 265 266&aobus { 267 pmu: pmu@e0 { 268 compatible = "amlogic,meson8-pmu", "syscon"; 269 reg = <0xe0 0x18>; 270 }; 271 272 pinctrl_aobus: pinctrl@84 { 273 compatible = "amlogic,meson8-aobus-pinctrl"; 274 reg = <0x84 0xc>; 275 #address-cells = <1>; 276 #size-cells = <1>; 277 ranges; 278 279 gpio_ao: ao-bank@14 { 280 reg = <0x14 0x4>, 281 <0x2c 0x4>, 282 <0x24 0x8>; 283 reg-names = "mux", "pull", "gpio"; 284 gpio-controller; 285 #gpio-cells = <2>; 286 gpio-ranges = <&pinctrl_aobus 0 0 16>; 287 }; 288 289 uart_ao_a_pins: uart_ao_a { 290 mux { 291 groups = "uart_tx_ao_a", "uart_rx_ao_a"; 292 function = "uart_ao"; 293 bias-disable; 294 }; 295 }; 296 297 i2c_ao_pins: i2c_mst_ao { 298 mux { 299 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; 300 function = "i2c_mst_ao"; 301 bias-disable; 302 }; 303 }; 304 305 ir_recv_pins: remote { 306 mux { 307 groups = "remote_input"; 308 function = "remote"; 309 bias-disable; 310 }; 311 }; 312 313 pwm_f_ao_pins: pwm-f-ao { 314 mux { 315 groups = "pwm_f_ao"; 316 function = "pwm_f_ao"; 317 bias-disable; 318 }; 319 }; 320 }; 321}; 322 323&cbus { 324 reset: reset-controller@4404 { 325 compatible = "amlogic,meson8b-reset"; 326 reg = <0x4404 0x9c>; 327 #reset-cells = <1>; 328 }; 329 330 analog_top: analog-top@81a8 { 331 compatible = "amlogic,meson8-analog-top", "syscon"; 332 reg = <0x81a8 0x14>; 333 }; 334 335 pwm_ef: pwm@86c0 { 336 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; 337 reg = <0x86c0 0x10>; 338 #pwm-cells = <3>; 339 status = "disabled"; 340 }; 341 342 clock-measure@8758 { 343 compatible = "amlogic,meson8-clk-measure"; 344 reg = <0x8758 0x1c>; 345 }; 346 347 pinctrl_cbus: pinctrl@9880 { 348 compatible = "amlogic,meson8-cbus-pinctrl"; 349 reg = <0x9880 0x10>; 350 #address-cells = <1>; 351 #size-cells = <1>; 352 ranges; 353 354 gpio: banks@80b0 { 355 reg = <0x80b0 0x28>, 356 <0x80e8 0x18>, 357 <0x8120 0x18>, 358 <0x8030 0x30>; 359 reg-names = "mux", "pull", "pull-enable", "gpio"; 360 gpio-controller; 361 #gpio-cells = <2>; 362 gpio-ranges = <&pinctrl_cbus 0 0 120>; 363 }; 364 365 sd_a_pins: sd-a { 366 mux { 367 groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", 368 "sd_d3_a", "sd_clk_a", "sd_cmd_a"; 369 function = "sd_a"; 370 bias-disable; 371 }; 372 }; 373 374 sd_b_pins: sd-b { 375 mux { 376 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", 377 "sd_d3_b", "sd_clk_b", "sd_cmd_b"; 378 function = "sd_b"; 379 bias-disable; 380 }; 381 }; 382 383 sd_c_pins: sd-c { 384 mux { 385 groups = "sd_d0_c", "sd_d1_c", "sd_d2_c", 386 "sd_d3_c", "sd_clk_c", "sd_cmd_c"; 387 function = "sd_c"; 388 bias-disable; 389 }; 390 }; 391 392 sdxc_b_pins: sdxc-b { 393 mux { 394 groups = "sdxc_d0_b", "sdxc_d13_b", 395 "sdxc_clk_b", "sdxc_cmd_b"; 396 function = "sdxc_b"; 397 bias-pull-up; 398 }; 399 }; 400 401 spi_nor_pins: nor { 402 mux { 403 groups = "nor_d", "nor_q", "nor_c", "nor_cs"; 404 function = "nor"; 405 bias-disable; 406 }; 407 }; 408 409 eth_pins: ethernet { 410 mux { 411 groups = "eth_tx_clk_50m", "eth_tx_en", 412 "eth_txd1", "eth_txd0", 413 "eth_rx_clk_in", "eth_rx_dv", 414 "eth_rxd1", "eth_rxd0", "eth_mdio", 415 "eth_mdc"; 416 function = "ethernet"; 417 bias-disable; 418 }; 419 }; 420 421 pwm_e_pins: pwm-e { 422 mux { 423 groups = "pwm_e"; 424 function = "pwm_e"; 425 bias-disable; 426 }; 427 }; 428 429 uart_a1_pins: uart-a1 { 430 mux { 431 groups = "uart_tx_a1", 432 "uart_rx_a1"; 433 function = "uart_a"; 434 bias-disable; 435 }; 436 }; 437 438 uart_a1_cts_rts_pins: uart-a1-cts-rts { 439 mux { 440 groups = "uart_cts_a1", 441 "uart_rts_a1"; 442 function = "uart_a"; 443 bias-disable; 444 }; 445 }; 446 }; 447}; 448 449&ahb_sram { 450 smp-sram@1ff80 { 451 compatible = "amlogic,meson8-smp-sram"; 452 reg = <0x1ff80 0x8>; 453 }; 454}; 455 456&efuse { 457 compatible = "amlogic,meson8-efuse"; 458 clocks = <&clkc CLKID_EFUSE>; 459 clock-names = "core"; 460 461 temperature_calib: calib@1f4 { 462 /* only the upper two bytes are relevant */ 463 reg = <0x1f4 0x4>; 464 }; 465}; 466 467ðmac { 468 clocks = <&clkc CLKID_ETH>; 469 clock-names = "stmmaceth"; 470 471 power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>; 472}; 473 474&gpio_intc { 475 compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc"; 476 status = "okay"; 477}; 478 479&hhi { 480 clkc: clock-controller { 481 compatible = "amlogic,meson8-clkc"; 482 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; 483 clock-names = "xtal", "ddr_pll"; 484 #clock-cells = <1>; 485 #reset-cells = <1>; 486 }; 487 488 pwrc: power-controller { 489 compatible = "amlogic,meson8-pwrc"; 490 #power-domain-cells = <1>; 491 amlogic,ao-sysctrl = <&pmu>; 492 clocks = <&clkc CLKID_VPU>; 493 clock-names = "vpu"; 494 assigned-clocks = <&clkc CLKID_VPU>; 495 assigned-clock-rates = <364285714>; 496 }; 497}; 498 499&hwrng { 500 compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; 501 clocks = <&clkc CLKID_RNG0>; 502 clock-names = "core"; 503}; 504 505&i2c_AO { 506 clocks = <&clkc CLKID_CLK81>; 507}; 508 509&i2c_A { 510 clocks = <&clkc CLKID_CLK81>; 511}; 512 513&i2c_B { 514 clocks = <&clkc CLKID_CLK81>; 515}; 516 517&L2 { 518 arm,data-latency = <3 3 3>; 519 arm,tag-latency = <2 2 2>; 520 arm,filter-ranges = <0x100000 0xc0000000>; 521 prefetch-data = <1>; 522 prefetch-instr = <1>; 523 arm,shared-override; 524}; 525 526&periph { 527 scu@0 { 528 compatible = "arm,cortex-a9-scu"; 529 reg = <0x0 0x100>; 530 }; 531 532 timer@200 { 533 compatible = "arm,cortex-a9-global-timer"; 534 reg = <0x200 0x20>; 535 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 536 clocks = <&clkc CLKID_PERIPH>; 537 538 /* 539 * the arm_global_timer driver currently does not handle clock 540 * rate changes. Keep it disabled for now. 541 */ 542 status = "disabled"; 543 }; 544 545 timer@600 { 546 compatible = "arm,cortex-a9-twd-timer"; 547 reg = <0x600 0x20>; 548 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 549 clocks = <&clkc CLKID_PERIPH>; 550 }; 551}; 552 553&pwm_ab { 554 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; 555}; 556 557&pwm_cd { 558 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; 559}; 560 561&rtc { 562 compatible = "amlogic,meson8-rtc"; 563 resets = <&reset RESET_RTC>; 564}; 565 566&saradc { 567 compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; 568 clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; 569 clock-names = "clkin", "core"; 570 amlogic,hhi-sysctrl = <&hhi>; 571 nvmem-cells = <&temperature_calib>; 572 nvmem-cell-names = "temperature_calib"; 573}; 574 575&sdhc { 576 compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; 577 clocks = <&xtal>, 578 <&clkc CLKID_FCLK_DIV4>, 579 <&clkc CLKID_FCLK_DIV3>, 580 <&clkc CLKID_FCLK_DIV5>, 581 <&clkc CLKID_SDHC>; 582 clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; 583}; 584 585&sdio { 586 compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; 587 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; 588 clock-names = "core", "clkin"; 589}; 590 591&spifc { 592 clocks = <&clkc CLKID_CLK81>; 593}; 594 595&timer_abcde { 596 clocks = <&xtal>, <&clkc CLKID_CLK81>; 597 clock-names = "xtal", "pclk"; 598}; 599 600&uart_AO { 601 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 602 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>; 603 clock-names = "baud", "xtal", "pclk"; 604}; 605 606&uart_A { 607 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 608 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>; 609 clock-names = "baud", "xtal", "pclk"; 610}; 611 612&uart_B { 613 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 614 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>; 615 clock-names = "baud", "xtal", "pclk"; 616}; 617 618&uart_C { 619 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 620 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>; 621 clock-names = "baud", "xtal", "pclk"; 622}; 623 624&usb0 { 625 compatible = "amlogic,meson8-usb", "snps,dwc2"; 626 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; 627 clock-names = "otg"; 628}; 629 630&usb1 { 631 compatible = "amlogic,meson8-usb", "snps,dwc2"; 632 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 633 clock-names = "otg"; 634}; 635 636&usb0_phy { 637 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; 638 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; 639 clock-names = "usb_general", "usb"; 640 resets = <&reset RESET_USB_OTG>; 641}; 642 643&usb1_phy { 644 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; 645 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; 646 clock-names = "usb_general", "usb"; 647 resets = <&reset RESET_USB_OTG>; 648}; 649