1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27
28 #include "amdgpu.h"
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_ih.h"
31 #include "amdgpu_uvd.h"
32 #include "amdgpu_vce.h"
33 #include "amdgpu_ucode.h"
34 #include "amdgpu_psp.h"
35 #include "atom.h"
36 #include "amd_pcie.h"
37
38 #include "uvd/uvd_7_0_offset.h"
39 #include "gc/gc_9_0_offset.h"
40 #include "gc/gc_9_0_sh_mask.h"
41 #include "sdma0/sdma0_4_0_offset.h"
42 #include "sdma1/sdma1_4_0_offset.h"
43 #include "hdp/hdp_4_0_offset.h"
44 #include "hdp/hdp_4_0_sh_mask.h"
45 #include "smuio/smuio_9_0_offset.h"
46 #include "smuio/smuio_9_0_sh_mask.h"
47 #include "nbio/nbio_7_0_default.h"
48 #include "nbio/nbio_7_0_offset.h"
49 #include "nbio/nbio_7_0_sh_mask.h"
50 #include "nbio/nbio_7_0_smn.h"
51 #include "mp/mp_9_0_offset.h"
52
53 #include "soc15.h"
54 #include "soc15_common.h"
55 #include "gfx_v9_0.h"
56 #include "gmc_v9_0.h"
57 #include "gfxhub_v1_0.h"
58 #include "mmhub_v1_0.h"
59 #include "df_v1_7.h"
60 #include "df_v3_6.h"
61 #include "nbio_v6_1.h"
62 #include "nbio_v7_0.h"
63 #include "nbio_v7_4.h"
64 #include "vega10_ih.h"
65 #include "sdma_v4_0.h"
66 #include "uvd_v7_0.h"
67 #include "vce_v4_0.h"
68 #include "vcn_v1_0.h"
69 #include "vcn_v2_0.h"
70 #include "jpeg_v2_0.h"
71 #include "vcn_v2_5.h"
72 #include "jpeg_v2_5.h"
73 #include "dce_virtual.h"
74 #include "mxgpu_ai.h"
75 #include "amdgpu_smu.h"
76 #include "amdgpu_ras.h"
77 #include "amdgpu_xgmi.h"
78 #include <uapi/linux/kfd_ioctl.h>
79
80 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
81 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
82 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
83 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
84
85 /* for Vega20 register name change */
86 #define mmHDP_MEM_POWER_CTRL 0x00d4
87 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
88 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
89 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
90 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
91 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
92
93 /* for Vega20/arcturus regiter offset change */
94 #define mmROM_INDEX_VG20 0x00e4
95 #define mmROM_INDEX_VG20_BASE_IDX 0
96 #define mmROM_DATA_VG20 0x00e5
97 #define mmROM_DATA_VG20_BASE_IDX 0
98
99 /*
100 * Indirect registers accessor
101 */
soc15_pcie_rreg(struct amdgpu_device * adev,u32 reg)102 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
103 {
104 unsigned long address, data;
105 address = adev->nbio.funcs->get_pcie_index_offset(adev);
106 data = adev->nbio.funcs->get_pcie_data_offset(adev);
107
108 return amdgpu_device_indirect_rreg(adev, address, data, reg);
109 }
110
soc15_pcie_wreg(struct amdgpu_device * adev,u32 reg,u32 v)111 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
112 {
113 unsigned long address, data;
114
115 address = adev->nbio.funcs->get_pcie_index_offset(adev);
116 data = adev->nbio.funcs->get_pcie_data_offset(adev);
117
118 amdgpu_device_indirect_wreg(adev, address, data, reg, v);
119 }
120
soc15_pcie_rreg64(struct amdgpu_device * adev,u32 reg)121 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
122 {
123 unsigned long address, data;
124 address = adev->nbio.funcs->get_pcie_index_offset(adev);
125 data = adev->nbio.funcs->get_pcie_data_offset(adev);
126
127 return amdgpu_device_indirect_rreg64(adev, address, data, reg);
128 }
129
soc15_pcie_wreg64(struct amdgpu_device * adev,u32 reg,u64 v)130 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
131 {
132 unsigned long address, data;
133
134 address = adev->nbio.funcs->get_pcie_index_offset(adev);
135 data = adev->nbio.funcs->get_pcie_data_offset(adev);
136
137 amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
138 }
139
soc15_uvd_ctx_rreg(struct amdgpu_device * adev,u32 reg)140 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
141 {
142 unsigned long flags, address, data;
143 u32 r;
144
145 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
146 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
147
148 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
149 WREG32(address, ((reg) & 0x1ff));
150 r = RREG32(data);
151 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
152 return r;
153 }
154
soc15_uvd_ctx_wreg(struct amdgpu_device * adev,u32 reg,u32 v)155 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
156 {
157 unsigned long flags, address, data;
158
159 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
160 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
161
162 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
163 WREG32(address, ((reg) & 0x1ff));
164 WREG32(data, (v));
165 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
166 }
167
soc15_didt_rreg(struct amdgpu_device * adev,u32 reg)168 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
169 {
170 unsigned long flags, address, data;
171 u32 r;
172
173 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
174 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
175
176 spin_lock_irqsave(&adev->didt_idx_lock, flags);
177 WREG32(address, (reg));
178 r = RREG32(data);
179 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
180 return r;
181 }
182
soc15_didt_wreg(struct amdgpu_device * adev,u32 reg,u32 v)183 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
184 {
185 unsigned long flags, address, data;
186
187 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
188 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
189
190 spin_lock_irqsave(&adev->didt_idx_lock, flags);
191 WREG32(address, (reg));
192 WREG32(data, (v));
193 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
194 }
195
soc15_gc_cac_rreg(struct amdgpu_device * adev,u32 reg)196 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
197 {
198 unsigned long flags;
199 u32 r;
200
201 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
202 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
203 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
204 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
205 return r;
206 }
207
soc15_gc_cac_wreg(struct amdgpu_device * adev,u32 reg,u32 v)208 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
209 {
210 unsigned long flags;
211
212 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
213 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
214 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
215 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
216 }
217
soc15_se_cac_rreg(struct amdgpu_device * adev,u32 reg)218 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
219 {
220 unsigned long flags;
221 u32 r;
222
223 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
224 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
225 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
226 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
227 return r;
228 }
229
soc15_se_cac_wreg(struct amdgpu_device * adev,u32 reg,u32 v)230 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
231 {
232 unsigned long flags;
233
234 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
235 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
236 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
237 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
238 }
239
soc15_get_config_memsize(struct amdgpu_device * adev)240 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
241 {
242 return adev->nbio.funcs->get_memsize(adev);
243 }
244
soc15_get_xclk(struct amdgpu_device * adev)245 static u32 soc15_get_xclk(struct amdgpu_device *adev)
246 {
247 u32 reference_clock = adev->clock.spll.reference_freq;
248
249 if (adev->asic_type == CHIP_RENOIR)
250 return 10000;
251 if (adev->asic_type == CHIP_RAVEN)
252 return reference_clock / 4;
253
254 return reference_clock;
255 }
256
257
soc15_grbm_select(struct amdgpu_device * adev,u32 me,u32 pipe,u32 queue,u32 vmid)258 void soc15_grbm_select(struct amdgpu_device *adev,
259 u32 me, u32 pipe, u32 queue, u32 vmid)
260 {
261 u32 grbm_gfx_cntl = 0;
262 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
263 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
264 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
265 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
266
267 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
268 }
269
soc15_vga_set_state(struct amdgpu_device * adev,bool state)270 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
271 {
272 /* todo */
273 }
274
soc15_read_disabled_bios(struct amdgpu_device * adev)275 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
276 {
277 /* todo */
278 return false;
279 }
280
soc15_read_bios_from_rom(struct amdgpu_device * adev,u8 * bios,u32 length_bytes)281 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
282 u8 *bios, u32 length_bytes)
283 {
284 u32 *dw_ptr;
285 u32 i, length_dw;
286 uint32_t rom_index_offset;
287 uint32_t rom_data_offset;
288
289 if (bios == NULL)
290 return false;
291 if (length_bytes == 0)
292 return false;
293 /* APU vbios image is part of sbios image */
294 if (adev->flags & AMD_IS_APU)
295 return false;
296
297 dw_ptr = (u32 *)bios;
298 length_dw = ALIGN(length_bytes, 4) / 4;
299
300 switch (adev->asic_type) {
301 case CHIP_VEGA20:
302 case CHIP_ARCTURUS:
303 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX_VG20);
304 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA_VG20);
305 break;
306 default:
307 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
308 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
309 break;
310 }
311
312 /* set rom index to 0 */
313 WREG32(rom_index_offset, 0);
314 /* read out the rom data */
315 for (i = 0; i < length_dw; i++)
316 dw_ptr[i] = RREG32(rom_data_offset);
317
318 return true;
319 }
320
321 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
322 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
323 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
324 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
325 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
326 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
327 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
328 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
329 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
330 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
331 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
332 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
333 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
334 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
335 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
336 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
337 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
338 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
339 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
340 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
341 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
342 };
343
soc15_read_indexed_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset)344 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
345 u32 sh_num, u32 reg_offset)
346 {
347 uint32_t val;
348
349 mutex_lock(&adev->grbm_idx_mutex);
350 if (se_num != 0xffffffff || sh_num != 0xffffffff)
351 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
352
353 val = RREG32(reg_offset);
354
355 if (se_num != 0xffffffff || sh_num != 0xffffffff)
356 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
357 mutex_unlock(&adev->grbm_idx_mutex);
358 return val;
359 }
360
soc15_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset)361 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
362 bool indexed, u32 se_num,
363 u32 sh_num, u32 reg_offset)
364 {
365 if (indexed) {
366 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
367 } else {
368 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
369 return adev->gfx.config.gb_addr_config;
370 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
371 return adev->gfx.config.db_debug2;
372 return RREG32(reg_offset);
373 }
374 }
375
soc15_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value)376 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
377 u32 sh_num, u32 reg_offset, u32 *value)
378 {
379 uint32_t i;
380 struct soc15_allowed_register_entry *en;
381
382 *value = 0;
383 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
384 en = &soc15_allowed_read_registers[i];
385 if (adev->reg_offset[en->hwip][en->inst] &&
386 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
387 + en->reg_offset))
388 continue;
389
390 *value = soc15_get_register_value(adev,
391 soc15_allowed_read_registers[i].grbm_indexed,
392 se_num, sh_num, reg_offset);
393 return 0;
394 }
395 return -EINVAL;
396 }
397
398
399 /**
400 * soc15_program_register_sequence - program an array of registers.
401 *
402 * @adev: amdgpu_device pointer
403 * @regs: pointer to the register array
404 * @array_size: size of the register array
405 *
406 * Programs an array or registers with and and or masks.
407 * This is a helper for setting golden registers.
408 */
409
soc15_program_register_sequence(struct amdgpu_device * adev,const struct soc15_reg_golden * regs,const u32 array_size)410 void soc15_program_register_sequence(struct amdgpu_device *adev,
411 const struct soc15_reg_golden *regs,
412 const u32 array_size)
413 {
414 const struct soc15_reg_golden *entry;
415 u32 tmp, reg;
416 int i;
417
418 for (i = 0; i < array_size; ++i) {
419 entry = ®s[i];
420 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
421
422 if (entry->and_mask == 0xffffffff) {
423 tmp = entry->or_mask;
424 } else {
425 tmp = RREG32(reg);
426 tmp &= ~(entry->and_mask);
427 tmp |= (entry->or_mask & entry->and_mask);
428 }
429
430 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
431 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
432 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
433 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
434 WREG32_RLC(reg, tmp);
435 else
436 WREG32(reg, tmp);
437
438 }
439
440 }
441
soc15_asic_mode1_reset(struct amdgpu_device * adev)442 static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
443 {
444 u32 i;
445 int ret = 0;
446
447 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
448
449 dev_info(adev->dev, "GPU mode1 reset\n");
450
451 /* disable BM */
452 pci_clear_master(adev->pdev);
453
454 amdgpu_device_cache_pci_state(adev->pdev);
455
456 ret = psp_gpu_reset(adev);
457 if (ret)
458 dev_err(adev->dev, "GPU mode1 reset failed\n");
459
460 amdgpu_device_load_pci_state(adev->pdev);
461
462 /* wait for asic to come out of reset */
463 for (i = 0; i < adev->usec_timeout; i++) {
464 u32 memsize = adev->nbio.funcs->get_memsize(adev);
465
466 if (memsize != 0xffffffff)
467 break;
468 udelay(1);
469 }
470
471 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
472
473 return ret;
474 }
475
soc15_asic_baco_reset(struct amdgpu_device * adev)476 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
477 {
478 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
479 int ret = 0;
480
481 /* avoid NBIF got stuck when do RAS recovery in BACO reset */
482 if (ras && ras->supported)
483 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
484
485 ret = amdgpu_dpm_baco_reset(adev);
486 if (ret)
487 return ret;
488
489 /* re-enable doorbell interrupt after BACO exit */
490 if (ras && ras->supported)
491 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
492
493 return 0;
494 }
495
496 static enum amd_reset_method
soc15_asic_reset_method(struct amdgpu_device * adev)497 soc15_asic_reset_method(struct amdgpu_device *adev)
498 {
499 bool baco_reset = false;
500 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
501
502 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
503 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
504 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
505 return amdgpu_reset_method;
506
507 if (amdgpu_reset_method != -1)
508 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
509 amdgpu_reset_method);
510
511 switch (adev->asic_type) {
512 case CHIP_RAVEN:
513 case CHIP_RENOIR:
514 return AMD_RESET_METHOD_MODE2;
515 case CHIP_VEGA10:
516 case CHIP_VEGA12:
517 case CHIP_ARCTURUS:
518 baco_reset = amdgpu_dpm_is_baco_supported(adev);
519 break;
520 case CHIP_VEGA20:
521 if (adev->psp.sos_fw_version >= 0x80067)
522 baco_reset = amdgpu_dpm_is_baco_supported(adev);
523
524 /*
525 * 1. PMFW version > 0x284300: all cases use baco
526 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
527 */
528 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
529 baco_reset = false;
530 break;
531 default:
532 break;
533 }
534
535 if (baco_reset)
536 return AMD_RESET_METHOD_BACO;
537 else
538 return AMD_RESET_METHOD_MODE1;
539 }
540
soc15_asic_reset(struct amdgpu_device * adev)541 static int soc15_asic_reset(struct amdgpu_device *adev)
542 {
543 /* original raven doesn't have full asic reset */
544 if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
545 !(adev->apu_flags & AMD_APU_IS_RAVEN2))
546 return 0;
547
548 switch (soc15_asic_reset_method(adev)) {
549 case AMD_RESET_METHOD_BACO:
550 dev_info(adev->dev, "BACO reset\n");
551 return soc15_asic_baco_reset(adev);
552 case AMD_RESET_METHOD_MODE2:
553 dev_info(adev->dev, "MODE2 reset\n");
554 return amdgpu_dpm_mode2_reset(adev);
555 default:
556 dev_info(adev->dev, "MODE1 reset\n");
557 return soc15_asic_mode1_reset(adev);
558 }
559 }
560
soc15_supports_baco(struct amdgpu_device * adev)561 static bool soc15_supports_baco(struct amdgpu_device *adev)
562 {
563 switch (adev->asic_type) {
564 case CHIP_VEGA10:
565 case CHIP_VEGA12:
566 case CHIP_ARCTURUS:
567 return amdgpu_dpm_is_baco_supported(adev);
568 case CHIP_VEGA20:
569 if (adev->psp.sos_fw_version >= 0x80067)
570 return amdgpu_dpm_is_baco_supported(adev);
571 return false;
572 default:
573 return false;
574 }
575 }
576
577 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
578 u32 cntl_reg, u32 status_reg)
579 {
580 return 0;
581 }*/
582
soc15_set_uvd_clocks(struct amdgpu_device * adev,u32 vclk,u32 dclk)583 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
584 {
585 /*int r;
586
587 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
588 if (r)
589 return r;
590
591 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
592 */
593 return 0;
594 }
595
soc15_set_vce_clocks(struct amdgpu_device * adev,u32 evclk,u32 ecclk)596 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
597 {
598 /* todo */
599
600 return 0;
601 }
602
soc15_pcie_gen3_enable(struct amdgpu_device * adev)603 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
604 {
605 if (pci_is_root_bus(adev->pdev->bus))
606 return;
607
608 if (amdgpu_pcie_gen2 == 0)
609 return;
610
611 if (adev->flags & AMD_IS_APU)
612 return;
613
614 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
615 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
616 return;
617
618 /* todo */
619 }
620
soc15_program_aspm(struct amdgpu_device * adev)621 static void soc15_program_aspm(struct amdgpu_device *adev)
622 {
623
624 if (amdgpu_aspm == 0)
625 return;
626
627 /* todo */
628 }
629
soc15_enable_doorbell_aperture(struct amdgpu_device * adev,bool enable)630 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
631 bool enable)
632 {
633 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
634 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
635 }
636
637 static const struct amdgpu_ip_block_version vega10_common_ip_block =
638 {
639 .type = AMD_IP_BLOCK_TYPE_COMMON,
640 .major = 2,
641 .minor = 0,
642 .rev = 0,
643 .funcs = &soc15_common_ip_funcs,
644 };
645
soc15_get_rev_id(struct amdgpu_device * adev)646 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
647 {
648 return adev->nbio.funcs->get_rev_id(adev);
649 }
650
soc15_reg_base_init(struct amdgpu_device * adev)651 static void soc15_reg_base_init(struct amdgpu_device *adev)
652 {
653 int r;
654
655 /* Set IP register base before any HW register access */
656 switch (adev->asic_type) {
657 case CHIP_VEGA10:
658 case CHIP_VEGA12:
659 case CHIP_RAVEN:
660 vega10_reg_base_init(adev);
661 break;
662 case CHIP_RENOIR:
663 /* It's safe to do ip discovery here for Renior,
664 * it doesn't support SRIOV. */
665 if (amdgpu_discovery) {
666 r = amdgpu_discovery_reg_base_init(adev);
667 if (r == 0)
668 break;
669 DRM_WARN("failed to init reg base from ip discovery table, "
670 "fallback to legacy init method\n");
671 }
672 vega10_reg_base_init(adev);
673 break;
674 case CHIP_VEGA20:
675 vega20_reg_base_init(adev);
676 break;
677 case CHIP_ARCTURUS:
678 arct_reg_base_init(adev);
679 break;
680 default:
681 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
682 break;
683 }
684 }
685
soc15_set_virt_ops(struct amdgpu_device * adev)686 void soc15_set_virt_ops(struct amdgpu_device *adev)
687 {
688 adev->virt.ops = &xgpu_ai_virt_ops;
689
690 /* init soc15 reg base early enough so we can
691 * request request full access for sriov before
692 * set_ip_blocks. */
693 soc15_reg_base_init(adev);
694 }
695
soc15_set_ip_blocks(struct amdgpu_device * adev)696 int soc15_set_ip_blocks(struct amdgpu_device *adev)
697 {
698 /* for bare metal case */
699 if (!amdgpu_sriov_vf(adev))
700 soc15_reg_base_init(adev);
701
702 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
703 adev->gmc.xgmi.supported = true;
704
705 if (adev->flags & AMD_IS_APU) {
706 adev->nbio.funcs = &nbio_v7_0_funcs;
707 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
708 } else if (adev->asic_type == CHIP_VEGA20 ||
709 adev->asic_type == CHIP_ARCTURUS) {
710 adev->nbio.funcs = &nbio_v7_4_funcs;
711 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
712 } else {
713 adev->nbio.funcs = &nbio_v6_1_funcs;
714 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
715 }
716
717 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
718 adev->df.funcs = &df_v3_6_funcs;
719 else
720 adev->df.funcs = &df_v1_7_funcs;
721
722 adev->rev_id = soc15_get_rev_id(adev);
723
724 switch (adev->asic_type) {
725 case CHIP_VEGA10:
726 case CHIP_VEGA12:
727 case CHIP_VEGA20:
728 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
729 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
730
731 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
732 if (amdgpu_sriov_vf(adev)) {
733 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
734 if (adev->asic_type == CHIP_VEGA20)
735 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
736 else
737 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
738 }
739 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
740 } else {
741 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
742 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
743 if (adev->asic_type == CHIP_VEGA20)
744 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
745 else
746 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
747 }
748 }
749 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
750 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
751 if (is_support_sw_smu(adev)) {
752 if (!amdgpu_sriov_vf(adev))
753 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
754 } else {
755 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
756 }
757 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
758 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
759 #if defined(CONFIG_DRM_AMD_DC)
760 else if (amdgpu_device_has_dc_support(adev))
761 amdgpu_device_ip_block_add(adev, &dm_ip_block);
762 #endif
763 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
764 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
765 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
766 }
767 break;
768 case CHIP_RAVEN:
769 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
770 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
771 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
772 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
773 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
774 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
775 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
776 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
777 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
778 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
779 #if defined(CONFIG_DRM_AMD_DC)
780 else if (amdgpu_device_has_dc_support(adev))
781 amdgpu_device_ip_block_add(adev, &dm_ip_block);
782 #endif
783 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
784 break;
785 case CHIP_ARCTURUS:
786 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
787 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
788
789 if (amdgpu_sriov_vf(adev)) {
790 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
791 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
792 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
793 } else {
794 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
795 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
796 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
797 }
798
799 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
800 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
801 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
802 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
803 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
804
805 if (amdgpu_sriov_vf(adev)) {
806 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
807 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
808 } else {
809 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
810 }
811 if (!amdgpu_sriov_vf(adev))
812 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
813 break;
814 case CHIP_RENOIR:
815 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
816 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
817 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
818 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
819 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
820 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
821 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
822 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
823 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
824 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
825 #if defined(CONFIG_DRM_AMD_DC)
826 else if (amdgpu_device_has_dc_support(adev))
827 amdgpu_device_ip_block_add(adev, &dm_ip_block);
828 #endif
829 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
830 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
831 break;
832 default:
833 return -EINVAL;
834 }
835
836 return 0;
837 }
838
soc15_flush_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring)839 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
840 {
841 adev->nbio.funcs->hdp_flush(adev, ring);
842 }
843
soc15_invalidate_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring)844 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
845 struct amdgpu_ring *ring)
846 {
847 if (!ring || !ring->funcs->emit_wreg)
848 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
849 else
850 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
851 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
852 }
853
soc15_need_full_reset(struct amdgpu_device * adev)854 static bool soc15_need_full_reset(struct amdgpu_device *adev)
855 {
856 /* change this when we implement soft reset */
857 return true;
858 }
859
vega20_reset_hdp_ras_error_count(struct amdgpu_device * adev)860 static void vega20_reset_hdp_ras_error_count(struct amdgpu_device *adev)
861 {
862 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
863 return;
864 /*read back hdp ras counter to reset it to 0 */
865 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
866 }
867
soc15_get_pcie_usage(struct amdgpu_device * adev,uint64_t * count0,uint64_t * count1)868 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
869 uint64_t *count1)
870 {
871 uint32_t perfctr = 0;
872 uint64_t cnt0_of, cnt1_of;
873 int tmp;
874
875 /* This reports 0 on APUs, so return to avoid writing/reading registers
876 * that may or may not be different from their GPU counterparts
877 */
878 if (adev->flags & AMD_IS_APU)
879 return;
880
881 /* Set the 2 events that we wish to watch, defined above */
882 /* Reg 40 is # received msgs */
883 /* Reg 104 is # of posted requests sent */
884 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
885 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
886
887 /* Write to enable desired perf counters */
888 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
889 /* Zero out and enable the perf counters
890 * Write 0x5:
891 * Bit 0 = Start all counters(1)
892 * Bit 2 = Global counter reset enable(1)
893 */
894 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
895
896 msleep(1000);
897
898 /* Load the shadow and disable the perf counters
899 * Write 0x2:
900 * Bit 0 = Stop counters(0)
901 * Bit 1 = Load the shadow counters(1)
902 */
903 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
904
905 /* Read register values to get any >32bit overflow */
906 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
907 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
908 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
909
910 /* Get the values and add the overflow */
911 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
912 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
913 }
914
vega20_get_pcie_usage(struct amdgpu_device * adev,uint64_t * count0,uint64_t * count1)915 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
916 uint64_t *count1)
917 {
918 uint32_t perfctr = 0;
919 uint64_t cnt0_of, cnt1_of;
920 int tmp;
921
922 /* This reports 0 on APUs, so return to avoid writing/reading registers
923 * that may or may not be different from their GPU counterparts
924 */
925 if (adev->flags & AMD_IS_APU)
926 return;
927
928 /* Set the 2 events that we wish to watch, defined above */
929 /* Reg 40 is # received msgs */
930 /* Reg 108 is # of posted requests sent on VG20 */
931 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
932 EVENT0_SEL, 40);
933 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
934 EVENT1_SEL, 108);
935
936 /* Write to enable desired perf counters */
937 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
938 /* Zero out and enable the perf counters
939 * Write 0x5:
940 * Bit 0 = Start all counters(1)
941 * Bit 2 = Global counter reset enable(1)
942 */
943 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
944
945 msleep(1000);
946
947 /* Load the shadow and disable the perf counters
948 * Write 0x2:
949 * Bit 0 = Stop counters(0)
950 * Bit 1 = Load the shadow counters(1)
951 */
952 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
953
954 /* Read register values to get any >32bit overflow */
955 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
956 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
957 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
958
959 /* Get the values and add the overflow */
960 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
961 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
962 }
963
soc15_need_reset_on_init(struct amdgpu_device * adev)964 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
965 {
966 u32 sol_reg;
967
968 /* Just return false for soc15 GPUs. Reset does not seem to
969 * be necessary.
970 */
971 if (!amdgpu_passthrough(adev))
972 return false;
973
974 if (adev->flags & AMD_IS_APU)
975 return false;
976
977 /* Check sOS sign of life register to confirm sys driver and sOS
978 * are already been loaded.
979 */
980 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
981 if (sol_reg)
982 return true;
983
984 return false;
985 }
986
soc15_get_pcie_replay_count(struct amdgpu_device * adev)987 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
988 {
989 uint64_t nak_r, nak_g;
990
991 /* Get the number of NAKs received and generated */
992 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
993 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
994
995 /* Add the total number of NAKs, i.e the number of replays */
996 return (nak_r + nak_g);
997 }
998
soc15_pre_asic_init(struct amdgpu_device * adev)999 static void soc15_pre_asic_init(struct amdgpu_device *adev)
1000 {
1001 gmc_v9_0_restore_registers(adev);
1002 }
1003
1004 static const struct amdgpu_asic_funcs soc15_asic_funcs =
1005 {
1006 .read_disabled_bios = &soc15_read_disabled_bios,
1007 .read_bios_from_rom = &soc15_read_bios_from_rom,
1008 .read_register = &soc15_read_register,
1009 .reset = &soc15_asic_reset,
1010 .reset_method = &soc15_asic_reset_method,
1011 .set_vga_state = &soc15_vga_set_state,
1012 .get_xclk = &soc15_get_xclk,
1013 .set_uvd_clocks = &soc15_set_uvd_clocks,
1014 .set_vce_clocks = &soc15_set_vce_clocks,
1015 .get_config_memsize = &soc15_get_config_memsize,
1016 .flush_hdp = &soc15_flush_hdp,
1017 .invalidate_hdp = &soc15_invalidate_hdp,
1018 .need_full_reset = &soc15_need_full_reset,
1019 .init_doorbell_index = &vega10_doorbell_index_init,
1020 .get_pcie_usage = &soc15_get_pcie_usage,
1021 .need_reset_on_init = &soc15_need_reset_on_init,
1022 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1023 .supports_baco = &soc15_supports_baco,
1024 .pre_asic_init = &soc15_pre_asic_init,
1025 };
1026
1027 static const struct amdgpu_asic_funcs vega20_asic_funcs =
1028 {
1029 .read_disabled_bios = &soc15_read_disabled_bios,
1030 .read_bios_from_rom = &soc15_read_bios_from_rom,
1031 .read_register = &soc15_read_register,
1032 .reset = &soc15_asic_reset,
1033 .reset_method = &soc15_asic_reset_method,
1034 .set_vga_state = &soc15_vga_set_state,
1035 .get_xclk = &soc15_get_xclk,
1036 .set_uvd_clocks = &soc15_set_uvd_clocks,
1037 .set_vce_clocks = &soc15_set_vce_clocks,
1038 .get_config_memsize = &soc15_get_config_memsize,
1039 .flush_hdp = &soc15_flush_hdp,
1040 .invalidate_hdp = &soc15_invalidate_hdp,
1041 .reset_hdp_ras_error_count = &vega20_reset_hdp_ras_error_count,
1042 .need_full_reset = &soc15_need_full_reset,
1043 .init_doorbell_index = &vega20_doorbell_index_init,
1044 .get_pcie_usage = &vega20_get_pcie_usage,
1045 .need_reset_on_init = &soc15_need_reset_on_init,
1046 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1047 .supports_baco = &soc15_supports_baco,
1048 .pre_asic_init = &soc15_pre_asic_init,
1049 };
1050
soc15_common_early_init(void * handle)1051 static int soc15_common_early_init(void *handle)
1052 {
1053 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1054 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1055
1056 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1057 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1058 adev->smc_rreg = NULL;
1059 adev->smc_wreg = NULL;
1060 adev->pcie_rreg = &soc15_pcie_rreg;
1061 adev->pcie_wreg = &soc15_pcie_wreg;
1062 adev->pcie_rreg64 = &soc15_pcie_rreg64;
1063 adev->pcie_wreg64 = &soc15_pcie_wreg64;
1064 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
1065 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
1066 adev->didt_rreg = &soc15_didt_rreg;
1067 adev->didt_wreg = &soc15_didt_wreg;
1068 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
1069 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
1070 adev->se_cac_rreg = &soc15_se_cac_rreg;
1071 adev->se_cac_wreg = &soc15_se_cac_wreg;
1072
1073
1074 adev->external_rev_id = 0xFF;
1075 switch (adev->asic_type) {
1076 case CHIP_VEGA10:
1077 adev->asic_funcs = &soc15_asic_funcs;
1078 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1079 AMD_CG_SUPPORT_GFX_MGLS |
1080 AMD_CG_SUPPORT_GFX_RLC_LS |
1081 AMD_CG_SUPPORT_GFX_CP_LS |
1082 AMD_CG_SUPPORT_GFX_3D_CGCG |
1083 AMD_CG_SUPPORT_GFX_3D_CGLS |
1084 AMD_CG_SUPPORT_GFX_CGCG |
1085 AMD_CG_SUPPORT_GFX_CGLS |
1086 AMD_CG_SUPPORT_BIF_MGCG |
1087 AMD_CG_SUPPORT_BIF_LS |
1088 AMD_CG_SUPPORT_HDP_LS |
1089 AMD_CG_SUPPORT_DRM_MGCG |
1090 AMD_CG_SUPPORT_DRM_LS |
1091 AMD_CG_SUPPORT_ROM_MGCG |
1092 AMD_CG_SUPPORT_DF_MGCG |
1093 AMD_CG_SUPPORT_SDMA_MGCG |
1094 AMD_CG_SUPPORT_SDMA_LS |
1095 AMD_CG_SUPPORT_MC_MGCG |
1096 AMD_CG_SUPPORT_MC_LS;
1097 adev->pg_flags = 0;
1098 adev->external_rev_id = 0x1;
1099 break;
1100 case CHIP_VEGA12:
1101 adev->asic_funcs = &soc15_asic_funcs;
1102 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1103 AMD_CG_SUPPORT_GFX_MGLS |
1104 AMD_CG_SUPPORT_GFX_CGCG |
1105 AMD_CG_SUPPORT_GFX_CGLS |
1106 AMD_CG_SUPPORT_GFX_3D_CGCG |
1107 AMD_CG_SUPPORT_GFX_3D_CGLS |
1108 AMD_CG_SUPPORT_GFX_CP_LS |
1109 AMD_CG_SUPPORT_MC_LS |
1110 AMD_CG_SUPPORT_MC_MGCG |
1111 AMD_CG_SUPPORT_SDMA_MGCG |
1112 AMD_CG_SUPPORT_SDMA_LS |
1113 AMD_CG_SUPPORT_BIF_MGCG |
1114 AMD_CG_SUPPORT_BIF_LS |
1115 AMD_CG_SUPPORT_HDP_MGCG |
1116 AMD_CG_SUPPORT_HDP_LS |
1117 AMD_CG_SUPPORT_ROM_MGCG |
1118 AMD_CG_SUPPORT_VCE_MGCG |
1119 AMD_CG_SUPPORT_UVD_MGCG;
1120 adev->pg_flags = 0;
1121 adev->external_rev_id = adev->rev_id + 0x14;
1122 break;
1123 case CHIP_VEGA20:
1124 adev->asic_funcs = &vega20_asic_funcs;
1125 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1126 AMD_CG_SUPPORT_GFX_MGLS |
1127 AMD_CG_SUPPORT_GFX_CGCG |
1128 AMD_CG_SUPPORT_GFX_CGLS |
1129 AMD_CG_SUPPORT_GFX_3D_CGCG |
1130 AMD_CG_SUPPORT_GFX_3D_CGLS |
1131 AMD_CG_SUPPORT_GFX_CP_LS |
1132 AMD_CG_SUPPORT_MC_LS |
1133 AMD_CG_SUPPORT_MC_MGCG |
1134 AMD_CG_SUPPORT_SDMA_MGCG |
1135 AMD_CG_SUPPORT_SDMA_LS |
1136 AMD_CG_SUPPORT_BIF_MGCG |
1137 AMD_CG_SUPPORT_BIF_LS |
1138 AMD_CG_SUPPORT_HDP_MGCG |
1139 AMD_CG_SUPPORT_HDP_LS |
1140 AMD_CG_SUPPORT_ROM_MGCG |
1141 AMD_CG_SUPPORT_VCE_MGCG |
1142 AMD_CG_SUPPORT_UVD_MGCG;
1143 adev->pg_flags = 0;
1144 adev->external_rev_id = adev->rev_id + 0x28;
1145 break;
1146 case CHIP_RAVEN:
1147 adev->asic_funcs = &soc15_asic_funcs;
1148 if (adev->pdev->device == 0x15dd)
1149 adev->apu_flags |= AMD_APU_IS_RAVEN;
1150 if (adev->pdev->device == 0x15d8)
1151 adev->apu_flags |= AMD_APU_IS_PICASSO;
1152 if (adev->rev_id >= 0x8)
1153 adev->apu_flags |= AMD_APU_IS_RAVEN2;
1154
1155 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1156 adev->external_rev_id = adev->rev_id + 0x79;
1157 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1158 adev->external_rev_id = adev->rev_id + 0x41;
1159 else if (adev->rev_id == 1)
1160 adev->external_rev_id = adev->rev_id + 0x20;
1161 else
1162 adev->external_rev_id = adev->rev_id + 0x01;
1163
1164 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1165 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1166 AMD_CG_SUPPORT_GFX_MGLS |
1167 AMD_CG_SUPPORT_GFX_CP_LS |
1168 AMD_CG_SUPPORT_GFX_3D_CGCG |
1169 AMD_CG_SUPPORT_GFX_3D_CGLS |
1170 AMD_CG_SUPPORT_GFX_CGCG |
1171 AMD_CG_SUPPORT_GFX_CGLS |
1172 AMD_CG_SUPPORT_BIF_LS |
1173 AMD_CG_SUPPORT_HDP_LS |
1174 AMD_CG_SUPPORT_ROM_MGCG |
1175 AMD_CG_SUPPORT_MC_MGCG |
1176 AMD_CG_SUPPORT_MC_LS |
1177 AMD_CG_SUPPORT_SDMA_MGCG |
1178 AMD_CG_SUPPORT_SDMA_LS |
1179 AMD_CG_SUPPORT_VCN_MGCG;
1180
1181 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1182 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
1183 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1184 AMD_CG_SUPPORT_GFX_MGLS |
1185 AMD_CG_SUPPORT_GFX_CP_LS |
1186 AMD_CG_SUPPORT_GFX_3D_CGLS |
1187 AMD_CG_SUPPORT_GFX_CGCG |
1188 AMD_CG_SUPPORT_GFX_CGLS |
1189 AMD_CG_SUPPORT_BIF_LS |
1190 AMD_CG_SUPPORT_HDP_LS |
1191 AMD_CG_SUPPORT_ROM_MGCG |
1192 AMD_CG_SUPPORT_MC_MGCG |
1193 AMD_CG_SUPPORT_MC_LS |
1194 AMD_CG_SUPPORT_SDMA_MGCG |
1195 AMD_CG_SUPPORT_SDMA_LS;
1196
1197 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1198 AMD_PG_SUPPORT_MMHUB |
1199 AMD_PG_SUPPORT_VCN;
1200 } else {
1201 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1202 AMD_CG_SUPPORT_GFX_MGLS |
1203 AMD_CG_SUPPORT_GFX_RLC_LS |
1204 AMD_CG_SUPPORT_GFX_CP_LS |
1205 AMD_CG_SUPPORT_GFX_3D_CGLS |
1206 AMD_CG_SUPPORT_GFX_CGCG |
1207 AMD_CG_SUPPORT_GFX_CGLS |
1208 AMD_CG_SUPPORT_BIF_MGCG |
1209 AMD_CG_SUPPORT_BIF_LS |
1210 AMD_CG_SUPPORT_HDP_MGCG |
1211 AMD_CG_SUPPORT_HDP_LS |
1212 AMD_CG_SUPPORT_DRM_MGCG |
1213 AMD_CG_SUPPORT_DRM_LS |
1214 AMD_CG_SUPPORT_ROM_MGCG |
1215 AMD_CG_SUPPORT_MC_MGCG |
1216 AMD_CG_SUPPORT_MC_LS |
1217 AMD_CG_SUPPORT_SDMA_MGCG |
1218 AMD_CG_SUPPORT_SDMA_LS |
1219 AMD_CG_SUPPORT_VCN_MGCG;
1220
1221 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1222 }
1223 break;
1224 case CHIP_ARCTURUS:
1225 adev->asic_funcs = &vega20_asic_funcs;
1226 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1227 AMD_CG_SUPPORT_GFX_MGLS |
1228 AMD_CG_SUPPORT_GFX_CGCG |
1229 AMD_CG_SUPPORT_GFX_CGLS |
1230 AMD_CG_SUPPORT_GFX_CP_LS |
1231 AMD_CG_SUPPORT_HDP_MGCG |
1232 AMD_CG_SUPPORT_HDP_LS |
1233 AMD_CG_SUPPORT_SDMA_MGCG |
1234 AMD_CG_SUPPORT_SDMA_LS |
1235 AMD_CG_SUPPORT_MC_MGCG |
1236 AMD_CG_SUPPORT_MC_LS |
1237 AMD_CG_SUPPORT_IH_CG |
1238 AMD_CG_SUPPORT_VCN_MGCG |
1239 AMD_CG_SUPPORT_JPEG_MGCG;
1240 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1241 adev->external_rev_id = adev->rev_id + 0x32;
1242 break;
1243 case CHIP_RENOIR:
1244 adev->asic_funcs = &soc15_asic_funcs;
1245 if ((adev->pdev->device == 0x1636) ||
1246 (adev->pdev->device == 0x164c))
1247 adev->apu_flags |= AMD_APU_IS_RENOIR;
1248 else
1249 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1250
1251 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1252 adev->external_rev_id = adev->rev_id + 0x91;
1253 else
1254 adev->external_rev_id = adev->rev_id + 0xa1;
1255 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1256 AMD_CG_SUPPORT_GFX_MGLS |
1257 AMD_CG_SUPPORT_GFX_3D_CGCG |
1258 AMD_CG_SUPPORT_GFX_3D_CGLS |
1259 AMD_CG_SUPPORT_GFX_CGCG |
1260 AMD_CG_SUPPORT_GFX_CGLS |
1261 AMD_CG_SUPPORT_GFX_CP_LS |
1262 AMD_CG_SUPPORT_MC_MGCG |
1263 AMD_CG_SUPPORT_MC_LS |
1264 AMD_CG_SUPPORT_SDMA_MGCG |
1265 AMD_CG_SUPPORT_SDMA_LS |
1266 AMD_CG_SUPPORT_BIF_LS |
1267 AMD_CG_SUPPORT_HDP_LS |
1268 AMD_CG_SUPPORT_ROM_MGCG |
1269 AMD_CG_SUPPORT_VCN_MGCG |
1270 AMD_CG_SUPPORT_JPEG_MGCG |
1271 AMD_CG_SUPPORT_IH_CG |
1272 AMD_CG_SUPPORT_ATHUB_LS |
1273 AMD_CG_SUPPORT_ATHUB_MGCG |
1274 AMD_CG_SUPPORT_DF_MGCG;
1275 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1276 AMD_PG_SUPPORT_VCN |
1277 AMD_PG_SUPPORT_JPEG |
1278 AMD_PG_SUPPORT_VCN_DPG;
1279 break;
1280 default:
1281 /* FIXME: not supported yet */
1282 return -EINVAL;
1283 }
1284
1285 if (amdgpu_sriov_vf(adev)) {
1286 amdgpu_virt_init_setting(adev);
1287 xgpu_ai_mailbox_set_irq_funcs(adev);
1288 }
1289
1290 return 0;
1291 }
1292
soc15_common_late_init(void * handle)1293 static int soc15_common_late_init(void *handle)
1294 {
1295 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1296 int r = 0;
1297
1298 if (amdgpu_sriov_vf(adev))
1299 xgpu_ai_mailbox_get_irq(adev);
1300
1301 if (adev->asic_funcs &&
1302 adev->asic_funcs->reset_hdp_ras_error_count)
1303 adev->asic_funcs->reset_hdp_ras_error_count(adev);
1304
1305 if (adev->nbio.funcs->ras_late_init)
1306 r = adev->nbio.funcs->ras_late_init(adev);
1307
1308 return r;
1309 }
1310
soc15_common_sw_init(void * handle)1311 static int soc15_common_sw_init(void *handle)
1312 {
1313 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1314
1315 if (amdgpu_sriov_vf(adev))
1316 xgpu_ai_mailbox_add_irq_id(adev);
1317
1318 adev->df.funcs->sw_init(adev);
1319
1320 return 0;
1321 }
1322
soc15_common_sw_fini(void * handle)1323 static int soc15_common_sw_fini(void *handle)
1324 {
1325 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1326
1327 amdgpu_nbio_ras_fini(adev);
1328 adev->df.funcs->sw_fini(adev);
1329 return 0;
1330 }
1331
soc15_doorbell_range_init(struct amdgpu_device * adev)1332 static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1333 {
1334 int i;
1335 struct amdgpu_ring *ring;
1336
1337 /* sdma/ih doorbell range are programed by hypervisor */
1338 if (!amdgpu_sriov_vf(adev)) {
1339 for (i = 0; i < adev->sdma.num_instances; i++) {
1340 ring = &adev->sdma.instance[i].ring;
1341 adev->nbio.funcs->sdma_doorbell_range(adev, i,
1342 ring->use_doorbell, ring->doorbell_index,
1343 adev->doorbell_index.sdma_doorbell_range);
1344 }
1345
1346 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1347 adev->irq.ih.doorbell_index);
1348 }
1349 }
1350
soc15_common_hw_init(void * handle)1351 static int soc15_common_hw_init(void *handle)
1352 {
1353 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1354
1355 /* enable pcie gen2/3 link */
1356 soc15_pcie_gen3_enable(adev);
1357 /* enable aspm */
1358 soc15_program_aspm(adev);
1359 /* setup nbio registers */
1360 adev->nbio.funcs->init_registers(adev);
1361 /* remap HDP registers to a hole in mmio space,
1362 * for the purpose of expose those registers
1363 * to process space
1364 */
1365 if (adev->nbio.funcs->remap_hdp_registers)
1366 adev->nbio.funcs->remap_hdp_registers(adev);
1367
1368 /* enable the doorbell aperture */
1369 soc15_enable_doorbell_aperture(adev, true);
1370 /* HW doorbell routing policy: doorbell writing not
1371 * in SDMA/IH/MM/ACV range will be routed to CP. So
1372 * we need to init SDMA/IH/MM/ACV doorbell range prior
1373 * to CP ip block init and ring test.
1374 */
1375 soc15_doorbell_range_init(adev);
1376
1377 return 0;
1378 }
1379
soc15_common_hw_fini(void * handle)1380 static int soc15_common_hw_fini(void *handle)
1381 {
1382 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1383
1384 /* disable the doorbell aperture */
1385 soc15_enable_doorbell_aperture(adev, false);
1386 if (amdgpu_sriov_vf(adev))
1387 xgpu_ai_mailbox_put_irq(adev);
1388
1389 if (adev->nbio.ras_if &&
1390 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1391 if (adev->nbio.funcs->init_ras_controller_interrupt)
1392 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1393 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)
1394 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1395 }
1396
1397 return 0;
1398 }
1399
soc15_common_suspend(void * handle)1400 static int soc15_common_suspend(void *handle)
1401 {
1402 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1403
1404 return soc15_common_hw_fini(adev);
1405 }
1406
soc15_common_resume(void * handle)1407 static int soc15_common_resume(void *handle)
1408 {
1409 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1410
1411 return soc15_common_hw_init(adev);
1412 }
1413
soc15_common_is_idle(void * handle)1414 static bool soc15_common_is_idle(void *handle)
1415 {
1416 return true;
1417 }
1418
soc15_common_wait_for_idle(void * handle)1419 static int soc15_common_wait_for_idle(void *handle)
1420 {
1421 return 0;
1422 }
1423
soc15_common_soft_reset(void * handle)1424 static int soc15_common_soft_reset(void *handle)
1425 {
1426 return 0;
1427 }
1428
soc15_update_hdp_light_sleep(struct amdgpu_device * adev,bool enable)1429 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1430 {
1431 uint32_t def, data;
1432
1433 if (adev->asic_type == CHIP_VEGA20 ||
1434 adev->asic_type == CHIP_ARCTURUS ||
1435 adev->asic_type == CHIP_RENOIR) {
1436 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1437
1438 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1439 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1440 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1441 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1442 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1443 else
1444 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1445 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1446 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1447 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
1448
1449 if (def != data)
1450 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1451 } else {
1452 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1453
1454 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1455 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1456 else
1457 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1458
1459 if (def != data)
1460 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1461 }
1462 }
1463
soc15_update_drm_clock_gating(struct amdgpu_device * adev,bool enable)1464 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1465 {
1466 uint32_t def, data;
1467
1468 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1469
1470 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1471 data &= ~(0x01000000 |
1472 0x02000000 |
1473 0x04000000 |
1474 0x08000000 |
1475 0x10000000 |
1476 0x20000000 |
1477 0x40000000 |
1478 0x80000000);
1479 else
1480 data |= (0x01000000 |
1481 0x02000000 |
1482 0x04000000 |
1483 0x08000000 |
1484 0x10000000 |
1485 0x20000000 |
1486 0x40000000 |
1487 0x80000000);
1488
1489 if (def != data)
1490 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1491 }
1492
soc15_update_drm_light_sleep(struct amdgpu_device * adev,bool enable)1493 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1494 {
1495 uint32_t def, data;
1496
1497 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1498
1499 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1500 data |= 1;
1501 else
1502 data &= ~1;
1503
1504 if (def != data)
1505 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1506 }
1507
soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)1508 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1509 bool enable)
1510 {
1511 uint32_t def, data;
1512
1513 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1514
1515 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1516 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1517 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1518 else
1519 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1520 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1521
1522 if (def != data)
1523 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1524 }
1525
soc15_common_set_clockgating_state(void * handle,enum amd_clockgating_state state)1526 static int soc15_common_set_clockgating_state(void *handle,
1527 enum amd_clockgating_state state)
1528 {
1529 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1530
1531 if (amdgpu_sriov_vf(adev))
1532 return 0;
1533
1534 switch (adev->asic_type) {
1535 case CHIP_VEGA10:
1536 case CHIP_VEGA12:
1537 case CHIP_VEGA20:
1538 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1539 state == AMD_CG_STATE_GATE);
1540 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1541 state == AMD_CG_STATE_GATE);
1542 soc15_update_hdp_light_sleep(adev,
1543 state == AMD_CG_STATE_GATE);
1544 soc15_update_drm_clock_gating(adev,
1545 state == AMD_CG_STATE_GATE);
1546 soc15_update_drm_light_sleep(adev,
1547 state == AMD_CG_STATE_GATE);
1548 soc15_update_rom_medium_grain_clock_gating(adev,
1549 state == AMD_CG_STATE_GATE);
1550 adev->df.funcs->update_medium_grain_clock_gating(adev,
1551 state == AMD_CG_STATE_GATE);
1552 break;
1553 case CHIP_RAVEN:
1554 case CHIP_RENOIR:
1555 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1556 state == AMD_CG_STATE_GATE);
1557 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1558 state == AMD_CG_STATE_GATE);
1559 soc15_update_hdp_light_sleep(adev,
1560 state == AMD_CG_STATE_GATE);
1561 soc15_update_drm_clock_gating(adev,
1562 state == AMD_CG_STATE_GATE);
1563 soc15_update_drm_light_sleep(adev,
1564 state == AMD_CG_STATE_GATE);
1565 soc15_update_rom_medium_grain_clock_gating(adev,
1566 state == AMD_CG_STATE_GATE);
1567 break;
1568 case CHIP_ARCTURUS:
1569 soc15_update_hdp_light_sleep(adev,
1570 state == AMD_CG_STATE_GATE);
1571 break;
1572 default:
1573 break;
1574 }
1575 return 0;
1576 }
1577
soc15_common_get_clockgating_state(void * handle,u32 * flags)1578 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1579 {
1580 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1581 int data;
1582
1583 if (amdgpu_sriov_vf(adev))
1584 *flags = 0;
1585
1586 adev->nbio.funcs->get_clockgating_state(adev, flags);
1587
1588 /* AMD_CG_SUPPORT_HDP_LS */
1589 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1590 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1591 *flags |= AMD_CG_SUPPORT_HDP_LS;
1592
1593 /* AMD_CG_SUPPORT_DRM_MGCG */
1594 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1595 if (!(data & 0x01000000))
1596 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1597
1598 /* AMD_CG_SUPPORT_DRM_LS */
1599 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1600 if (data & 0x1)
1601 *flags |= AMD_CG_SUPPORT_DRM_LS;
1602
1603 /* AMD_CG_SUPPORT_ROM_MGCG */
1604 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1605 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1606 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1607
1608 adev->df.funcs->get_clockgating_state(adev, flags);
1609 }
1610
soc15_common_set_powergating_state(void * handle,enum amd_powergating_state state)1611 static int soc15_common_set_powergating_state(void *handle,
1612 enum amd_powergating_state state)
1613 {
1614 /* todo */
1615 return 0;
1616 }
1617
1618 const struct amd_ip_funcs soc15_common_ip_funcs = {
1619 .name = "soc15_common",
1620 .early_init = soc15_common_early_init,
1621 .late_init = soc15_common_late_init,
1622 .sw_init = soc15_common_sw_init,
1623 .sw_fini = soc15_common_sw_fini,
1624 .hw_init = soc15_common_hw_init,
1625 .hw_fini = soc15_common_hw_fini,
1626 .suspend = soc15_common_suspend,
1627 .resume = soc15_common_resume,
1628 .is_idle = soc15_common_is_idle,
1629 .wait_for_idle = soc15_common_wait_for_idle,
1630 .soft_reset = soc15_common_soft_reset,
1631 .set_clockgating_state = soc15_common_set_clockgating_state,
1632 .set_powergating_state = soc15_common_set_powergating_state,
1633 .get_clockgating_state= soc15_common_get_clockgating_state,
1634 };
1635