1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * i.MX drm driver - LVDS display bridge
4 *
5 * Copyright (C) 2012 Sascha Hauer, Pengutronix
6 */
7
8 #include <linux/clk.h>
9 #include <linux/component.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/of_graph.h>
15 #include <linux/regmap.h>
16 #include <linux/videodev2.h>
17
18 #include <video/of_display_timing.h>
19 #include <video/of_videomode.h>
20
21 #include <drm/drm_atomic.h>
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_bridge.h>
24 #include <drm/drm_fb_helper.h>
25 #include <drm/drm_of.h>
26 #include <drm/drm_panel.h>
27 #include <drm/drm_print.h>
28 #include <drm/drm_probe_helper.h>
29 #include <drm/drm_simple_kms_helper.h>
30
31 #include "imx-drm.h"
32
33 #define DRIVER_NAME "imx-ldb"
34
35 #define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
36 #define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
37 #define LDB_CH0_MODE_EN_MASK (3 << 0)
38 #define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
39 #define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
40 #define LDB_CH1_MODE_EN_MASK (3 << 2)
41 #define LDB_SPLIT_MODE_EN (1 << 4)
42 #define LDB_DATA_WIDTH_CH0_24 (1 << 5)
43 #define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
44 #define LDB_DATA_WIDTH_CH1_24 (1 << 7)
45 #define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
46 #define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
47 #define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
48 #define LDB_BGREF_RMODE_INT (1 << 15)
49
50 struct imx_ldb;
51
52 struct imx_ldb_channel {
53 struct imx_ldb *ldb;
54 struct drm_connector connector;
55 struct drm_encoder encoder;
56
57 /* Defines what is connected to the ldb, only one at a time */
58 struct drm_panel *panel;
59 struct drm_bridge *bridge;
60
61 struct device_node *child;
62 struct i2c_adapter *ddc;
63 int chno;
64 void *edid;
65 struct drm_display_mode mode;
66 int mode_valid;
67 u32 bus_format;
68 u32 bus_flags;
69 };
70
con_to_imx_ldb_ch(struct drm_connector * c)71 static inline struct imx_ldb_channel *con_to_imx_ldb_ch(struct drm_connector *c)
72 {
73 return container_of(c, struct imx_ldb_channel, connector);
74 }
75
enc_to_imx_ldb_ch(struct drm_encoder * e)76 static inline struct imx_ldb_channel *enc_to_imx_ldb_ch(struct drm_encoder *e)
77 {
78 return container_of(e, struct imx_ldb_channel, encoder);
79 }
80
81 struct bus_mux {
82 int reg;
83 int shift;
84 int mask;
85 };
86
87 struct imx_ldb {
88 struct regmap *regmap;
89 struct device *dev;
90 struct imx_ldb_channel channel[2];
91 struct clk *clk[2]; /* our own clock */
92 struct clk *clk_sel[4]; /* parent of display clock */
93 struct clk *clk_parent[4]; /* original parent of clk_sel */
94 struct clk *clk_pll[2]; /* upstream clock we can adjust */
95 u32 ldb_ctrl;
96 const struct bus_mux *lvds_mux;
97 };
98
imx_ldb_ch_set_bus_format(struct imx_ldb_channel * imx_ldb_ch,u32 bus_format)99 static void imx_ldb_ch_set_bus_format(struct imx_ldb_channel *imx_ldb_ch,
100 u32 bus_format)
101 {
102 struct imx_ldb *ldb = imx_ldb_ch->ldb;
103 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
104
105 switch (bus_format) {
106 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
107 break;
108 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
109 if (imx_ldb_ch->chno == 0 || dual)
110 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
111 if (imx_ldb_ch->chno == 1 || dual)
112 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
113 break;
114 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
115 if (imx_ldb_ch->chno == 0 || dual)
116 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
117 LDB_BIT_MAP_CH0_JEIDA;
118 if (imx_ldb_ch->chno == 1 || dual)
119 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
120 LDB_BIT_MAP_CH1_JEIDA;
121 break;
122 }
123 }
124
imx_ldb_connector_get_modes(struct drm_connector * connector)125 static int imx_ldb_connector_get_modes(struct drm_connector *connector)
126 {
127 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
128 int num_modes;
129
130 num_modes = drm_panel_get_modes(imx_ldb_ch->panel, connector);
131 if (num_modes > 0)
132 return num_modes;
133
134 if (!imx_ldb_ch->edid && imx_ldb_ch->ddc)
135 imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc);
136
137 if (imx_ldb_ch->edid) {
138 drm_connector_update_edid_property(connector,
139 imx_ldb_ch->edid);
140 num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
141 }
142
143 if (imx_ldb_ch->mode_valid) {
144 struct drm_display_mode *mode;
145
146 mode = drm_mode_create(connector->dev);
147 if (!mode)
148 return -EINVAL;
149 drm_mode_copy(mode, &imx_ldb_ch->mode);
150 mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
151 drm_mode_probed_add(connector, mode);
152 num_modes++;
153 }
154
155 return num_modes;
156 }
157
imx_ldb_set_clock(struct imx_ldb * ldb,int mux,int chno,unsigned long serial_clk,unsigned long di_clk)158 static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
159 unsigned long serial_clk, unsigned long di_clk)
160 {
161 int ret;
162
163 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
164 clk_get_rate(ldb->clk_pll[chno]), serial_clk);
165 clk_set_rate(ldb->clk_pll[chno], serial_clk);
166
167 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
168 clk_get_rate(ldb->clk_pll[chno]));
169
170 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
171 clk_get_rate(ldb->clk[chno]),
172 (long int)di_clk);
173 clk_set_rate(ldb->clk[chno], di_clk);
174
175 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
176 clk_get_rate(ldb->clk[chno]));
177
178 /* set display clock mux to LDB input clock */
179 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
180 if (ret)
181 dev_err(ldb->dev,
182 "unable to set di%d parent clock to ldb_di%d\n", mux,
183 chno);
184 }
185
imx_ldb_encoder_enable(struct drm_encoder * encoder)186 static void imx_ldb_encoder_enable(struct drm_encoder *encoder)
187 {
188 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
189 struct imx_ldb *ldb = imx_ldb_ch->ldb;
190 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
191 int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
192
193 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
194 dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);
195 return;
196 }
197
198 drm_panel_prepare(imx_ldb_ch->panel);
199
200 if (dual) {
201 clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]);
202 clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]);
203
204 clk_prepare_enable(ldb->clk[0]);
205 clk_prepare_enable(ldb->clk[1]);
206 } else {
207 clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]);
208 }
209
210 if (imx_ldb_ch == &ldb->channel[0] || dual) {
211 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
212 if (mux == 0 || ldb->lvds_mux)
213 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
214 else if (mux == 1)
215 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
216 }
217 if (imx_ldb_ch == &ldb->channel[1] || dual) {
218 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
219 if (mux == 1 || ldb->lvds_mux)
220 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
221 else if (mux == 0)
222 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
223 }
224
225 if (ldb->lvds_mux) {
226 const struct bus_mux *lvds_mux = NULL;
227
228 if (imx_ldb_ch == &ldb->channel[0])
229 lvds_mux = &ldb->lvds_mux[0];
230 else if (imx_ldb_ch == &ldb->channel[1])
231 lvds_mux = &ldb->lvds_mux[1];
232
233 regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
234 mux << lvds_mux->shift);
235 }
236
237 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
238
239 drm_panel_enable(imx_ldb_ch->panel);
240 }
241
242 static void
imx_ldb_encoder_atomic_mode_set(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * connector_state)243 imx_ldb_encoder_atomic_mode_set(struct drm_encoder *encoder,
244 struct drm_crtc_state *crtc_state,
245 struct drm_connector_state *connector_state)
246 {
247 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
248 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
249 struct imx_ldb *ldb = imx_ldb_ch->ldb;
250 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
251 unsigned long serial_clk;
252 unsigned long di_clk = mode->clock * 1000;
253 int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
254 u32 bus_format = imx_ldb_ch->bus_format;
255
256 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
257 dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);
258 return;
259 }
260
261 if (mode->clock > 170000) {
262 dev_warn(ldb->dev,
263 "%s: mode exceeds 170 MHz pixel clock\n", __func__);
264 }
265 if (mode->clock > 85000 && !dual) {
266 dev_warn(ldb->dev,
267 "%s: mode exceeds 85 MHz pixel clock\n", __func__);
268 }
269
270 if (dual) {
271 serial_clk = 3500UL * mode->clock;
272 imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
273 imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
274 } else {
275 serial_clk = 7000UL * mode->clock;
276 imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
277 di_clk);
278 }
279
280 /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
281 if (imx_ldb_ch == &ldb->channel[0] || dual) {
282 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
283 ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
284 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
285 ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
286 }
287 if (imx_ldb_ch == &ldb->channel[1] || dual) {
288 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
289 ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
290 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
291 ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
292 }
293
294 if (!bus_format) {
295 struct drm_connector *connector = connector_state->connector;
296 struct drm_display_info *di = &connector->display_info;
297
298 if (di->num_bus_formats)
299 bus_format = di->bus_formats[0];
300 }
301 imx_ldb_ch_set_bus_format(imx_ldb_ch, bus_format);
302 }
303
imx_ldb_encoder_disable(struct drm_encoder * encoder)304 static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
305 {
306 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
307 struct imx_ldb *ldb = imx_ldb_ch->ldb;
308 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
309 int mux, ret;
310
311 drm_panel_disable(imx_ldb_ch->panel);
312
313 if (imx_ldb_ch == &ldb->channel[0] || dual)
314 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
315 if (imx_ldb_ch == &ldb->channel[1] || dual)
316 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
317
318 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
319
320 if (dual) {
321 clk_disable_unprepare(ldb->clk[0]);
322 clk_disable_unprepare(ldb->clk[1]);
323 }
324
325 if (ldb->lvds_mux) {
326 const struct bus_mux *lvds_mux = NULL;
327
328 if (imx_ldb_ch == &ldb->channel[0])
329 lvds_mux = &ldb->lvds_mux[0];
330 else if (imx_ldb_ch == &ldb->channel[1])
331 lvds_mux = &ldb->lvds_mux[1];
332
333 regmap_read(ldb->regmap, lvds_mux->reg, &mux);
334 mux &= lvds_mux->mask;
335 mux >>= lvds_mux->shift;
336 } else {
337 mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1;
338 }
339
340 /* set display clock mux back to original input clock */
341 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);
342 if (ret)
343 dev_err(ldb->dev,
344 "unable to set di%d parent clock to original parent\n",
345 mux);
346
347 drm_panel_unprepare(imx_ldb_ch->panel);
348 }
349
imx_ldb_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)350 static int imx_ldb_encoder_atomic_check(struct drm_encoder *encoder,
351 struct drm_crtc_state *crtc_state,
352 struct drm_connector_state *conn_state)
353 {
354 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
355 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
356 struct drm_display_info *di = &conn_state->connector->display_info;
357 u32 bus_format = imx_ldb_ch->bus_format;
358
359 /* Bus format description in DT overrides connector display info. */
360 if (!bus_format && di->num_bus_formats) {
361 bus_format = di->bus_formats[0];
362 imx_crtc_state->bus_flags = di->bus_flags;
363 } else {
364 bus_format = imx_ldb_ch->bus_format;
365 imx_crtc_state->bus_flags = imx_ldb_ch->bus_flags;
366 }
367 switch (bus_format) {
368 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
369 imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB666_1X18;
370 break;
371 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
372 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
373 imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
374 break;
375 default:
376 return -EINVAL;
377 }
378
379 imx_crtc_state->di_hsync_pin = 2;
380 imx_crtc_state->di_vsync_pin = 3;
381
382 return 0;
383 }
384
385
386 static const struct drm_connector_funcs imx_ldb_connector_funcs = {
387 .fill_modes = drm_helper_probe_single_connector_modes,
388 .destroy = imx_drm_connector_destroy,
389 .reset = drm_atomic_helper_connector_reset,
390 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
391 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
392 };
393
394 static const struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
395 .get_modes = imx_ldb_connector_get_modes,
396 };
397
398 static const struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
399 .atomic_mode_set = imx_ldb_encoder_atomic_mode_set,
400 .enable = imx_ldb_encoder_enable,
401 .disable = imx_ldb_encoder_disable,
402 .atomic_check = imx_ldb_encoder_atomic_check,
403 };
404
imx_ldb_get_clk(struct imx_ldb * ldb,int chno)405 static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
406 {
407 char clkname[16];
408
409 snprintf(clkname, sizeof(clkname), "di%d", chno);
410 ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
411 if (IS_ERR(ldb->clk[chno]))
412 return PTR_ERR(ldb->clk[chno]);
413
414 snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
415 ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
416
417 return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
418 }
419
imx_ldb_register(struct drm_device * drm,struct imx_ldb_channel * imx_ldb_ch)420 static int imx_ldb_register(struct drm_device *drm,
421 struct imx_ldb_channel *imx_ldb_ch)
422 {
423 struct imx_ldb *ldb = imx_ldb_ch->ldb;
424 struct drm_encoder *encoder = &imx_ldb_ch->encoder;
425 int ret;
426
427 ret = imx_drm_encoder_parse_of(drm, encoder, imx_ldb_ch->child);
428 if (ret)
429 return ret;
430
431 ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
432 if (ret)
433 return ret;
434
435 if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
436 ret = imx_ldb_get_clk(ldb, 1);
437 if (ret)
438 return ret;
439 }
440
441 drm_encoder_helper_add(encoder, &imx_ldb_encoder_helper_funcs);
442 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_LVDS);
443
444 if (imx_ldb_ch->bridge) {
445 ret = drm_bridge_attach(&imx_ldb_ch->encoder,
446 imx_ldb_ch->bridge, NULL, 0);
447 if (ret) {
448 DRM_ERROR("Failed to initialize bridge with drm\n");
449 return ret;
450 }
451 } else {
452 /*
453 * We want to add the connector whenever there is no bridge
454 * that brings its own, not only when there is a panel. For
455 * historical reasons, the ldb driver can also work without
456 * a panel.
457 */
458 drm_connector_helper_add(&imx_ldb_ch->connector,
459 &imx_ldb_connector_helper_funcs);
460 drm_connector_init_with_ddc(drm, &imx_ldb_ch->connector,
461 &imx_ldb_connector_funcs,
462 DRM_MODE_CONNECTOR_LVDS,
463 imx_ldb_ch->ddc);
464 drm_connector_attach_encoder(&imx_ldb_ch->connector, encoder);
465 }
466
467 return 0;
468 }
469
470 struct imx_ldb_bit_mapping {
471 u32 bus_format;
472 u32 datawidth;
473 const char * const mapping;
474 };
475
476 static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = {
477 { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" },
478 { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" },
479 { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" },
480 };
481
of_get_bus_format(struct device * dev,struct device_node * np)482 static u32 of_get_bus_format(struct device *dev, struct device_node *np)
483 {
484 const char *bm;
485 u32 datawidth = 0;
486 int ret, i;
487
488 ret = of_property_read_string(np, "fsl,data-mapping", &bm);
489 if (ret < 0)
490 return ret;
491
492 of_property_read_u32(np, "fsl,data-width", &datawidth);
493
494 for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) {
495 if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) &&
496 datawidth == imx_ldb_bit_mappings[i].datawidth)
497 return imx_ldb_bit_mappings[i].bus_format;
498 }
499
500 dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm);
501
502 return -ENOENT;
503 }
504
505 static struct bus_mux imx6q_lvds_mux[2] = {
506 {
507 .reg = IOMUXC_GPR3,
508 .shift = 6,
509 .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
510 }, {
511 .reg = IOMUXC_GPR3,
512 .shift = 8,
513 .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
514 }
515 };
516
517 /*
518 * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
519 * of_match_device will walk through this list and take the first entry
520 * matching any of its compatible values. Therefore, the more generic
521 * entries (in this case fsl,imx53-ldb) need to be ordered last.
522 */
523 static const struct of_device_id imx_ldb_dt_ids[] = {
524 { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
525 { .compatible = "fsl,imx53-ldb", .data = NULL, },
526 { }
527 };
528 MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
529
imx_ldb_panel_ddc(struct device * dev,struct imx_ldb_channel * channel,struct device_node * child)530 static int imx_ldb_panel_ddc(struct device *dev,
531 struct imx_ldb_channel *channel, struct device_node *child)
532 {
533 struct device_node *ddc_node;
534 const u8 *edidp;
535 int ret;
536
537 ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0);
538 if (ddc_node) {
539 channel->ddc = of_find_i2c_adapter_by_node(ddc_node);
540 of_node_put(ddc_node);
541 if (!channel->ddc) {
542 dev_warn(dev, "failed to get ddc i2c adapter\n");
543 return -EPROBE_DEFER;
544 }
545 }
546
547 if (!channel->ddc) {
548 int edid_len;
549
550 /* if no DDC available, fallback to hardcoded EDID */
551 dev_dbg(dev, "no ddc available\n");
552
553 edidp = of_get_property(child, "edid", &edid_len);
554 if (edidp) {
555 channel->edid = kmemdup(edidp, edid_len, GFP_KERNEL);
556 } else if (!channel->panel) {
557 /* fallback to display-timings node */
558 ret = of_get_drm_display_mode(child,
559 &channel->mode,
560 &channel->bus_flags,
561 OF_USE_NATIVE_MODE);
562 if (!ret)
563 channel->mode_valid = 1;
564 }
565 }
566 return 0;
567 }
568
imx_ldb_bind(struct device * dev,struct device * master,void * data)569 static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
570 {
571 struct drm_device *drm = data;
572 struct device_node *np = dev->of_node;
573 const struct of_device_id *of_id =
574 of_match_device(imx_ldb_dt_ids, dev);
575 struct device_node *child;
576 struct imx_ldb *imx_ldb;
577 int dual;
578 int ret;
579 int i;
580
581 imx_ldb = dev_get_drvdata(dev);
582 memset(imx_ldb, 0, sizeof(*imx_ldb));
583
584 imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
585 if (IS_ERR(imx_ldb->regmap)) {
586 dev_err(dev, "failed to get parent regmap\n");
587 return PTR_ERR(imx_ldb->regmap);
588 }
589
590 /* disable LDB by resetting the control register to POR default */
591 regmap_write(imx_ldb->regmap, IOMUXC_GPR2, 0);
592
593 imx_ldb->dev = dev;
594
595 if (of_id)
596 imx_ldb->lvds_mux = of_id->data;
597
598 dual = of_property_read_bool(np, "fsl,dual-channel");
599 if (dual)
600 imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
601
602 /*
603 * There are three different possible clock mux configurations:
604 * i.MX53: ipu1_di0_sel, ipu1_di1_sel
605 * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
606 * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
607 * Map them all to di0_sel...di3_sel.
608 */
609 for (i = 0; i < 4; i++) {
610 char clkname[16];
611
612 sprintf(clkname, "di%d_sel", i);
613 imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
614 if (IS_ERR(imx_ldb->clk_sel[i])) {
615 ret = PTR_ERR(imx_ldb->clk_sel[i]);
616 imx_ldb->clk_sel[i] = NULL;
617 break;
618 }
619
620 imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]);
621 }
622 if (i == 0)
623 return ret;
624
625 for_each_child_of_node(np, child) {
626 struct imx_ldb_channel *channel;
627 int bus_format;
628
629 ret = of_property_read_u32(child, "reg", &i);
630 if (ret || i < 0 || i > 1) {
631 ret = -EINVAL;
632 goto free_child;
633 }
634
635 if (!of_device_is_available(child))
636 continue;
637
638 if (dual && i > 0) {
639 dev_warn(dev, "dual-channel mode, ignoring second output\n");
640 continue;
641 }
642
643 channel = &imx_ldb->channel[i];
644 channel->ldb = imx_ldb;
645 channel->chno = i;
646
647 /*
648 * The output port is port@4 with an external 4-port mux or
649 * port@2 with the internal 2-port mux.
650 */
651 ret = drm_of_find_panel_or_bridge(child,
652 imx_ldb->lvds_mux ? 4 : 2, 0,
653 &channel->panel, &channel->bridge);
654 if (ret && ret != -ENODEV)
655 goto free_child;
656
657 /* panel ddc only if there is no bridge */
658 if (!channel->bridge) {
659 ret = imx_ldb_panel_ddc(dev, channel, child);
660 if (ret)
661 goto free_child;
662 }
663
664 bus_format = of_get_bus_format(dev, child);
665 if (bus_format == -EINVAL) {
666 /*
667 * If no bus format was specified in the device tree,
668 * we can still get it from the connected panel later.
669 */
670 if (channel->panel && channel->panel->funcs &&
671 channel->panel->funcs->get_modes)
672 bus_format = 0;
673 }
674 if (bus_format < 0) {
675 dev_err(dev, "could not determine data mapping: %d\n",
676 bus_format);
677 ret = bus_format;
678 goto free_child;
679 }
680 channel->bus_format = bus_format;
681 channel->child = child;
682
683 ret = imx_ldb_register(drm, channel);
684 if (ret) {
685 channel->child = NULL;
686 goto free_child;
687 }
688 }
689
690 return 0;
691
692 free_child:
693 of_node_put(child);
694 return ret;
695 }
696
imx_ldb_unbind(struct device * dev,struct device * master,void * data)697 static void imx_ldb_unbind(struct device *dev, struct device *master,
698 void *data)
699 {
700 struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
701 int i;
702
703 for (i = 0; i < 2; i++) {
704 struct imx_ldb_channel *channel = &imx_ldb->channel[i];
705
706 kfree(channel->edid);
707 i2c_put_adapter(channel->ddc);
708 }
709 }
710
711 static const struct component_ops imx_ldb_ops = {
712 .bind = imx_ldb_bind,
713 .unbind = imx_ldb_unbind,
714 };
715
imx_ldb_probe(struct platform_device * pdev)716 static int imx_ldb_probe(struct platform_device *pdev)
717 {
718 struct imx_ldb *imx_ldb;
719
720 imx_ldb = devm_kzalloc(&pdev->dev, sizeof(*imx_ldb), GFP_KERNEL);
721 if (!imx_ldb)
722 return -ENOMEM;
723
724 platform_set_drvdata(pdev, imx_ldb);
725
726 return component_add(&pdev->dev, &imx_ldb_ops);
727 }
728
imx_ldb_remove(struct platform_device * pdev)729 static int imx_ldb_remove(struct platform_device *pdev)
730 {
731 component_del(&pdev->dev, &imx_ldb_ops);
732 return 0;
733 }
734
735 static struct platform_driver imx_ldb_driver = {
736 .probe = imx_ldb_probe,
737 .remove = imx_ldb_remove,
738 .driver = {
739 .of_match_table = imx_ldb_dt_ids,
740 .name = DRIVER_NAME,
741 },
742 };
743
744 module_platform_driver(imx_ldb_driver);
745
746 MODULE_DESCRIPTION("i.MX LVDS driver");
747 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
748 MODULE_LICENSE("GPL");
749 MODULE_ALIAS("platform:" DRIVER_NAME);
750