1 /*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/iopoll.h>
27 #include <linux/module.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/regulator/consumer.h>
31
32 #include <video/display_timing.h>
33 #include <video/of_display_timing.h>
34 #include <video/videomode.h>
35
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_device.h>
38 #include <drm/drm_mipi_dsi.h>
39 #include <drm/drm_panel.h>
40
41 /**
42 * @modes: Pointer to array of fixed modes appropriate for this panel. If
43 * only one mode then this can just be the address of this the mode.
44 * NOTE: cannot be used with "timings" and also if this is specified
45 * then you cannot override the mode in the device tree.
46 * @num_modes: Number of elements in modes array.
47 * @timings: Pointer to array of display timings. NOTE: cannot be used with
48 * "modes" and also these will be used to validate a device tree
49 * override if one is present.
50 * @num_timings: Number of elements in timings array.
51 * @bpc: Bits per color.
52 * @size: Structure containing the physical size of this panel.
53 * @delay: Structure containing various delay values for this panel.
54 * @bus_format: See MEDIA_BUS_FMT_... defines.
55 * @bus_flags: See DRM_BUS_FLAG_... defines.
56 */
57 struct panel_desc {
58 const struct drm_display_mode *modes;
59 unsigned int num_modes;
60 const struct display_timing *timings;
61 unsigned int num_timings;
62
63 unsigned int bpc;
64
65 /**
66 * @width: width (in millimeters) of the panel's active display area
67 * @height: height (in millimeters) of the panel's active display area
68 */
69 struct {
70 unsigned int width;
71 unsigned int height;
72 } size;
73
74 /**
75 * @prepare: the time (in milliseconds) that it takes for the panel to
76 * become ready and start receiving video data
77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
78 * Plug Detect isn't used.
79 * @enable: the time (in milliseconds) that it takes for the panel to
80 * display the first valid frame after starting to receive
81 * video data
82 * @disable: the time (in milliseconds) that it takes for the panel to
83 * turn the display off (no content is visible)
84 * @unprepare: the time (in milliseconds) that it takes for the panel
85 * to power itself down completely
86 */
87 struct {
88 unsigned int prepare;
89 unsigned int hpd_absent_delay;
90 unsigned int enable;
91 unsigned int disable;
92 unsigned int unprepare;
93 } delay;
94
95 u32 bus_format;
96 u32 bus_flags;
97 int connector_type;
98 };
99
100 struct panel_simple {
101 struct drm_panel base;
102 bool prepared;
103 bool enabled;
104 bool no_hpd;
105
106 const struct panel_desc *desc;
107
108 struct regulator *supply;
109 struct i2c_adapter *ddc;
110
111 struct gpio_desc *enable_gpio;
112 struct gpio_desc *hpd_gpio;
113
114 struct drm_display_mode override_mode;
115
116 enum drm_panel_orientation orientation;
117 };
118
to_panel_simple(struct drm_panel * panel)119 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
120 {
121 return container_of(panel, struct panel_simple, base);
122 }
123
panel_simple_get_timings_modes(struct panel_simple * panel,struct drm_connector * connector)124 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
125 struct drm_connector *connector)
126 {
127 struct drm_display_mode *mode;
128 unsigned int i, num = 0;
129
130 for (i = 0; i < panel->desc->num_timings; i++) {
131 const struct display_timing *dt = &panel->desc->timings[i];
132 struct videomode vm;
133
134 videomode_from_timing(dt, &vm);
135 mode = drm_mode_create(connector->dev);
136 if (!mode) {
137 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
138 dt->hactive.typ, dt->vactive.typ);
139 continue;
140 }
141
142 drm_display_mode_from_videomode(&vm, mode);
143
144 mode->type |= DRM_MODE_TYPE_DRIVER;
145
146 if (panel->desc->num_timings == 1)
147 mode->type |= DRM_MODE_TYPE_PREFERRED;
148
149 drm_mode_probed_add(connector, mode);
150 num++;
151 }
152
153 return num;
154 }
155
panel_simple_get_display_modes(struct panel_simple * panel,struct drm_connector * connector)156 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
157 struct drm_connector *connector)
158 {
159 struct drm_display_mode *mode;
160 unsigned int i, num = 0;
161
162 for (i = 0; i < panel->desc->num_modes; i++) {
163 const struct drm_display_mode *m = &panel->desc->modes[i];
164
165 mode = drm_mode_duplicate(connector->dev, m);
166 if (!mode) {
167 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
168 m->hdisplay, m->vdisplay,
169 drm_mode_vrefresh(m));
170 continue;
171 }
172
173 mode->type |= DRM_MODE_TYPE_DRIVER;
174
175 if (panel->desc->num_modes == 1)
176 mode->type |= DRM_MODE_TYPE_PREFERRED;
177
178 drm_mode_set_name(mode);
179
180 drm_mode_probed_add(connector, mode);
181 num++;
182 }
183
184 return num;
185 }
186
panel_simple_get_non_edid_modes(struct panel_simple * panel,struct drm_connector * connector)187 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
188 struct drm_connector *connector)
189 {
190 struct drm_display_mode *mode;
191 bool has_override = panel->override_mode.type;
192 unsigned int num = 0;
193
194 if (!panel->desc)
195 return 0;
196
197 if (has_override) {
198 mode = drm_mode_duplicate(connector->dev,
199 &panel->override_mode);
200 if (mode) {
201 drm_mode_probed_add(connector, mode);
202 num = 1;
203 } else {
204 dev_err(panel->base.dev, "failed to add override mode\n");
205 }
206 }
207
208 /* Only add timings if override was not there or failed to validate */
209 if (num == 0 && panel->desc->num_timings)
210 num = panel_simple_get_timings_modes(panel, connector);
211
212 /*
213 * Only add fixed modes if timings/override added no mode.
214 *
215 * We should only ever have either the display timings specified
216 * or a fixed mode. Anything else is rather bogus.
217 */
218 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
219 if (num == 0)
220 num = panel_simple_get_display_modes(panel, connector);
221
222 connector->display_info.bpc = panel->desc->bpc;
223 connector->display_info.width_mm = panel->desc->size.width;
224 connector->display_info.height_mm = panel->desc->size.height;
225 if (panel->desc->bus_format)
226 drm_display_info_set_bus_formats(&connector->display_info,
227 &panel->desc->bus_format, 1);
228 connector->display_info.bus_flags = panel->desc->bus_flags;
229
230 return num;
231 }
232
panel_simple_disable(struct drm_panel * panel)233 static int panel_simple_disable(struct drm_panel *panel)
234 {
235 struct panel_simple *p = to_panel_simple(panel);
236
237 if (!p->enabled)
238 return 0;
239
240 if (p->desc->delay.disable)
241 msleep(p->desc->delay.disable);
242
243 p->enabled = false;
244
245 return 0;
246 }
247
panel_simple_unprepare(struct drm_panel * panel)248 static int panel_simple_unprepare(struct drm_panel *panel)
249 {
250 struct panel_simple *p = to_panel_simple(panel);
251
252 if (!p->prepared)
253 return 0;
254
255 gpiod_set_value_cansleep(p->enable_gpio, 0);
256
257 regulator_disable(p->supply);
258
259 if (p->desc->delay.unprepare)
260 msleep(p->desc->delay.unprepare);
261
262 p->prepared = false;
263
264 return 0;
265 }
266
panel_simple_get_hpd_gpio(struct device * dev,struct panel_simple * p,bool from_probe)267 static int panel_simple_get_hpd_gpio(struct device *dev,
268 struct panel_simple *p, bool from_probe)
269 {
270 int err;
271
272 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
273 if (IS_ERR(p->hpd_gpio)) {
274 err = PTR_ERR(p->hpd_gpio);
275
276 /*
277 * If we're called from probe we won't consider '-EPROBE_DEFER'
278 * to be an error--we'll leave the error code in "hpd_gpio".
279 * When we try to use it we'll try again. This allows for
280 * circular dependencies where the component providing the
281 * hpd gpio needs the panel to init before probing.
282 */
283 if (err != -EPROBE_DEFER || !from_probe) {
284 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
285 return err;
286 }
287 }
288
289 return 0;
290 }
291
panel_simple_prepare(struct drm_panel * panel)292 static int panel_simple_prepare(struct drm_panel *panel)
293 {
294 struct panel_simple *p = to_panel_simple(panel);
295 unsigned int delay;
296 int err;
297 int hpd_asserted;
298
299 if (p->prepared)
300 return 0;
301
302 err = regulator_enable(p->supply);
303 if (err < 0) {
304 dev_err(panel->dev, "failed to enable supply: %d\n", err);
305 return err;
306 }
307
308 gpiod_set_value_cansleep(p->enable_gpio, 1);
309
310 delay = p->desc->delay.prepare;
311 if (p->no_hpd)
312 delay += p->desc->delay.hpd_absent_delay;
313 if (delay)
314 msleep(delay);
315
316 if (p->hpd_gpio) {
317 if (IS_ERR(p->hpd_gpio)) {
318 err = panel_simple_get_hpd_gpio(panel->dev, p, false);
319 if (err)
320 return err;
321 }
322
323 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
324 hpd_asserted, hpd_asserted,
325 1000, 2000000);
326 if (hpd_asserted < 0)
327 err = hpd_asserted;
328
329 if (err) {
330 dev_err(panel->dev,
331 "error waiting for hpd GPIO: %d\n", err);
332 return err;
333 }
334 }
335
336 p->prepared = true;
337
338 return 0;
339 }
340
panel_simple_enable(struct drm_panel * panel)341 static int panel_simple_enable(struct drm_panel *panel)
342 {
343 struct panel_simple *p = to_panel_simple(panel);
344
345 if (p->enabled)
346 return 0;
347
348 if (p->desc->delay.enable)
349 msleep(p->desc->delay.enable);
350
351 p->enabled = true;
352
353 return 0;
354 }
355
panel_simple_get_modes(struct drm_panel * panel,struct drm_connector * connector)356 static int panel_simple_get_modes(struct drm_panel *panel,
357 struct drm_connector *connector)
358 {
359 struct panel_simple *p = to_panel_simple(panel);
360 int num = 0;
361
362 /* probe EDID if a DDC bus is available */
363 if (p->ddc) {
364 struct edid *edid = drm_get_edid(connector, p->ddc);
365
366 drm_connector_update_edid_property(connector, edid);
367 if (edid) {
368 num += drm_add_edid_modes(connector, edid);
369 kfree(edid);
370 }
371 }
372
373 /* add hard-coded panel modes */
374 num += panel_simple_get_non_edid_modes(p, connector);
375
376 /* set up connector's "panel orientation" property */
377 drm_connector_set_panel_orientation(connector, p->orientation);
378
379 return num;
380 }
381
panel_simple_get_timings(struct drm_panel * panel,unsigned int num_timings,struct display_timing * timings)382 static int panel_simple_get_timings(struct drm_panel *panel,
383 unsigned int num_timings,
384 struct display_timing *timings)
385 {
386 struct panel_simple *p = to_panel_simple(panel);
387 unsigned int i;
388
389 if (p->desc->num_timings < num_timings)
390 num_timings = p->desc->num_timings;
391
392 if (timings)
393 for (i = 0; i < num_timings; i++)
394 timings[i] = p->desc->timings[i];
395
396 return p->desc->num_timings;
397 }
398
399 static const struct drm_panel_funcs panel_simple_funcs = {
400 .disable = panel_simple_disable,
401 .unprepare = panel_simple_unprepare,
402 .prepare = panel_simple_prepare,
403 .enable = panel_simple_enable,
404 .get_modes = panel_simple_get_modes,
405 .get_timings = panel_simple_get_timings,
406 };
407
408 static struct panel_desc panel_dpi;
409
panel_dpi_probe(struct device * dev,struct panel_simple * panel)410 static int panel_dpi_probe(struct device *dev,
411 struct panel_simple *panel)
412 {
413 struct display_timing *timing;
414 const struct device_node *np;
415 struct panel_desc *desc;
416 unsigned int bus_flags;
417 struct videomode vm;
418 int ret;
419
420 np = dev->of_node;
421 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
422 if (!desc)
423 return -ENOMEM;
424
425 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
426 if (!timing)
427 return -ENOMEM;
428
429 ret = of_get_display_timing(np, "panel-timing", timing);
430 if (ret < 0) {
431 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
432 np);
433 return ret;
434 }
435
436 desc->timings = timing;
437 desc->num_timings = 1;
438
439 of_property_read_u32(np, "width-mm", &desc->size.width);
440 of_property_read_u32(np, "height-mm", &desc->size.height);
441
442 /* Extract bus_flags from display_timing */
443 bus_flags = 0;
444 vm.flags = timing->flags;
445 drm_bus_flags_from_videomode(&vm, &bus_flags);
446 desc->bus_flags = bus_flags;
447
448 /* We do not know the connector for the DT node, so guess it */
449 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
450
451 panel->desc = desc;
452
453 return 0;
454 }
455
456 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
457 (to_check->field.typ >= bounds->field.min && \
458 to_check->field.typ <= bounds->field.max)
panel_simple_parse_panel_timing_node(struct device * dev,struct panel_simple * panel,const struct display_timing * ot)459 static void panel_simple_parse_panel_timing_node(struct device *dev,
460 struct panel_simple *panel,
461 const struct display_timing *ot)
462 {
463 const struct panel_desc *desc = panel->desc;
464 struct videomode vm;
465 unsigned int i;
466
467 if (WARN_ON(desc->num_modes)) {
468 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
469 return;
470 }
471 if (WARN_ON(!desc->num_timings)) {
472 dev_err(dev, "Reject override mode: no timings specified\n");
473 return;
474 }
475
476 for (i = 0; i < panel->desc->num_timings; i++) {
477 const struct display_timing *dt = &panel->desc->timings[i];
478
479 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
480 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
481 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
482 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
483 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
484 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
485 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
486 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
487 continue;
488
489 if (ot->flags != dt->flags)
490 continue;
491
492 videomode_from_timing(ot, &vm);
493 drm_display_mode_from_videomode(&vm, &panel->override_mode);
494 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
495 DRM_MODE_TYPE_PREFERRED;
496 break;
497 }
498
499 if (WARN_ON(!panel->override_mode.type))
500 dev_err(dev, "Reject override mode: No display_timing found\n");
501 }
502
panel_simple_probe(struct device * dev,const struct panel_desc * desc)503 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
504 {
505 struct panel_simple *panel;
506 struct display_timing dt;
507 struct device_node *ddc;
508 int connector_type;
509 u32 bus_flags;
510 int err;
511
512 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
513 if (!panel)
514 return -ENOMEM;
515
516 panel->enabled = false;
517 panel->prepared = false;
518 panel->desc = desc;
519
520 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
521 if (!panel->no_hpd) {
522 err = panel_simple_get_hpd_gpio(dev, panel, true);
523 if (err)
524 return err;
525 }
526
527 panel->supply = devm_regulator_get(dev, "power");
528 if (IS_ERR(panel->supply))
529 return PTR_ERR(panel->supply);
530
531 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
532 GPIOD_OUT_LOW);
533 if (IS_ERR(panel->enable_gpio)) {
534 err = PTR_ERR(panel->enable_gpio);
535 if (err != -EPROBE_DEFER)
536 dev_err(dev, "failed to request GPIO: %d\n", err);
537 return err;
538 }
539
540 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
541 if (err) {
542 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
543 return err;
544 }
545
546 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
547 if (ddc) {
548 panel->ddc = of_find_i2c_adapter_by_node(ddc);
549 of_node_put(ddc);
550
551 if (!panel->ddc)
552 return -EPROBE_DEFER;
553 }
554
555 if (desc == &panel_dpi) {
556 /* Handle the generic panel-dpi binding */
557 err = panel_dpi_probe(dev, panel);
558 if (err)
559 goto free_ddc;
560 } else {
561 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
562 panel_simple_parse_panel_timing_node(dev, panel, &dt);
563 }
564
565 connector_type = desc->connector_type;
566 /* Catch common mistakes for panels. */
567 switch (connector_type) {
568 case 0:
569 dev_warn(dev, "Specify missing connector_type\n");
570 connector_type = DRM_MODE_CONNECTOR_DPI;
571 break;
572 case DRM_MODE_CONNECTOR_LVDS:
573 WARN_ON(desc->bus_flags &
574 ~(DRM_BUS_FLAG_DE_LOW |
575 DRM_BUS_FLAG_DE_HIGH |
576 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
577 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
578 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
579 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
580 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
581 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
582 desc->bpc != 6);
583 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
584 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
585 desc->bpc != 8);
586 break;
587 case DRM_MODE_CONNECTOR_eDP:
588 if (desc->bus_format == 0)
589 dev_warn(dev, "Specify missing bus_format\n");
590 if (desc->bpc != 6 && desc->bpc != 8)
591 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
592 break;
593 case DRM_MODE_CONNECTOR_DSI:
594 if (desc->bpc != 6 && desc->bpc != 8)
595 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
596 break;
597 case DRM_MODE_CONNECTOR_DPI:
598 bus_flags = DRM_BUS_FLAG_DE_LOW |
599 DRM_BUS_FLAG_DE_HIGH |
600 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
601 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
602 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
603 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
604 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
605 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
606 if (desc->bus_flags & ~bus_flags)
607 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
608 if (!(desc->bus_flags & bus_flags))
609 dev_warn(dev, "Specify missing bus_flags\n");
610 if (desc->bus_format == 0)
611 dev_warn(dev, "Specify missing bus_format\n");
612 if (desc->bpc != 6 && desc->bpc != 8)
613 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
614 break;
615 default:
616 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
617 connector_type = DRM_MODE_CONNECTOR_DPI;
618 break;
619 }
620
621 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
622
623 err = drm_panel_of_backlight(&panel->base);
624 if (err)
625 goto free_ddc;
626
627 drm_panel_add(&panel->base);
628
629 dev_set_drvdata(dev, panel);
630
631 return 0;
632
633 free_ddc:
634 if (panel->ddc)
635 put_device(&panel->ddc->dev);
636
637 return err;
638 }
639
panel_simple_remove(struct device * dev)640 static int panel_simple_remove(struct device *dev)
641 {
642 struct panel_simple *panel = dev_get_drvdata(dev);
643
644 drm_panel_remove(&panel->base);
645 drm_panel_disable(&panel->base);
646 drm_panel_unprepare(&panel->base);
647
648 if (panel->ddc)
649 put_device(&panel->ddc->dev);
650
651 return 0;
652 }
653
panel_simple_shutdown(struct device * dev)654 static void panel_simple_shutdown(struct device *dev)
655 {
656 struct panel_simple *panel = dev_get_drvdata(dev);
657
658 drm_panel_disable(&panel->base);
659 drm_panel_unprepare(&panel->base);
660 }
661
662 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
663 .clock = 71100,
664 .hdisplay = 1280,
665 .hsync_start = 1280 + 40,
666 .hsync_end = 1280 + 40 + 80,
667 .htotal = 1280 + 40 + 80 + 40,
668 .vdisplay = 800,
669 .vsync_start = 800 + 3,
670 .vsync_end = 800 + 3 + 10,
671 .vtotal = 800 + 3 + 10 + 10,
672 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
673 };
674
675 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
676 .modes = &ire_am_1280800n3tzqw_t00h_mode,
677 .num_modes = 1,
678 .bpc = 6,
679 .size = {
680 .width = 217,
681 .height = 136,
682 },
683 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
684 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
685 .connector_type = DRM_MODE_CONNECTOR_LVDS,
686 };
687
688 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
689 .clock = 9000,
690 .hdisplay = 480,
691 .hsync_start = 480 + 2,
692 .hsync_end = 480 + 2 + 41,
693 .htotal = 480 + 2 + 41 + 2,
694 .vdisplay = 272,
695 .vsync_start = 272 + 2,
696 .vsync_end = 272 + 2 + 10,
697 .vtotal = 272 + 2 + 10 + 2,
698 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
699 };
700
701 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
702 .modes = &ire_am_480272h3tmqw_t01h_mode,
703 .num_modes = 1,
704 .bpc = 8,
705 .size = {
706 .width = 105,
707 .height = 67,
708 },
709 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
710 };
711
712 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
713 .clock = 33333,
714 .hdisplay = 800,
715 .hsync_start = 800 + 0,
716 .hsync_end = 800 + 0 + 255,
717 .htotal = 800 + 0 + 255 + 0,
718 .vdisplay = 480,
719 .vsync_start = 480 + 2,
720 .vsync_end = 480 + 2 + 45,
721 .vtotal = 480 + 2 + 45 + 0,
722 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
723 };
724
725 static const struct panel_desc ampire_am800480r3tmqwa1h = {
726 .modes = &ire_am800480r3tmqwa1h_mode,
727 .num_modes = 1,
728 .bpc = 6,
729 .size = {
730 .width = 152,
731 .height = 91,
732 },
733 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
734 };
735
736 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
737 .pixelclock = { 26400000, 33300000, 46800000 },
738 .hactive = { 800, 800, 800 },
739 .hfront_porch = { 16, 210, 354 },
740 .hback_porch = { 45, 36, 6 },
741 .hsync_len = { 1, 10, 40 },
742 .vactive = { 480, 480, 480 },
743 .vfront_porch = { 7, 22, 147 },
744 .vback_porch = { 22, 13, 3 },
745 .vsync_len = { 1, 10, 20 },
746 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
747 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
748 };
749
750 static const struct panel_desc armadeus_st0700_adapt = {
751 .timings = &santek_st0700i5y_rbslw_f_timing,
752 .num_timings = 1,
753 .bpc = 6,
754 .size = {
755 .width = 154,
756 .height = 86,
757 },
758 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
759 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
760 };
761
762 static const struct drm_display_mode auo_b101aw03_mode = {
763 .clock = 51450,
764 .hdisplay = 1024,
765 .hsync_start = 1024 + 156,
766 .hsync_end = 1024 + 156 + 8,
767 .htotal = 1024 + 156 + 8 + 156,
768 .vdisplay = 600,
769 .vsync_start = 600 + 16,
770 .vsync_end = 600 + 16 + 6,
771 .vtotal = 600 + 16 + 6 + 16,
772 };
773
774 static const struct panel_desc auo_b101aw03 = {
775 .modes = &auo_b101aw03_mode,
776 .num_modes = 1,
777 .bpc = 6,
778 .size = {
779 .width = 223,
780 .height = 125,
781 },
782 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
783 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
784 .connector_type = DRM_MODE_CONNECTOR_LVDS,
785 };
786
787 static const struct display_timing auo_b101ean01_timing = {
788 .pixelclock = { 65300000, 72500000, 75000000 },
789 .hactive = { 1280, 1280, 1280 },
790 .hfront_porch = { 18, 119, 119 },
791 .hback_porch = { 21, 21, 21 },
792 .hsync_len = { 32, 32, 32 },
793 .vactive = { 800, 800, 800 },
794 .vfront_porch = { 4, 4, 4 },
795 .vback_porch = { 8, 8, 8 },
796 .vsync_len = { 18, 20, 20 },
797 };
798
799 static const struct panel_desc auo_b101ean01 = {
800 .timings = &auo_b101ean01_timing,
801 .num_timings = 1,
802 .bpc = 6,
803 .size = {
804 .width = 217,
805 .height = 136,
806 },
807 };
808
809 static const struct drm_display_mode auo_b101xtn01_mode = {
810 .clock = 72000,
811 .hdisplay = 1366,
812 .hsync_start = 1366 + 20,
813 .hsync_end = 1366 + 20 + 70,
814 .htotal = 1366 + 20 + 70,
815 .vdisplay = 768,
816 .vsync_start = 768 + 14,
817 .vsync_end = 768 + 14 + 42,
818 .vtotal = 768 + 14 + 42,
819 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
820 };
821
822 static const struct panel_desc auo_b101xtn01 = {
823 .modes = &auo_b101xtn01_mode,
824 .num_modes = 1,
825 .bpc = 6,
826 .size = {
827 .width = 223,
828 .height = 125,
829 },
830 };
831
832 static const struct drm_display_mode auo_b116xak01_mode = {
833 .clock = 69300,
834 .hdisplay = 1366,
835 .hsync_start = 1366 + 48,
836 .hsync_end = 1366 + 48 + 32,
837 .htotal = 1366 + 48 + 32 + 10,
838 .vdisplay = 768,
839 .vsync_start = 768 + 4,
840 .vsync_end = 768 + 4 + 6,
841 .vtotal = 768 + 4 + 6 + 15,
842 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
843 };
844
845 static const struct panel_desc auo_b116xak01 = {
846 .modes = &auo_b116xak01_mode,
847 .num_modes = 1,
848 .bpc = 6,
849 .size = {
850 .width = 256,
851 .height = 144,
852 },
853 .delay = {
854 .hpd_absent_delay = 200,
855 },
856 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
857 .connector_type = DRM_MODE_CONNECTOR_eDP,
858 };
859
860 static const struct drm_display_mode auo_b116xw03_mode = {
861 .clock = 70589,
862 .hdisplay = 1366,
863 .hsync_start = 1366 + 40,
864 .hsync_end = 1366 + 40 + 40,
865 .htotal = 1366 + 40 + 40 + 32,
866 .vdisplay = 768,
867 .vsync_start = 768 + 10,
868 .vsync_end = 768 + 10 + 12,
869 .vtotal = 768 + 10 + 12 + 6,
870 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
871 };
872
873 static const struct panel_desc auo_b116xw03 = {
874 .modes = &auo_b116xw03_mode,
875 .num_modes = 1,
876 .bpc = 6,
877 .size = {
878 .width = 256,
879 .height = 144,
880 },
881 .delay = {
882 .enable = 400,
883 },
884 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
885 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
886 .connector_type = DRM_MODE_CONNECTOR_eDP,
887 };
888
889 static const struct drm_display_mode auo_b133xtn01_mode = {
890 .clock = 69500,
891 .hdisplay = 1366,
892 .hsync_start = 1366 + 48,
893 .hsync_end = 1366 + 48 + 32,
894 .htotal = 1366 + 48 + 32 + 20,
895 .vdisplay = 768,
896 .vsync_start = 768 + 3,
897 .vsync_end = 768 + 3 + 6,
898 .vtotal = 768 + 3 + 6 + 13,
899 };
900
901 static const struct panel_desc auo_b133xtn01 = {
902 .modes = &auo_b133xtn01_mode,
903 .num_modes = 1,
904 .bpc = 6,
905 .size = {
906 .width = 293,
907 .height = 165,
908 },
909 };
910
911 static const struct drm_display_mode auo_b133htn01_mode = {
912 .clock = 150660,
913 .hdisplay = 1920,
914 .hsync_start = 1920 + 172,
915 .hsync_end = 1920 + 172 + 80,
916 .htotal = 1920 + 172 + 80 + 60,
917 .vdisplay = 1080,
918 .vsync_start = 1080 + 25,
919 .vsync_end = 1080 + 25 + 10,
920 .vtotal = 1080 + 25 + 10 + 10,
921 };
922
923 static const struct panel_desc auo_b133htn01 = {
924 .modes = &auo_b133htn01_mode,
925 .num_modes = 1,
926 .bpc = 6,
927 .size = {
928 .width = 293,
929 .height = 165,
930 },
931 .delay = {
932 .prepare = 105,
933 .enable = 20,
934 .unprepare = 50,
935 },
936 };
937
938 static const struct display_timing auo_g070vvn01_timings = {
939 .pixelclock = { 33300000, 34209000, 45000000 },
940 .hactive = { 800, 800, 800 },
941 .hfront_porch = { 20, 40, 200 },
942 .hback_porch = { 87, 40, 1 },
943 .hsync_len = { 1, 48, 87 },
944 .vactive = { 480, 480, 480 },
945 .vfront_porch = { 5, 13, 200 },
946 .vback_porch = { 31, 31, 29 },
947 .vsync_len = { 1, 1, 3 },
948 };
949
950 static const struct panel_desc auo_g070vvn01 = {
951 .timings = &auo_g070vvn01_timings,
952 .num_timings = 1,
953 .bpc = 8,
954 .size = {
955 .width = 152,
956 .height = 91,
957 },
958 .delay = {
959 .prepare = 200,
960 .enable = 50,
961 .disable = 50,
962 .unprepare = 1000,
963 },
964 };
965
966 static const struct drm_display_mode auo_g101evn010_mode = {
967 .clock = 68930,
968 .hdisplay = 1280,
969 .hsync_start = 1280 + 82,
970 .hsync_end = 1280 + 82 + 2,
971 .htotal = 1280 + 82 + 2 + 84,
972 .vdisplay = 800,
973 .vsync_start = 800 + 8,
974 .vsync_end = 800 + 8 + 2,
975 .vtotal = 800 + 8 + 2 + 6,
976 };
977
978 static const struct panel_desc auo_g101evn010 = {
979 .modes = &auo_g101evn010_mode,
980 .num_modes = 1,
981 .bpc = 6,
982 .size = {
983 .width = 216,
984 .height = 135,
985 },
986 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
987 .connector_type = DRM_MODE_CONNECTOR_LVDS,
988 };
989
990 static const struct drm_display_mode auo_g104sn02_mode = {
991 .clock = 40000,
992 .hdisplay = 800,
993 .hsync_start = 800 + 40,
994 .hsync_end = 800 + 40 + 216,
995 .htotal = 800 + 40 + 216 + 128,
996 .vdisplay = 600,
997 .vsync_start = 600 + 10,
998 .vsync_end = 600 + 10 + 35,
999 .vtotal = 600 + 10 + 35 + 2,
1000 };
1001
1002 static const struct panel_desc auo_g104sn02 = {
1003 .modes = &auo_g104sn02_mode,
1004 .num_modes = 1,
1005 .bpc = 8,
1006 .size = {
1007 .width = 211,
1008 .height = 158,
1009 },
1010 };
1011
1012 static const struct drm_display_mode auo_g121ean01_mode = {
1013 .clock = 66700,
1014 .hdisplay = 1280,
1015 .hsync_start = 1280 + 58,
1016 .hsync_end = 1280 + 58 + 8,
1017 .htotal = 1280 + 58 + 8 + 70,
1018 .vdisplay = 800,
1019 .vsync_start = 800 + 6,
1020 .vsync_end = 800 + 6 + 4,
1021 .vtotal = 800 + 6 + 4 + 10,
1022 };
1023
1024 static const struct panel_desc auo_g121ean01 = {
1025 .modes = &auo_g121ean01_mode,
1026 .num_modes = 1,
1027 .bpc = 8,
1028 .size = {
1029 .width = 261,
1030 .height = 163,
1031 },
1032 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1033 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1034 };
1035
1036 static const struct display_timing auo_g133han01_timings = {
1037 .pixelclock = { 134000000, 141200000, 149000000 },
1038 .hactive = { 1920, 1920, 1920 },
1039 .hfront_porch = { 39, 58, 77 },
1040 .hback_porch = { 59, 88, 117 },
1041 .hsync_len = { 28, 42, 56 },
1042 .vactive = { 1080, 1080, 1080 },
1043 .vfront_porch = { 3, 8, 11 },
1044 .vback_porch = { 5, 14, 19 },
1045 .vsync_len = { 4, 14, 19 },
1046 };
1047
1048 static const struct panel_desc auo_g133han01 = {
1049 .timings = &auo_g133han01_timings,
1050 .num_timings = 1,
1051 .bpc = 8,
1052 .size = {
1053 .width = 293,
1054 .height = 165,
1055 },
1056 .delay = {
1057 .prepare = 200,
1058 .enable = 50,
1059 .disable = 50,
1060 .unprepare = 1000,
1061 },
1062 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1063 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1064 };
1065
1066 static const struct drm_display_mode auo_g156xtn01_mode = {
1067 .clock = 76000,
1068 .hdisplay = 1366,
1069 .hsync_start = 1366 + 33,
1070 .hsync_end = 1366 + 33 + 67,
1071 .htotal = 1560,
1072 .vdisplay = 768,
1073 .vsync_start = 768 + 4,
1074 .vsync_end = 768 + 4 + 4,
1075 .vtotal = 806,
1076 };
1077
1078 static const struct panel_desc auo_g156xtn01 = {
1079 .modes = &auo_g156xtn01_mode,
1080 .num_modes = 1,
1081 .bpc = 8,
1082 .size = {
1083 .width = 344,
1084 .height = 194,
1085 },
1086 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1087 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1088 };
1089
1090 static const struct display_timing auo_g185han01_timings = {
1091 .pixelclock = { 120000000, 144000000, 175000000 },
1092 .hactive = { 1920, 1920, 1920 },
1093 .hfront_porch = { 36, 120, 148 },
1094 .hback_porch = { 24, 88, 108 },
1095 .hsync_len = { 20, 48, 64 },
1096 .vactive = { 1080, 1080, 1080 },
1097 .vfront_porch = { 6, 10, 40 },
1098 .vback_porch = { 2, 5, 20 },
1099 .vsync_len = { 2, 5, 20 },
1100 };
1101
1102 static const struct panel_desc auo_g185han01 = {
1103 .timings = &auo_g185han01_timings,
1104 .num_timings = 1,
1105 .bpc = 8,
1106 .size = {
1107 .width = 409,
1108 .height = 230,
1109 },
1110 .delay = {
1111 .prepare = 50,
1112 .enable = 200,
1113 .disable = 110,
1114 .unprepare = 1000,
1115 },
1116 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1117 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1118 };
1119
1120 static const struct display_timing auo_g190ean01_timings = {
1121 .pixelclock = { 90000000, 108000000, 135000000 },
1122 .hactive = { 1280, 1280, 1280 },
1123 .hfront_porch = { 126, 184, 1266 },
1124 .hback_porch = { 84, 122, 844 },
1125 .hsync_len = { 70, 102, 704 },
1126 .vactive = { 1024, 1024, 1024 },
1127 .vfront_porch = { 4, 26, 76 },
1128 .vback_porch = { 2, 8, 25 },
1129 .vsync_len = { 2, 8, 25 },
1130 };
1131
1132 static const struct panel_desc auo_g190ean01 = {
1133 .timings = &auo_g190ean01_timings,
1134 .num_timings = 1,
1135 .bpc = 8,
1136 .size = {
1137 .width = 376,
1138 .height = 301,
1139 },
1140 .delay = {
1141 .prepare = 50,
1142 .enable = 200,
1143 .disable = 110,
1144 .unprepare = 1000,
1145 },
1146 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1147 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1148 };
1149
1150 static const struct display_timing auo_p320hvn03_timings = {
1151 .pixelclock = { 106000000, 148500000, 164000000 },
1152 .hactive = { 1920, 1920, 1920 },
1153 .hfront_porch = { 25, 50, 130 },
1154 .hback_porch = { 25, 50, 130 },
1155 .hsync_len = { 20, 40, 105 },
1156 .vactive = { 1080, 1080, 1080 },
1157 .vfront_porch = { 8, 17, 150 },
1158 .vback_porch = { 8, 17, 150 },
1159 .vsync_len = { 4, 11, 100 },
1160 };
1161
1162 static const struct panel_desc auo_p320hvn03 = {
1163 .timings = &auo_p320hvn03_timings,
1164 .num_timings = 1,
1165 .bpc = 8,
1166 .size = {
1167 .width = 698,
1168 .height = 393,
1169 },
1170 .delay = {
1171 .prepare = 1,
1172 .enable = 450,
1173 .unprepare = 500,
1174 },
1175 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1176 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1177 };
1178
1179 static const struct drm_display_mode auo_t215hvn01_mode = {
1180 .clock = 148800,
1181 .hdisplay = 1920,
1182 .hsync_start = 1920 + 88,
1183 .hsync_end = 1920 + 88 + 44,
1184 .htotal = 1920 + 88 + 44 + 148,
1185 .vdisplay = 1080,
1186 .vsync_start = 1080 + 4,
1187 .vsync_end = 1080 + 4 + 5,
1188 .vtotal = 1080 + 4 + 5 + 36,
1189 };
1190
1191 static const struct panel_desc auo_t215hvn01 = {
1192 .modes = &auo_t215hvn01_mode,
1193 .num_modes = 1,
1194 .bpc = 8,
1195 .size = {
1196 .width = 430,
1197 .height = 270,
1198 },
1199 .delay = {
1200 .disable = 5,
1201 .unprepare = 1000,
1202 }
1203 };
1204
1205 static const struct drm_display_mode avic_tm070ddh03_mode = {
1206 .clock = 51200,
1207 .hdisplay = 1024,
1208 .hsync_start = 1024 + 160,
1209 .hsync_end = 1024 + 160 + 4,
1210 .htotal = 1024 + 160 + 4 + 156,
1211 .vdisplay = 600,
1212 .vsync_start = 600 + 17,
1213 .vsync_end = 600 + 17 + 1,
1214 .vtotal = 600 + 17 + 1 + 17,
1215 };
1216
1217 static const struct panel_desc avic_tm070ddh03 = {
1218 .modes = &avic_tm070ddh03_mode,
1219 .num_modes = 1,
1220 .bpc = 8,
1221 .size = {
1222 .width = 154,
1223 .height = 90,
1224 },
1225 .delay = {
1226 .prepare = 20,
1227 .enable = 200,
1228 .disable = 200,
1229 },
1230 };
1231
1232 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1233 .clock = 30000,
1234 .hdisplay = 800,
1235 .hsync_start = 800 + 40,
1236 .hsync_end = 800 + 40 + 48,
1237 .htotal = 800 + 40 + 48 + 40,
1238 .vdisplay = 480,
1239 .vsync_start = 480 + 13,
1240 .vsync_end = 480 + 13 + 3,
1241 .vtotal = 480 + 13 + 3 + 29,
1242 };
1243
1244 static const struct panel_desc bananapi_s070wv20_ct16 = {
1245 .modes = &bananapi_s070wv20_ct16_mode,
1246 .num_modes = 1,
1247 .bpc = 6,
1248 .size = {
1249 .width = 154,
1250 .height = 86,
1251 },
1252 };
1253
1254 static const struct drm_display_mode boe_hv070wsa_mode = {
1255 .clock = 42105,
1256 .hdisplay = 1024,
1257 .hsync_start = 1024 + 30,
1258 .hsync_end = 1024 + 30 + 30,
1259 .htotal = 1024 + 30 + 30 + 30,
1260 .vdisplay = 600,
1261 .vsync_start = 600 + 10,
1262 .vsync_end = 600 + 10 + 10,
1263 .vtotal = 600 + 10 + 10 + 10,
1264 };
1265
1266 static const struct panel_desc boe_hv070wsa = {
1267 .modes = &boe_hv070wsa_mode,
1268 .num_modes = 1,
1269 .bpc = 8,
1270 .size = {
1271 .width = 154,
1272 .height = 90,
1273 },
1274 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1275 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1276 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1277 };
1278
1279 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1280 {
1281 .clock = 71900,
1282 .hdisplay = 1280,
1283 .hsync_start = 1280 + 48,
1284 .hsync_end = 1280 + 48 + 32,
1285 .htotal = 1280 + 48 + 32 + 80,
1286 .vdisplay = 800,
1287 .vsync_start = 800 + 3,
1288 .vsync_end = 800 + 3 + 5,
1289 .vtotal = 800 + 3 + 5 + 24,
1290 },
1291 {
1292 .clock = 57500,
1293 .hdisplay = 1280,
1294 .hsync_start = 1280 + 48,
1295 .hsync_end = 1280 + 48 + 32,
1296 .htotal = 1280 + 48 + 32 + 80,
1297 .vdisplay = 800,
1298 .vsync_start = 800 + 3,
1299 .vsync_end = 800 + 3 + 5,
1300 .vtotal = 800 + 3 + 5 + 24,
1301 },
1302 };
1303
1304 static const struct panel_desc boe_nv101wxmn51 = {
1305 .modes = boe_nv101wxmn51_modes,
1306 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1307 .bpc = 8,
1308 .size = {
1309 .width = 217,
1310 .height = 136,
1311 },
1312 .delay = {
1313 .prepare = 210,
1314 .enable = 50,
1315 .unprepare = 160,
1316 },
1317 };
1318
1319 /* Also used for boe_nv133fhm_n62 */
1320 static const struct drm_display_mode boe_nv133fhm_n61_modes = {
1321 .clock = 147840,
1322 .hdisplay = 1920,
1323 .hsync_start = 1920 + 48,
1324 .hsync_end = 1920 + 48 + 32,
1325 .htotal = 1920 + 48 + 32 + 200,
1326 .vdisplay = 1080,
1327 .vsync_start = 1080 + 3,
1328 .vsync_end = 1080 + 3 + 6,
1329 .vtotal = 1080 + 3 + 6 + 31,
1330 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
1331 };
1332
1333 /* Also used for boe_nv133fhm_n62 */
1334 static const struct panel_desc boe_nv133fhm_n61 = {
1335 .modes = &boe_nv133fhm_n61_modes,
1336 .num_modes = 1,
1337 .bpc = 6,
1338 .size = {
1339 .width = 294,
1340 .height = 165,
1341 },
1342 .delay = {
1343 /*
1344 * When power is first given to the panel there's a short
1345 * spike on the HPD line. It was explained that this spike
1346 * was until the TCON data download was complete. On
1347 * one system this was measured at 8 ms. We'll put 15 ms
1348 * in the prepare delay just to be safe and take it away
1349 * from the hpd_absent_delay (which would otherwise be 200 ms)
1350 * to handle this. That means:
1351 * - If HPD isn't hooked up you still have 200 ms delay.
1352 * - If HPD is hooked up we won't try to look at it for the
1353 * first 15 ms.
1354 */
1355 .prepare = 15,
1356 .hpd_absent_delay = 185,
1357
1358 .unprepare = 500,
1359 },
1360 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1361 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1362 .connector_type = DRM_MODE_CONNECTOR_eDP,
1363 };
1364
1365 static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1366 {
1367 .clock = 148500,
1368 .hdisplay = 1920,
1369 .hsync_start = 1920 + 48,
1370 .hsync_end = 1920 + 48 + 32,
1371 .htotal = 2200,
1372 .vdisplay = 1080,
1373 .vsync_start = 1080 + 3,
1374 .vsync_end = 1080 + 3 + 5,
1375 .vtotal = 1125,
1376 },
1377 };
1378
1379 static const struct panel_desc boe_nv140fhmn49 = {
1380 .modes = boe_nv140fhmn49_modes,
1381 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1382 .bpc = 6,
1383 .size = {
1384 .width = 309,
1385 .height = 174,
1386 },
1387 .delay = {
1388 .prepare = 210,
1389 .enable = 50,
1390 .unprepare = 160,
1391 },
1392 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1393 .connector_type = DRM_MODE_CONNECTOR_eDP,
1394 };
1395
1396 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1397 .clock = 9000,
1398 .hdisplay = 480,
1399 .hsync_start = 480 + 5,
1400 .hsync_end = 480 + 5 + 5,
1401 .htotal = 480 + 5 + 5 + 40,
1402 .vdisplay = 272,
1403 .vsync_start = 272 + 8,
1404 .vsync_end = 272 + 8 + 8,
1405 .vtotal = 272 + 8 + 8 + 8,
1406 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1407 };
1408
1409 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1410 .modes = &cdtech_s043wq26h_ct7_mode,
1411 .num_modes = 1,
1412 .bpc = 8,
1413 .size = {
1414 .width = 95,
1415 .height = 54,
1416 },
1417 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1418 };
1419
1420 /* S070PWS19HP-FC21 2017/04/22 */
1421 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1422 .clock = 51200,
1423 .hdisplay = 1024,
1424 .hsync_start = 1024 + 160,
1425 .hsync_end = 1024 + 160 + 20,
1426 .htotal = 1024 + 160 + 20 + 140,
1427 .vdisplay = 600,
1428 .vsync_start = 600 + 12,
1429 .vsync_end = 600 + 12 + 3,
1430 .vtotal = 600 + 12 + 3 + 20,
1431 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1432 };
1433
1434 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1435 .modes = &cdtech_s070pws19hp_fc21_mode,
1436 .num_modes = 1,
1437 .bpc = 6,
1438 .size = {
1439 .width = 154,
1440 .height = 86,
1441 },
1442 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1443 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1444 .connector_type = DRM_MODE_CONNECTOR_DPI,
1445 };
1446
1447 /* S070SWV29HG-DC44 2017/09/21 */
1448 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1449 .clock = 33300,
1450 .hdisplay = 800,
1451 .hsync_start = 800 + 210,
1452 .hsync_end = 800 + 210 + 2,
1453 .htotal = 800 + 210 + 2 + 44,
1454 .vdisplay = 480,
1455 .vsync_start = 480 + 22,
1456 .vsync_end = 480 + 22 + 2,
1457 .vtotal = 480 + 22 + 2 + 21,
1458 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1459 };
1460
1461 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1462 .modes = &cdtech_s070swv29hg_dc44_mode,
1463 .num_modes = 1,
1464 .bpc = 6,
1465 .size = {
1466 .width = 154,
1467 .height = 86,
1468 },
1469 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1470 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1471 .connector_type = DRM_MODE_CONNECTOR_DPI,
1472 };
1473
1474 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1475 .clock = 35000,
1476 .hdisplay = 800,
1477 .hsync_start = 800 + 40,
1478 .hsync_end = 800 + 40 + 40,
1479 .htotal = 800 + 40 + 40 + 48,
1480 .vdisplay = 480,
1481 .vsync_start = 480 + 29,
1482 .vsync_end = 480 + 29 + 13,
1483 .vtotal = 480 + 29 + 13 + 3,
1484 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1485 };
1486
1487 static const struct panel_desc cdtech_s070wv95_ct16 = {
1488 .modes = &cdtech_s070wv95_ct16_mode,
1489 .num_modes = 1,
1490 .bpc = 8,
1491 .size = {
1492 .width = 154,
1493 .height = 85,
1494 },
1495 };
1496
1497 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1498 .pixelclock = { 68900000, 71100000, 73400000 },
1499 .hactive = { 1280, 1280, 1280 },
1500 .hfront_porch = { 65, 80, 95 },
1501 .hback_porch = { 64, 79, 94 },
1502 .hsync_len = { 1, 1, 1 },
1503 .vactive = { 800, 800, 800 },
1504 .vfront_porch = { 7, 11, 14 },
1505 .vback_porch = { 7, 11, 14 },
1506 .vsync_len = { 1, 1, 1 },
1507 .flags = DISPLAY_FLAGS_DE_HIGH,
1508 };
1509
1510 static const struct panel_desc chefree_ch101olhlwh_002 = {
1511 .timings = &chefree_ch101olhlwh_002_timing,
1512 .num_timings = 1,
1513 .bpc = 8,
1514 .size = {
1515 .width = 217,
1516 .height = 135,
1517 },
1518 .delay = {
1519 .enable = 200,
1520 .disable = 200,
1521 },
1522 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1523 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1524 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1525 };
1526
1527 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1528 .clock = 66770,
1529 .hdisplay = 800,
1530 .hsync_start = 800 + 49,
1531 .hsync_end = 800 + 49 + 33,
1532 .htotal = 800 + 49 + 33 + 17,
1533 .vdisplay = 1280,
1534 .vsync_start = 1280 + 1,
1535 .vsync_end = 1280 + 1 + 7,
1536 .vtotal = 1280 + 1 + 7 + 15,
1537 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1538 };
1539
1540 static const struct panel_desc chunghwa_claa070wp03xg = {
1541 .modes = &chunghwa_claa070wp03xg_mode,
1542 .num_modes = 1,
1543 .bpc = 6,
1544 .size = {
1545 .width = 94,
1546 .height = 150,
1547 },
1548 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1549 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1550 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1551 };
1552
1553 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1554 .clock = 72070,
1555 .hdisplay = 1366,
1556 .hsync_start = 1366 + 58,
1557 .hsync_end = 1366 + 58 + 58,
1558 .htotal = 1366 + 58 + 58 + 58,
1559 .vdisplay = 768,
1560 .vsync_start = 768 + 4,
1561 .vsync_end = 768 + 4 + 4,
1562 .vtotal = 768 + 4 + 4 + 4,
1563 };
1564
1565 static const struct panel_desc chunghwa_claa101wa01a = {
1566 .modes = &chunghwa_claa101wa01a_mode,
1567 .num_modes = 1,
1568 .bpc = 6,
1569 .size = {
1570 .width = 220,
1571 .height = 120,
1572 },
1573 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1574 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1575 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1576 };
1577
1578 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1579 .clock = 69300,
1580 .hdisplay = 1366,
1581 .hsync_start = 1366 + 48,
1582 .hsync_end = 1366 + 48 + 32,
1583 .htotal = 1366 + 48 + 32 + 20,
1584 .vdisplay = 768,
1585 .vsync_start = 768 + 16,
1586 .vsync_end = 768 + 16 + 8,
1587 .vtotal = 768 + 16 + 8 + 16,
1588 };
1589
1590 static const struct panel_desc chunghwa_claa101wb01 = {
1591 .modes = &chunghwa_claa101wb01_mode,
1592 .num_modes = 1,
1593 .bpc = 6,
1594 .size = {
1595 .width = 223,
1596 .height = 125,
1597 },
1598 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1599 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1600 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1601 };
1602
1603 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1604 .clock = 33260,
1605 .hdisplay = 800,
1606 .hsync_start = 800 + 40,
1607 .hsync_end = 800 + 40 + 128,
1608 .htotal = 800 + 40 + 128 + 88,
1609 .vdisplay = 480,
1610 .vsync_start = 480 + 10,
1611 .vsync_end = 480 + 10 + 2,
1612 .vtotal = 480 + 10 + 2 + 33,
1613 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1614 };
1615
1616 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1617 .modes = &dataimage_scf0700c48ggu18_mode,
1618 .num_modes = 1,
1619 .bpc = 8,
1620 .size = {
1621 .width = 152,
1622 .height = 91,
1623 },
1624 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1625 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1626 };
1627
1628 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1629 .pixelclock = { 45000000, 51200000, 57000000 },
1630 .hactive = { 1024, 1024, 1024 },
1631 .hfront_porch = { 100, 106, 113 },
1632 .hback_porch = { 100, 106, 113 },
1633 .hsync_len = { 100, 108, 114 },
1634 .vactive = { 600, 600, 600 },
1635 .vfront_porch = { 8, 11, 15 },
1636 .vback_porch = { 8, 11, 15 },
1637 .vsync_len = { 9, 13, 15 },
1638 .flags = DISPLAY_FLAGS_DE_HIGH,
1639 };
1640
1641 static const struct panel_desc dlc_dlc0700yzg_1 = {
1642 .timings = &dlc_dlc0700yzg_1_timing,
1643 .num_timings = 1,
1644 .bpc = 6,
1645 .size = {
1646 .width = 154,
1647 .height = 86,
1648 },
1649 .delay = {
1650 .prepare = 30,
1651 .enable = 200,
1652 .disable = 200,
1653 },
1654 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1655 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1656 };
1657
1658 static const struct display_timing dlc_dlc1010gig_timing = {
1659 .pixelclock = { 68900000, 71100000, 73400000 },
1660 .hactive = { 1280, 1280, 1280 },
1661 .hfront_porch = { 43, 53, 63 },
1662 .hback_porch = { 43, 53, 63 },
1663 .hsync_len = { 44, 54, 64 },
1664 .vactive = { 800, 800, 800 },
1665 .vfront_porch = { 5, 8, 11 },
1666 .vback_porch = { 5, 8, 11 },
1667 .vsync_len = { 5, 7, 11 },
1668 .flags = DISPLAY_FLAGS_DE_HIGH,
1669 };
1670
1671 static const struct panel_desc dlc_dlc1010gig = {
1672 .timings = &dlc_dlc1010gig_timing,
1673 .num_timings = 1,
1674 .bpc = 8,
1675 .size = {
1676 .width = 216,
1677 .height = 135,
1678 },
1679 .delay = {
1680 .prepare = 60,
1681 .enable = 150,
1682 .disable = 100,
1683 .unprepare = 60,
1684 },
1685 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1686 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1687 };
1688
1689 static const struct drm_display_mode edt_et035012dm6_mode = {
1690 .clock = 6500,
1691 .hdisplay = 320,
1692 .hsync_start = 320 + 20,
1693 .hsync_end = 320 + 20 + 30,
1694 .htotal = 320 + 20 + 68,
1695 .vdisplay = 240,
1696 .vsync_start = 240 + 4,
1697 .vsync_end = 240 + 4 + 4,
1698 .vtotal = 240 + 4 + 4 + 14,
1699 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1700 };
1701
1702 static const struct panel_desc edt_et035012dm6 = {
1703 .modes = &edt_et035012dm6_mode,
1704 .num_modes = 1,
1705 .bpc = 8,
1706 .size = {
1707 .width = 70,
1708 .height = 52,
1709 },
1710 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1711 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1712 };
1713
1714 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1715 .clock = 10870,
1716 .hdisplay = 480,
1717 .hsync_start = 480 + 8,
1718 .hsync_end = 480 + 8 + 4,
1719 .htotal = 480 + 8 + 4 + 41,
1720
1721 /*
1722 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1723 * fb_align
1724 */
1725
1726 .vdisplay = 288,
1727 .vsync_start = 288 + 2,
1728 .vsync_end = 288 + 2 + 4,
1729 .vtotal = 288 + 2 + 4 + 10,
1730 };
1731
1732 static const struct panel_desc edt_etm043080dh6gp = {
1733 .modes = &edt_etm043080dh6gp_mode,
1734 .num_modes = 1,
1735 .bpc = 8,
1736 .size = {
1737 .width = 100,
1738 .height = 65,
1739 },
1740 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1741 .connector_type = DRM_MODE_CONNECTOR_DPI,
1742 };
1743
1744 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1745 .clock = 9000,
1746 .hdisplay = 480,
1747 .hsync_start = 480 + 2,
1748 .hsync_end = 480 + 2 + 41,
1749 .htotal = 480 + 2 + 41 + 2,
1750 .vdisplay = 272,
1751 .vsync_start = 272 + 2,
1752 .vsync_end = 272 + 2 + 10,
1753 .vtotal = 272 + 2 + 10 + 2,
1754 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1755 };
1756
1757 static const struct panel_desc edt_etm0430g0dh6 = {
1758 .modes = &edt_etm0430g0dh6_mode,
1759 .num_modes = 1,
1760 .bpc = 6,
1761 .size = {
1762 .width = 95,
1763 .height = 54,
1764 },
1765 };
1766
1767 static const struct drm_display_mode edt_et057090dhu_mode = {
1768 .clock = 25175,
1769 .hdisplay = 640,
1770 .hsync_start = 640 + 16,
1771 .hsync_end = 640 + 16 + 30,
1772 .htotal = 640 + 16 + 30 + 114,
1773 .vdisplay = 480,
1774 .vsync_start = 480 + 10,
1775 .vsync_end = 480 + 10 + 3,
1776 .vtotal = 480 + 10 + 3 + 32,
1777 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1778 };
1779
1780 static const struct panel_desc edt_et057090dhu = {
1781 .modes = &edt_et057090dhu_mode,
1782 .num_modes = 1,
1783 .bpc = 6,
1784 .size = {
1785 .width = 115,
1786 .height = 86,
1787 },
1788 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1789 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1790 .connector_type = DRM_MODE_CONNECTOR_DPI,
1791 };
1792
1793 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1794 .clock = 33260,
1795 .hdisplay = 800,
1796 .hsync_start = 800 + 40,
1797 .hsync_end = 800 + 40 + 128,
1798 .htotal = 800 + 40 + 128 + 88,
1799 .vdisplay = 480,
1800 .vsync_start = 480 + 10,
1801 .vsync_end = 480 + 10 + 2,
1802 .vtotal = 480 + 10 + 2 + 33,
1803 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1804 };
1805
1806 static const struct panel_desc edt_etm0700g0dh6 = {
1807 .modes = &edt_etm0700g0dh6_mode,
1808 .num_modes = 1,
1809 .bpc = 6,
1810 .size = {
1811 .width = 152,
1812 .height = 91,
1813 },
1814 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1815 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1816 };
1817
1818 static const struct panel_desc edt_etm0700g0bdh6 = {
1819 .modes = &edt_etm0700g0dh6_mode,
1820 .num_modes = 1,
1821 .bpc = 6,
1822 .size = {
1823 .width = 152,
1824 .height = 91,
1825 },
1826 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1827 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1828 };
1829
1830 static const struct display_timing evervision_vgg804821_timing = {
1831 .pixelclock = { 27600000, 33300000, 50000000 },
1832 .hactive = { 800, 800, 800 },
1833 .hfront_porch = { 40, 66, 70 },
1834 .hback_porch = { 40, 67, 70 },
1835 .hsync_len = { 40, 67, 70 },
1836 .vactive = { 480, 480, 480 },
1837 .vfront_porch = { 6, 10, 10 },
1838 .vback_porch = { 7, 11, 11 },
1839 .vsync_len = { 7, 11, 11 },
1840 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1841 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1842 DISPLAY_FLAGS_SYNC_NEGEDGE,
1843 };
1844
1845 static const struct panel_desc evervision_vgg804821 = {
1846 .timings = &evervision_vgg804821_timing,
1847 .num_timings = 1,
1848 .bpc = 8,
1849 .size = {
1850 .width = 108,
1851 .height = 64,
1852 },
1853 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1854 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1855 };
1856
1857 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1858 .clock = 32260,
1859 .hdisplay = 800,
1860 .hsync_start = 800 + 168,
1861 .hsync_end = 800 + 168 + 64,
1862 .htotal = 800 + 168 + 64 + 88,
1863 .vdisplay = 480,
1864 .vsync_start = 480 + 37,
1865 .vsync_end = 480 + 37 + 2,
1866 .vtotal = 480 + 37 + 2 + 8,
1867 };
1868
1869 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1870 .modes = &foxlink_fl500wvr00_a0t_mode,
1871 .num_modes = 1,
1872 .bpc = 8,
1873 .size = {
1874 .width = 108,
1875 .height = 65,
1876 },
1877 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1878 };
1879
1880 static const struct drm_display_mode frida_frd350h54004_modes[] = {
1881 { /* 60 Hz */
1882 .clock = 6000,
1883 .hdisplay = 320,
1884 .hsync_start = 320 + 44,
1885 .hsync_end = 320 + 44 + 16,
1886 .htotal = 320 + 44 + 16 + 20,
1887 .vdisplay = 240,
1888 .vsync_start = 240 + 2,
1889 .vsync_end = 240 + 2 + 6,
1890 .vtotal = 240 + 2 + 6 + 2,
1891 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1892 },
1893 { /* 50 Hz */
1894 .clock = 5400,
1895 .hdisplay = 320,
1896 .hsync_start = 320 + 56,
1897 .hsync_end = 320 + 56 + 16,
1898 .htotal = 320 + 56 + 16 + 40,
1899 .vdisplay = 240,
1900 .vsync_start = 240 + 2,
1901 .vsync_end = 240 + 2 + 6,
1902 .vtotal = 240 + 2 + 6 + 2,
1903 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1904 },
1905 };
1906
1907 static const struct panel_desc frida_frd350h54004 = {
1908 .modes = frida_frd350h54004_modes,
1909 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
1910 .bpc = 8,
1911 .size = {
1912 .width = 77,
1913 .height = 64,
1914 },
1915 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1916 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1917 .connector_type = DRM_MODE_CONNECTOR_DPI,
1918 };
1919
1920 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1921 .clock = 67185,
1922 .hdisplay = 800,
1923 .hsync_start = 800 + 20,
1924 .hsync_end = 800 + 20 + 24,
1925 .htotal = 800 + 20 + 24 + 20,
1926 .vdisplay = 1280,
1927 .vsync_start = 1280 + 4,
1928 .vsync_end = 1280 + 4 + 8,
1929 .vtotal = 1280 + 4 + 8 + 4,
1930 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1931 };
1932
1933 static const struct panel_desc friendlyarm_hd702e = {
1934 .modes = &friendlyarm_hd702e_mode,
1935 .num_modes = 1,
1936 .size = {
1937 .width = 94,
1938 .height = 151,
1939 },
1940 };
1941
1942 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1943 .clock = 9000,
1944 .hdisplay = 480,
1945 .hsync_start = 480 + 5,
1946 .hsync_end = 480 + 5 + 1,
1947 .htotal = 480 + 5 + 1 + 40,
1948 .vdisplay = 272,
1949 .vsync_start = 272 + 8,
1950 .vsync_end = 272 + 8 + 1,
1951 .vtotal = 272 + 8 + 1 + 8,
1952 };
1953
1954 static const struct panel_desc giantplus_gpg482739qs5 = {
1955 .modes = &giantplus_gpg482739qs5_mode,
1956 .num_modes = 1,
1957 .bpc = 8,
1958 .size = {
1959 .width = 95,
1960 .height = 54,
1961 },
1962 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1963 };
1964
1965 static const struct display_timing giantplus_gpm940b0_timing = {
1966 .pixelclock = { 13500000, 27000000, 27500000 },
1967 .hactive = { 320, 320, 320 },
1968 .hfront_porch = { 14, 686, 718 },
1969 .hback_porch = { 50, 70, 255 },
1970 .hsync_len = { 1, 1, 1 },
1971 .vactive = { 240, 240, 240 },
1972 .vfront_porch = { 1, 1, 179 },
1973 .vback_porch = { 1, 21, 31 },
1974 .vsync_len = { 1, 1, 6 },
1975 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1976 };
1977
1978 static const struct panel_desc giantplus_gpm940b0 = {
1979 .timings = &giantplus_gpm940b0_timing,
1980 .num_timings = 1,
1981 .bpc = 8,
1982 .size = {
1983 .width = 60,
1984 .height = 45,
1985 },
1986 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1987 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1988 };
1989
1990 static const struct display_timing hannstar_hsd070pww1_timing = {
1991 .pixelclock = { 64300000, 71100000, 82000000 },
1992 .hactive = { 1280, 1280, 1280 },
1993 .hfront_porch = { 1, 1, 10 },
1994 .hback_porch = { 1, 1, 10 },
1995 /*
1996 * According to the data sheet, the minimum horizontal blanking interval
1997 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1998 * minimum working horizontal blanking interval to be 60 clocks.
1999 */
2000 .hsync_len = { 58, 158, 661 },
2001 .vactive = { 800, 800, 800 },
2002 .vfront_porch = { 1, 1, 10 },
2003 .vback_porch = { 1, 1, 10 },
2004 .vsync_len = { 1, 21, 203 },
2005 .flags = DISPLAY_FLAGS_DE_HIGH,
2006 };
2007
2008 static const struct panel_desc hannstar_hsd070pww1 = {
2009 .timings = &hannstar_hsd070pww1_timing,
2010 .num_timings = 1,
2011 .bpc = 6,
2012 .size = {
2013 .width = 151,
2014 .height = 94,
2015 },
2016 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2017 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2018 };
2019
2020 static const struct display_timing hannstar_hsd100pxn1_timing = {
2021 .pixelclock = { 55000000, 65000000, 75000000 },
2022 .hactive = { 1024, 1024, 1024 },
2023 .hfront_porch = { 40, 40, 40 },
2024 .hback_porch = { 220, 220, 220 },
2025 .hsync_len = { 20, 60, 100 },
2026 .vactive = { 768, 768, 768 },
2027 .vfront_porch = { 7, 7, 7 },
2028 .vback_porch = { 21, 21, 21 },
2029 .vsync_len = { 10, 10, 10 },
2030 .flags = DISPLAY_FLAGS_DE_HIGH,
2031 };
2032
2033 static const struct panel_desc hannstar_hsd100pxn1 = {
2034 .timings = &hannstar_hsd100pxn1_timing,
2035 .num_timings = 1,
2036 .bpc = 6,
2037 .size = {
2038 .width = 203,
2039 .height = 152,
2040 },
2041 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2042 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2043 };
2044
2045 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2046 .clock = 33333,
2047 .hdisplay = 800,
2048 .hsync_start = 800 + 85,
2049 .hsync_end = 800 + 85 + 86,
2050 .htotal = 800 + 85 + 86 + 85,
2051 .vdisplay = 480,
2052 .vsync_start = 480 + 16,
2053 .vsync_end = 480 + 16 + 13,
2054 .vtotal = 480 + 16 + 13 + 16,
2055 };
2056
2057 static const struct panel_desc hitachi_tx23d38vm0caa = {
2058 .modes = &hitachi_tx23d38vm0caa_mode,
2059 .num_modes = 1,
2060 .bpc = 6,
2061 .size = {
2062 .width = 195,
2063 .height = 117,
2064 },
2065 .delay = {
2066 .enable = 160,
2067 .disable = 160,
2068 },
2069 };
2070
2071 static const struct drm_display_mode innolux_at043tn24_mode = {
2072 .clock = 9000,
2073 .hdisplay = 480,
2074 .hsync_start = 480 + 2,
2075 .hsync_end = 480 + 2 + 41,
2076 .htotal = 480 + 2 + 41 + 2,
2077 .vdisplay = 272,
2078 .vsync_start = 272 + 2,
2079 .vsync_end = 272 + 2 + 10,
2080 .vtotal = 272 + 2 + 10 + 2,
2081 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2082 };
2083
2084 static const struct panel_desc innolux_at043tn24 = {
2085 .modes = &innolux_at043tn24_mode,
2086 .num_modes = 1,
2087 .bpc = 8,
2088 .size = {
2089 .width = 95,
2090 .height = 54,
2091 },
2092 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2093 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2094 };
2095
2096 static const struct drm_display_mode innolux_at070tn92_mode = {
2097 .clock = 33333,
2098 .hdisplay = 800,
2099 .hsync_start = 800 + 210,
2100 .hsync_end = 800 + 210 + 20,
2101 .htotal = 800 + 210 + 20 + 46,
2102 .vdisplay = 480,
2103 .vsync_start = 480 + 22,
2104 .vsync_end = 480 + 22 + 10,
2105 .vtotal = 480 + 22 + 23 + 10,
2106 };
2107
2108 static const struct panel_desc innolux_at070tn92 = {
2109 .modes = &innolux_at070tn92_mode,
2110 .num_modes = 1,
2111 .size = {
2112 .width = 154,
2113 .height = 86,
2114 },
2115 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2116 };
2117
2118 static const struct display_timing innolux_g070y2_l01_timing = {
2119 .pixelclock = { 28000000, 29500000, 32000000 },
2120 .hactive = { 800, 800, 800 },
2121 .hfront_porch = { 61, 91, 141 },
2122 .hback_porch = { 60, 90, 140 },
2123 .hsync_len = { 12, 12, 12 },
2124 .vactive = { 480, 480, 480 },
2125 .vfront_porch = { 4, 9, 30 },
2126 .vback_porch = { 4, 8, 28 },
2127 .vsync_len = { 2, 2, 2 },
2128 .flags = DISPLAY_FLAGS_DE_HIGH,
2129 };
2130
2131 static const struct panel_desc innolux_g070y2_l01 = {
2132 .timings = &innolux_g070y2_l01_timing,
2133 .num_timings = 1,
2134 .bpc = 6,
2135 .size = {
2136 .width = 152,
2137 .height = 91,
2138 },
2139 .delay = {
2140 .prepare = 10,
2141 .enable = 100,
2142 .disable = 100,
2143 .unprepare = 800,
2144 },
2145 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2146 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2147 };
2148
2149 static const struct display_timing innolux_g101ice_l01_timing = {
2150 .pixelclock = { 60400000, 71100000, 74700000 },
2151 .hactive = { 1280, 1280, 1280 },
2152 .hfront_porch = { 41, 80, 100 },
2153 .hback_porch = { 40, 79, 99 },
2154 .hsync_len = { 1, 1, 1 },
2155 .vactive = { 800, 800, 800 },
2156 .vfront_porch = { 5, 11, 14 },
2157 .vback_porch = { 4, 11, 14 },
2158 .vsync_len = { 1, 1, 1 },
2159 .flags = DISPLAY_FLAGS_DE_HIGH,
2160 };
2161
2162 static const struct panel_desc innolux_g101ice_l01 = {
2163 .timings = &innolux_g101ice_l01_timing,
2164 .num_timings = 1,
2165 .bpc = 8,
2166 .size = {
2167 .width = 217,
2168 .height = 135,
2169 },
2170 .delay = {
2171 .enable = 200,
2172 .disable = 200,
2173 },
2174 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2175 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2176 };
2177
2178 static const struct display_timing innolux_g121i1_l01_timing = {
2179 .pixelclock = { 67450000, 71000000, 74550000 },
2180 .hactive = { 1280, 1280, 1280 },
2181 .hfront_porch = { 40, 80, 160 },
2182 .hback_porch = { 39, 79, 159 },
2183 .hsync_len = { 1, 1, 1 },
2184 .vactive = { 800, 800, 800 },
2185 .vfront_porch = { 5, 11, 100 },
2186 .vback_porch = { 4, 11, 99 },
2187 .vsync_len = { 1, 1, 1 },
2188 };
2189
2190 static const struct panel_desc innolux_g121i1_l01 = {
2191 .timings = &innolux_g121i1_l01_timing,
2192 .num_timings = 1,
2193 .bpc = 6,
2194 .size = {
2195 .width = 261,
2196 .height = 163,
2197 },
2198 .delay = {
2199 .enable = 200,
2200 .disable = 20,
2201 },
2202 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2203 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2204 };
2205
2206 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2207 .clock = 65000,
2208 .hdisplay = 1024,
2209 .hsync_start = 1024 + 0,
2210 .hsync_end = 1024 + 1,
2211 .htotal = 1024 + 0 + 1 + 320,
2212 .vdisplay = 768,
2213 .vsync_start = 768 + 38,
2214 .vsync_end = 768 + 38 + 1,
2215 .vtotal = 768 + 38 + 1 + 0,
2216 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2217 };
2218
2219 static const struct panel_desc innolux_g121x1_l03 = {
2220 .modes = &innolux_g121x1_l03_mode,
2221 .num_modes = 1,
2222 .bpc = 6,
2223 .size = {
2224 .width = 246,
2225 .height = 185,
2226 },
2227 .delay = {
2228 .enable = 200,
2229 .unprepare = 200,
2230 .disable = 400,
2231 },
2232 };
2233
2234 /*
2235 * Datasheet specifies that at 60 Hz refresh rate:
2236 * - total horizontal time: { 1506, 1592, 1716 }
2237 * - total vertical time: { 788, 800, 868 }
2238 *
2239 * ...but doesn't go into exactly how that should be split into a front
2240 * porch, back porch, or sync length. For now we'll leave a single setting
2241 * here which allows a bit of tweaking of the pixel clock at the expense of
2242 * refresh rate.
2243 */
2244 static const struct display_timing innolux_n116bge_timing = {
2245 .pixelclock = { 72600000, 76420000, 80240000 },
2246 .hactive = { 1366, 1366, 1366 },
2247 .hfront_porch = { 136, 136, 136 },
2248 .hback_porch = { 60, 60, 60 },
2249 .hsync_len = { 30, 30, 30 },
2250 .vactive = { 768, 768, 768 },
2251 .vfront_porch = { 8, 8, 8 },
2252 .vback_porch = { 12, 12, 12 },
2253 .vsync_len = { 12, 12, 12 },
2254 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2255 };
2256
2257 static const struct panel_desc innolux_n116bge = {
2258 .timings = &innolux_n116bge_timing,
2259 .num_timings = 1,
2260 .bpc = 6,
2261 .size = {
2262 .width = 256,
2263 .height = 144,
2264 },
2265 };
2266
2267 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2268 .clock = 69300,
2269 .hdisplay = 1366,
2270 .hsync_start = 1366 + 16,
2271 .hsync_end = 1366 + 16 + 34,
2272 .htotal = 1366 + 16 + 34 + 50,
2273 .vdisplay = 768,
2274 .vsync_start = 768 + 2,
2275 .vsync_end = 768 + 2 + 6,
2276 .vtotal = 768 + 2 + 6 + 12,
2277 };
2278
2279 static const struct panel_desc innolux_n156bge_l21 = {
2280 .modes = &innolux_n156bge_l21_mode,
2281 .num_modes = 1,
2282 .bpc = 6,
2283 .size = {
2284 .width = 344,
2285 .height = 193,
2286 },
2287 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2288 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2289 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2290 };
2291
2292 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
2293 .clock = 206016,
2294 .hdisplay = 2160,
2295 .hsync_start = 2160 + 48,
2296 .hsync_end = 2160 + 48 + 32,
2297 .htotal = 2160 + 48 + 32 + 80,
2298 .vdisplay = 1440,
2299 .vsync_start = 1440 + 3,
2300 .vsync_end = 1440 + 3 + 10,
2301 .vtotal = 1440 + 3 + 10 + 27,
2302 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2303 };
2304
2305 static const struct panel_desc innolux_p120zdg_bf1 = {
2306 .modes = &innolux_p120zdg_bf1_mode,
2307 .num_modes = 1,
2308 .bpc = 8,
2309 .size = {
2310 .width = 254,
2311 .height = 169,
2312 },
2313 .delay = {
2314 .hpd_absent_delay = 200,
2315 .unprepare = 500,
2316 },
2317 };
2318
2319 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2320 .clock = 51501,
2321 .hdisplay = 1024,
2322 .hsync_start = 1024 + 128,
2323 .hsync_end = 1024 + 128 + 64,
2324 .htotal = 1024 + 128 + 64 + 128,
2325 .vdisplay = 600,
2326 .vsync_start = 600 + 16,
2327 .vsync_end = 600 + 16 + 4,
2328 .vtotal = 600 + 16 + 4 + 16,
2329 };
2330
2331 static const struct panel_desc innolux_zj070na_01p = {
2332 .modes = &innolux_zj070na_01p_mode,
2333 .num_modes = 1,
2334 .bpc = 6,
2335 .size = {
2336 .width = 154,
2337 .height = 90,
2338 },
2339 };
2340
2341 static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
2342 .clock = 138778,
2343 .hdisplay = 1920,
2344 .hsync_start = 1920 + 24,
2345 .hsync_end = 1920 + 24 + 48,
2346 .htotal = 1920 + 24 + 48 + 88,
2347 .vdisplay = 1080,
2348 .vsync_start = 1080 + 3,
2349 .vsync_end = 1080 + 3 + 12,
2350 .vtotal = 1080 + 3 + 12 + 17,
2351 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2352 };
2353
2354 static const struct panel_desc ivo_m133nwf4_r0 = {
2355 .modes = &ivo_m133nwf4_r0_mode,
2356 .num_modes = 1,
2357 .bpc = 8,
2358 .size = {
2359 .width = 294,
2360 .height = 165,
2361 },
2362 .delay = {
2363 .hpd_absent_delay = 200,
2364 .unprepare = 500,
2365 },
2366 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2367 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2368 .connector_type = DRM_MODE_CONNECTOR_eDP,
2369 };
2370
2371 static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = {
2372 .clock = 81000,
2373 .hdisplay = 1366,
2374 .hsync_start = 1366 + 40,
2375 .hsync_end = 1366 + 40 + 32,
2376 .htotal = 1366 + 40 + 32 + 62,
2377 .vdisplay = 768,
2378 .vsync_start = 768 + 5,
2379 .vsync_end = 768 + 5 + 5,
2380 .vtotal = 768 + 5 + 5 + 122,
2381 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2382 };
2383
2384 static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = {
2385 .modes = &kingdisplay_kd116n21_30nv_a010_mode,
2386 .num_modes = 1,
2387 .bpc = 6,
2388 .size = {
2389 .width = 256,
2390 .height = 144,
2391 },
2392 .delay = {
2393 .hpd_absent_delay = 200,
2394 },
2395 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2396 .connector_type = DRM_MODE_CONNECTOR_eDP,
2397 };
2398
2399 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2400 .pixelclock = { 5580000, 5850000, 6200000 },
2401 .hactive = { 320, 320, 320 },
2402 .hfront_porch = { 30, 30, 30 },
2403 .hback_porch = { 30, 30, 30 },
2404 .hsync_len = { 1, 5, 17 },
2405 .vactive = { 240, 240, 240 },
2406 .vfront_porch = { 6, 6, 6 },
2407 .vback_porch = { 5, 5, 5 },
2408 .vsync_len = { 1, 2, 11 },
2409 .flags = DISPLAY_FLAGS_DE_HIGH,
2410 };
2411
2412 static const struct panel_desc koe_tx14d24vm1bpa = {
2413 .timings = &koe_tx14d24vm1bpa_timing,
2414 .num_timings = 1,
2415 .bpc = 6,
2416 .size = {
2417 .width = 115,
2418 .height = 86,
2419 },
2420 };
2421
2422 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2423 .pixelclock = { 151820000, 156720000, 159780000 },
2424 .hactive = { 1920, 1920, 1920 },
2425 .hfront_porch = { 105, 130, 142 },
2426 .hback_porch = { 45, 70, 82 },
2427 .hsync_len = { 30, 30, 30 },
2428 .vactive = { 1200, 1200, 1200},
2429 .vfront_porch = { 3, 5, 10 },
2430 .vback_porch = { 2, 5, 10 },
2431 .vsync_len = { 5, 5, 5 },
2432 };
2433
2434 static const struct panel_desc koe_tx26d202vm0bwa = {
2435 .timings = &koe_tx26d202vm0bwa_timing,
2436 .num_timings = 1,
2437 .bpc = 8,
2438 .size = {
2439 .width = 217,
2440 .height = 136,
2441 },
2442 .delay = {
2443 .prepare = 1000,
2444 .enable = 1000,
2445 .unprepare = 1000,
2446 .disable = 1000,
2447 },
2448 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2449 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2450 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2451 };
2452
2453 static const struct display_timing koe_tx31d200vm0baa_timing = {
2454 .pixelclock = { 39600000, 43200000, 48000000 },
2455 .hactive = { 1280, 1280, 1280 },
2456 .hfront_porch = { 16, 36, 56 },
2457 .hback_porch = { 16, 36, 56 },
2458 .hsync_len = { 8, 8, 8 },
2459 .vactive = { 480, 480, 480 },
2460 .vfront_porch = { 6, 21, 33 },
2461 .vback_porch = { 6, 21, 33 },
2462 .vsync_len = { 8, 8, 8 },
2463 .flags = DISPLAY_FLAGS_DE_HIGH,
2464 };
2465
2466 static const struct panel_desc koe_tx31d200vm0baa = {
2467 .timings = &koe_tx31d200vm0baa_timing,
2468 .num_timings = 1,
2469 .bpc = 6,
2470 .size = {
2471 .width = 292,
2472 .height = 109,
2473 },
2474 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2475 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2476 };
2477
2478 static const struct display_timing kyo_tcg121xglp_timing = {
2479 .pixelclock = { 52000000, 65000000, 71000000 },
2480 .hactive = { 1024, 1024, 1024 },
2481 .hfront_porch = { 2, 2, 2 },
2482 .hback_porch = { 2, 2, 2 },
2483 .hsync_len = { 86, 124, 244 },
2484 .vactive = { 768, 768, 768 },
2485 .vfront_porch = { 2, 2, 2 },
2486 .vback_porch = { 2, 2, 2 },
2487 .vsync_len = { 6, 34, 73 },
2488 .flags = DISPLAY_FLAGS_DE_HIGH,
2489 };
2490
2491 static const struct panel_desc kyo_tcg121xglp = {
2492 .timings = &kyo_tcg121xglp_timing,
2493 .num_timings = 1,
2494 .bpc = 8,
2495 .size = {
2496 .width = 246,
2497 .height = 184,
2498 },
2499 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2500 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2501 };
2502
2503 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2504 .clock = 7000,
2505 .hdisplay = 320,
2506 .hsync_start = 320 + 20,
2507 .hsync_end = 320 + 20 + 30,
2508 .htotal = 320 + 20 + 30 + 38,
2509 .vdisplay = 240,
2510 .vsync_start = 240 + 4,
2511 .vsync_end = 240 + 4 + 3,
2512 .vtotal = 240 + 4 + 3 + 15,
2513 };
2514
2515 static const struct panel_desc lemaker_bl035_rgb_002 = {
2516 .modes = &lemaker_bl035_rgb_002_mode,
2517 .num_modes = 1,
2518 .size = {
2519 .width = 70,
2520 .height = 52,
2521 },
2522 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2523 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2524 };
2525
2526 static const struct drm_display_mode lg_lb070wv8_mode = {
2527 .clock = 33246,
2528 .hdisplay = 800,
2529 .hsync_start = 800 + 88,
2530 .hsync_end = 800 + 88 + 80,
2531 .htotal = 800 + 88 + 80 + 88,
2532 .vdisplay = 480,
2533 .vsync_start = 480 + 10,
2534 .vsync_end = 480 + 10 + 25,
2535 .vtotal = 480 + 10 + 25 + 10,
2536 };
2537
2538 static const struct panel_desc lg_lb070wv8 = {
2539 .modes = &lg_lb070wv8_mode,
2540 .num_modes = 1,
2541 .bpc = 8,
2542 .size = {
2543 .width = 151,
2544 .height = 91,
2545 },
2546 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2547 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2548 };
2549
2550 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
2551 .clock = 200000,
2552 .hdisplay = 1536,
2553 .hsync_start = 1536 + 12,
2554 .hsync_end = 1536 + 12 + 16,
2555 .htotal = 1536 + 12 + 16 + 48,
2556 .vdisplay = 2048,
2557 .vsync_start = 2048 + 8,
2558 .vsync_end = 2048 + 8 + 4,
2559 .vtotal = 2048 + 8 + 4 + 8,
2560 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2561 };
2562
2563 static const struct panel_desc lg_lp079qx1_sp0v = {
2564 .modes = &lg_lp079qx1_sp0v_mode,
2565 .num_modes = 1,
2566 .size = {
2567 .width = 129,
2568 .height = 171,
2569 },
2570 };
2571
2572 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
2573 .clock = 205210,
2574 .hdisplay = 2048,
2575 .hsync_start = 2048 + 150,
2576 .hsync_end = 2048 + 150 + 5,
2577 .htotal = 2048 + 150 + 5 + 5,
2578 .vdisplay = 1536,
2579 .vsync_start = 1536 + 3,
2580 .vsync_end = 1536 + 3 + 1,
2581 .vtotal = 1536 + 3 + 1 + 9,
2582 };
2583
2584 static const struct panel_desc lg_lp097qx1_spa1 = {
2585 .modes = &lg_lp097qx1_spa1_mode,
2586 .num_modes = 1,
2587 .size = {
2588 .width = 208,
2589 .height = 147,
2590 },
2591 };
2592
2593 static const struct drm_display_mode lg_lp120up1_mode = {
2594 .clock = 162300,
2595 .hdisplay = 1920,
2596 .hsync_start = 1920 + 40,
2597 .hsync_end = 1920 + 40 + 40,
2598 .htotal = 1920 + 40 + 40+ 80,
2599 .vdisplay = 1280,
2600 .vsync_start = 1280 + 4,
2601 .vsync_end = 1280 + 4 + 4,
2602 .vtotal = 1280 + 4 + 4 + 12,
2603 };
2604
2605 static const struct panel_desc lg_lp120up1 = {
2606 .modes = &lg_lp120up1_mode,
2607 .num_modes = 1,
2608 .bpc = 8,
2609 .size = {
2610 .width = 267,
2611 .height = 183,
2612 },
2613 .connector_type = DRM_MODE_CONNECTOR_eDP,
2614 };
2615
2616 static const struct drm_display_mode lg_lp129qe_mode = {
2617 .clock = 285250,
2618 .hdisplay = 2560,
2619 .hsync_start = 2560 + 48,
2620 .hsync_end = 2560 + 48 + 32,
2621 .htotal = 2560 + 48 + 32 + 80,
2622 .vdisplay = 1700,
2623 .vsync_start = 1700 + 3,
2624 .vsync_end = 1700 + 3 + 10,
2625 .vtotal = 1700 + 3 + 10 + 36,
2626 };
2627
2628 static const struct panel_desc lg_lp129qe = {
2629 .modes = &lg_lp129qe_mode,
2630 .num_modes = 1,
2631 .bpc = 8,
2632 .size = {
2633 .width = 272,
2634 .height = 181,
2635 },
2636 };
2637
2638 static const struct display_timing logictechno_lt161010_2nh_timing = {
2639 .pixelclock = { 26400000, 33300000, 46800000 },
2640 .hactive = { 800, 800, 800 },
2641 .hfront_porch = { 16, 210, 354 },
2642 .hback_porch = { 46, 46, 46 },
2643 .hsync_len = { 1, 20, 40 },
2644 .vactive = { 480, 480, 480 },
2645 .vfront_porch = { 7, 22, 147 },
2646 .vback_porch = { 23, 23, 23 },
2647 .vsync_len = { 1, 10, 20 },
2648 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2649 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2650 DISPLAY_FLAGS_SYNC_POSEDGE,
2651 };
2652
2653 static const struct panel_desc logictechno_lt161010_2nh = {
2654 .timings = &logictechno_lt161010_2nh_timing,
2655 .num_timings = 1,
2656 .size = {
2657 .width = 154,
2658 .height = 86,
2659 },
2660 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2661 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2662 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2663 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2664 .connector_type = DRM_MODE_CONNECTOR_DPI,
2665 };
2666
2667 static const struct display_timing logictechno_lt170410_2whc_timing = {
2668 .pixelclock = { 68900000, 71100000, 73400000 },
2669 .hactive = { 1280, 1280, 1280 },
2670 .hfront_porch = { 23, 60, 71 },
2671 .hback_porch = { 23, 60, 71 },
2672 .hsync_len = { 15, 40, 47 },
2673 .vactive = { 800, 800, 800 },
2674 .vfront_porch = { 5, 7, 10 },
2675 .vback_porch = { 5, 7, 10 },
2676 .vsync_len = { 6, 9, 12 },
2677 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2678 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2679 DISPLAY_FLAGS_SYNC_POSEDGE,
2680 };
2681
2682 static const struct panel_desc logictechno_lt170410_2whc = {
2683 .timings = &logictechno_lt170410_2whc_timing,
2684 .num_timings = 1,
2685 .size = {
2686 .width = 217,
2687 .height = 136,
2688 },
2689 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2690 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2691 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2692 };
2693
2694 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2695 .clock = 30400,
2696 .hdisplay = 800,
2697 .hsync_start = 800 + 0,
2698 .hsync_end = 800 + 1,
2699 .htotal = 800 + 0 + 1 + 160,
2700 .vdisplay = 480,
2701 .vsync_start = 480 + 0,
2702 .vsync_end = 480 + 48 + 1,
2703 .vtotal = 480 + 48 + 1 + 0,
2704 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2705 };
2706
2707 static const struct drm_display_mode logicpd_type_28_mode = {
2708 .clock = 9107,
2709 .hdisplay = 480,
2710 .hsync_start = 480 + 3,
2711 .hsync_end = 480 + 3 + 42,
2712 .htotal = 480 + 3 + 42 + 2,
2713
2714 .vdisplay = 272,
2715 .vsync_start = 272 + 2,
2716 .vsync_end = 272 + 2 + 11,
2717 .vtotal = 272 + 2 + 11 + 3,
2718 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2719 };
2720
2721 static const struct panel_desc logicpd_type_28 = {
2722 .modes = &logicpd_type_28_mode,
2723 .num_modes = 1,
2724 .bpc = 8,
2725 .size = {
2726 .width = 105,
2727 .height = 67,
2728 },
2729 .delay = {
2730 .prepare = 200,
2731 .enable = 200,
2732 .unprepare = 200,
2733 .disable = 200,
2734 },
2735 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2736 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2737 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2738 .connector_type = DRM_MODE_CONNECTOR_DPI,
2739 };
2740
2741 static const struct panel_desc mitsubishi_aa070mc01 = {
2742 .modes = &mitsubishi_aa070mc01_mode,
2743 .num_modes = 1,
2744 .bpc = 8,
2745 .size = {
2746 .width = 152,
2747 .height = 91,
2748 },
2749
2750 .delay = {
2751 .enable = 200,
2752 .unprepare = 200,
2753 .disable = 400,
2754 },
2755 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2756 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2757 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2758 };
2759
2760 static const struct display_timing nec_nl12880bc20_05_timing = {
2761 .pixelclock = { 67000000, 71000000, 75000000 },
2762 .hactive = { 1280, 1280, 1280 },
2763 .hfront_porch = { 2, 30, 30 },
2764 .hback_porch = { 6, 100, 100 },
2765 .hsync_len = { 2, 30, 30 },
2766 .vactive = { 800, 800, 800 },
2767 .vfront_porch = { 5, 5, 5 },
2768 .vback_porch = { 11, 11, 11 },
2769 .vsync_len = { 7, 7, 7 },
2770 };
2771
2772 static const struct panel_desc nec_nl12880bc20_05 = {
2773 .timings = &nec_nl12880bc20_05_timing,
2774 .num_timings = 1,
2775 .bpc = 8,
2776 .size = {
2777 .width = 261,
2778 .height = 163,
2779 },
2780 .delay = {
2781 .enable = 50,
2782 .disable = 50,
2783 },
2784 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2785 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2786 };
2787
2788 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2789 .clock = 10870,
2790 .hdisplay = 480,
2791 .hsync_start = 480 + 2,
2792 .hsync_end = 480 + 2 + 41,
2793 .htotal = 480 + 2 + 41 + 2,
2794 .vdisplay = 272,
2795 .vsync_start = 272 + 2,
2796 .vsync_end = 272 + 2 + 4,
2797 .vtotal = 272 + 2 + 4 + 2,
2798 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2799 };
2800
2801 static const struct panel_desc nec_nl4827hc19_05b = {
2802 .modes = &nec_nl4827hc19_05b_mode,
2803 .num_modes = 1,
2804 .bpc = 8,
2805 .size = {
2806 .width = 95,
2807 .height = 54,
2808 },
2809 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2810 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2811 };
2812
2813 static const struct drm_display_mode netron_dy_e231732_mode = {
2814 .clock = 66000,
2815 .hdisplay = 1024,
2816 .hsync_start = 1024 + 160,
2817 .hsync_end = 1024 + 160 + 70,
2818 .htotal = 1024 + 160 + 70 + 90,
2819 .vdisplay = 600,
2820 .vsync_start = 600 + 127,
2821 .vsync_end = 600 + 127 + 20,
2822 .vtotal = 600 + 127 + 20 + 3,
2823 };
2824
2825 static const struct panel_desc netron_dy_e231732 = {
2826 .modes = &netron_dy_e231732_mode,
2827 .num_modes = 1,
2828 .size = {
2829 .width = 154,
2830 .height = 87,
2831 },
2832 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2833 };
2834
2835 static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
2836 {
2837 .clock = 138500,
2838 .hdisplay = 1920,
2839 .hsync_start = 1920 + 48,
2840 .hsync_end = 1920 + 48 + 32,
2841 .htotal = 1920 + 48 + 32 + 80,
2842 .vdisplay = 1080,
2843 .vsync_start = 1080 + 3,
2844 .vsync_end = 1080 + 3 + 5,
2845 .vtotal = 1080 + 3 + 5 + 23,
2846 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2847 }, {
2848 .clock = 110920,
2849 .hdisplay = 1920,
2850 .hsync_start = 1920 + 48,
2851 .hsync_end = 1920 + 48 + 32,
2852 .htotal = 1920 + 48 + 32 + 80,
2853 .vdisplay = 1080,
2854 .vsync_start = 1080 + 3,
2855 .vsync_end = 1080 + 3 + 5,
2856 .vtotal = 1080 + 3 + 5 + 23,
2857 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2858 }
2859 };
2860
2861 static const struct panel_desc neweast_wjfh116008a = {
2862 .modes = neweast_wjfh116008a_modes,
2863 .num_modes = 2,
2864 .bpc = 6,
2865 .size = {
2866 .width = 260,
2867 .height = 150,
2868 },
2869 .delay = {
2870 .prepare = 110,
2871 .enable = 20,
2872 .unprepare = 500,
2873 },
2874 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2875 .connector_type = DRM_MODE_CONNECTOR_eDP,
2876 };
2877
2878 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2879 .clock = 9000,
2880 .hdisplay = 480,
2881 .hsync_start = 480 + 2,
2882 .hsync_end = 480 + 2 + 41,
2883 .htotal = 480 + 2 + 41 + 2,
2884 .vdisplay = 272,
2885 .vsync_start = 272 + 2,
2886 .vsync_end = 272 + 2 + 10,
2887 .vtotal = 272 + 2 + 10 + 2,
2888 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2889 };
2890
2891 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2892 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2893 .num_modes = 1,
2894 .bpc = 8,
2895 .size = {
2896 .width = 95,
2897 .height = 54,
2898 },
2899 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2900 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2901 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2902 .connector_type = DRM_MODE_CONNECTOR_DPI,
2903 };
2904
2905 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2906 .pixelclock = { 130000000, 148350000, 163000000 },
2907 .hactive = { 1920, 1920, 1920 },
2908 .hfront_porch = { 80, 100, 100 },
2909 .hback_porch = { 100, 120, 120 },
2910 .hsync_len = { 50, 60, 60 },
2911 .vactive = { 1080, 1080, 1080 },
2912 .vfront_porch = { 12, 30, 30 },
2913 .vback_porch = { 4, 10, 10 },
2914 .vsync_len = { 4, 5, 5 },
2915 };
2916
2917 static const struct panel_desc nlt_nl192108ac18_02d = {
2918 .timings = &nlt_nl192108ac18_02d_timing,
2919 .num_timings = 1,
2920 .bpc = 8,
2921 .size = {
2922 .width = 344,
2923 .height = 194,
2924 },
2925 .delay = {
2926 .unprepare = 500,
2927 },
2928 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2929 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2930 };
2931
2932 static const struct drm_display_mode nvd_9128_mode = {
2933 .clock = 29500,
2934 .hdisplay = 800,
2935 .hsync_start = 800 + 130,
2936 .hsync_end = 800 + 130 + 98,
2937 .htotal = 800 + 0 + 130 + 98,
2938 .vdisplay = 480,
2939 .vsync_start = 480 + 10,
2940 .vsync_end = 480 + 10 + 50,
2941 .vtotal = 480 + 0 + 10 + 50,
2942 };
2943
2944 static const struct panel_desc nvd_9128 = {
2945 .modes = &nvd_9128_mode,
2946 .num_modes = 1,
2947 .bpc = 8,
2948 .size = {
2949 .width = 156,
2950 .height = 88,
2951 },
2952 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2953 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2954 };
2955
2956 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2957 .pixelclock = { 30000000, 30000000, 40000000 },
2958 .hactive = { 800, 800, 800 },
2959 .hfront_porch = { 40, 40, 40 },
2960 .hback_porch = { 40, 40, 40 },
2961 .hsync_len = { 1, 48, 48 },
2962 .vactive = { 480, 480, 480 },
2963 .vfront_porch = { 13, 13, 13 },
2964 .vback_porch = { 29, 29, 29 },
2965 .vsync_len = { 3, 3, 3 },
2966 .flags = DISPLAY_FLAGS_DE_HIGH,
2967 };
2968
2969 static const struct panel_desc okaya_rs800480t_7x0gp = {
2970 .timings = &okaya_rs800480t_7x0gp_timing,
2971 .num_timings = 1,
2972 .bpc = 6,
2973 .size = {
2974 .width = 154,
2975 .height = 87,
2976 },
2977 .delay = {
2978 .prepare = 41,
2979 .enable = 50,
2980 .unprepare = 41,
2981 .disable = 50,
2982 },
2983 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2984 };
2985
2986 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2987 .clock = 9000,
2988 .hdisplay = 480,
2989 .hsync_start = 480 + 5,
2990 .hsync_end = 480 + 5 + 30,
2991 .htotal = 480 + 5 + 30 + 10,
2992 .vdisplay = 272,
2993 .vsync_start = 272 + 8,
2994 .vsync_end = 272 + 8 + 5,
2995 .vtotal = 272 + 8 + 5 + 3,
2996 };
2997
2998 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2999 .modes = &olimex_lcd_olinuxino_43ts_mode,
3000 .num_modes = 1,
3001 .size = {
3002 .width = 95,
3003 .height = 54,
3004 },
3005 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3006 };
3007
3008 /*
3009 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3010 * pixel clocks, but this is the timing that was being used in the Adafruit
3011 * installation instructions.
3012 */
3013 static const struct drm_display_mode ontat_yx700wv03_mode = {
3014 .clock = 29500,
3015 .hdisplay = 800,
3016 .hsync_start = 824,
3017 .hsync_end = 896,
3018 .htotal = 992,
3019 .vdisplay = 480,
3020 .vsync_start = 483,
3021 .vsync_end = 493,
3022 .vtotal = 500,
3023 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3024 };
3025
3026 /*
3027 * Specification at:
3028 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3029 */
3030 static const struct panel_desc ontat_yx700wv03 = {
3031 .modes = &ontat_yx700wv03_mode,
3032 .num_modes = 1,
3033 .bpc = 8,
3034 .size = {
3035 .width = 154,
3036 .height = 83,
3037 },
3038 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3039 };
3040
3041 static const struct drm_display_mode ortustech_com37h3m_mode = {
3042 .clock = 22230,
3043 .hdisplay = 480,
3044 .hsync_start = 480 + 40,
3045 .hsync_end = 480 + 40 + 10,
3046 .htotal = 480 + 40 + 10 + 40,
3047 .vdisplay = 640,
3048 .vsync_start = 640 + 4,
3049 .vsync_end = 640 + 4 + 2,
3050 .vtotal = 640 + 4 + 2 + 4,
3051 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3052 };
3053
3054 static const struct panel_desc ortustech_com37h3m = {
3055 .modes = &ortustech_com37h3m_mode,
3056 .num_modes = 1,
3057 .bpc = 8,
3058 .size = {
3059 .width = 56, /* 56.16mm */
3060 .height = 75, /* 74.88mm */
3061 },
3062 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3063 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3064 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3065 };
3066
3067 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3068 .clock = 25000,
3069 .hdisplay = 480,
3070 .hsync_start = 480 + 10,
3071 .hsync_end = 480 + 10 + 10,
3072 .htotal = 480 + 10 + 10 + 15,
3073 .vdisplay = 800,
3074 .vsync_start = 800 + 3,
3075 .vsync_end = 800 + 3 + 3,
3076 .vtotal = 800 + 3 + 3 + 3,
3077 };
3078
3079 static const struct panel_desc ortustech_com43h4m85ulc = {
3080 .modes = &ortustech_com43h4m85ulc_mode,
3081 .num_modes = 1,
3082 .bpc = 6,
3083 .size = {
3084 .width = 56,
3085 .height = 93,
3086 },
3087 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3088 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3089 .connector_type = DRM_MODE_CONNECTOR_DPI,
3090 };
3091
3092 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3093 .clock = 33000,
3094 .hdisplay = 800,
3095 .hsync_start = 800 + 210,
3096 .hsync_end = 800 + 210 + 30,
3097 .htotal = 800 + 210 + 30 + 16,
3098 .vdisplay = 480,
3099 .vsync_start = 480 + 22,
3100 .vsync_end = 480 + 22 + 13,
3101 .vtotal = 480 + 22 + 13 + 10,
3102 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3103 };
3104
3105 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3106 .modes = &osddisplays_osd070t1718_19ts_mode,
3107 .num_modes = 1,
3108 .bpc = 8,
3109 .size = {
3110 .width = 152,
3111 .height = 91,
3112 },
3113 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3114 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3115 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3116 .connector_type = DRM_MODE_CONNECTOR_DPI,
3117 };
3118
3119 static const struct drm_display_mode pda_91_00156_a0_mode = {
3120 .clock = 33300,
3121 .hdisplay = 800,
3122 .hsync_start = 800 + 1,
3123 .hsync_end = 800 + 1 + 64,
3124 .htotal = 800 + 1 + 64 + 64,
3125 .vdisplay = 480,
3126 .vsync_start = 480 + 1,
3127 .vsync_end = 480 + 1 + 23,
3128 .vtotal = 480 + 1 + 23 + 22,
3129 };
3130
3131 static const struct panel_desc pda_91_00156_a0 = {
3132 .modes = &pda_91_00156_a0_mode,
3133 .num_modes = 1,
3134 .size = {
3135 .width = 152,
3136 .height = 91,
3137 },
3138 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3139 };
3140
3141 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3142 .clock = 24750,
3143 .hdisplay = 800,
3144 .hsync_start = 800 + 54,
3145 .hsync_end = 800 + 54 + 2,
3146 .htotal = 800 + 54 + 2 + 44,
3147 .vdisplay = 480,
3148 .vsync_start = 480 + 49,
3149 .vsync_end = 480 + 49 + 2,
3150 .vtotal = 480 + 49 + 2 + 22,
3151 };
3152
3153 static const struct panel_desc powertip_ph800480t013_idf02 = {
3154 .modes = &powertip_ph800480t013_idf02_mode,
3155 .num_modes = 1,
3156 .size = {
3157 .width = 152,
3158 .height = 91,
3159 },
3160 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3161 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3162 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3163 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3164 .connector_type = DRM_MODE_CONNECTOR_DPI,
3165 };
3166
3167 static const struct drm_display_mode qd43003c0_40_mode = {
3168 .clock = 9000,
3169 .hdisplay = 480,
3170 .hsync_start = 480 + 8,
3171 .hsync_end = 480 + 8 + 4,
3172 .htotal = 480 + 8 + 4 + 39,
3173 .vdisplay = 272,
3174 .vsync_start = 272 + 4,
3175 .vsync_end = 272 + 4 + 10,
3176 .vtotal = 272 + 4 + 10 + 2,
3177 };
3178
3179 static const struct panel_desc qd43003c0_40 = {
3180 .modes = &qd43003c0_40_mode,
3181 .num_modes = 1,
3182 .bpc = 8,
3183 .size = {
3184 .width = 95,
3185 .height = 53,
3186 },
3187 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3188 };
3189
3190 static const struct display_timing rocktech_rk070er9427_timing = {
3191 .pixelclock = { 26400000, 33300000, 46800000 },
3192 .hactive = { 800, 800, 800 },
3193 .hfront_porch = { 16, 210, 354 },
3194 .hback_porch = { 46, 46, 46 },
3195 .hsync_len = { 1, 1, 1 },
3196 .vactive = { 480, 480, 480 },
3197 .vfront_porch = { 7, 22, 147 },
3198 .vback_porch = { 23, 23, 23 },
3199 .vsync_len = { 1, 1, 1 },
3200 .flags = DISPLAY_FLAGS_DE_HIGH,
3201 };
3202
3203 static const struct panel_desc rocktech_rk070er9427 = {
3204 .timings = &rocktech_rk070er9427_timing,
3205 .num_timings = 1,
3206 .bpc = 6,
3207 .size = {
3208 .width = 154,
3209 .height = 86,
3210 },
3211 .delay = {
3212 .prepare = 41,
3213 .enable = 50,
3214 .unprepare = 41,
3215 .disable = 50,
3216 },
3217 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3218 };
3219
3220 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3221 .clock = 71100,
3222 .hdisplay = 1280,
3223 .hsync_start = 1280 + 48,
3224 .hsync_end = 1280 + 48 + 32,
3225 .htotal = 1280 + 48 + 32 + 80,
3226 .vdisplay = 800,
3227 .vsync_start = 800 + 2,
3228 .vsync_end = 800 + 2 + 5,
3229 .vtotal = 800 + 2 + 5 + 16,
3230 };
3231
3232 static const struct panel_desc rocktech_rk101ii01d_ct = {
3233 .modes = &rocktech_rk101ii01d_ct_mode,
3234 .num_modes = 1,
3235 .size = {
3236 .width = 217,
3237 .height = 136,
3238 },
3239 .delay = {
3240 .prepare = 50,
3241 .disable = 50,
3242 },
3243 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3244 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3245 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3246 };
3247
3248 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
3249 .clock = 271560,
3250 .hdisplay = 2560,
3251 .hsync_start = 2560 + 48,
3252 .hsync_end = 2560 + 48 + 32,
3253 .htotal = 2560 + 48 + 32 + 80,
3254 .vdisplay = 1600,
3255 .vsync_start = 1600 + 2,
3256 .vsync_end = 1600 + 2 + 5,
3257 .vtotal = 1600 + 2 + 5 + 57,
3258 };
3259
3260 static const struct panel_desc samsung_lsn122dl01_c01 = {
3261 .modes = &samsung_lsn122dl01_c01_mode,
3262 .num_modes = 1,
3263 .size = {
3264 .width = 263,
3265 .height = 164,
3266 },
3267 };
3268
3269 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3270 .clock = 54030,
3271 .hdisplay = 1024,
3272 .hsync_start = 1024 + 24,
3273 .hsync_end = 1024 + 24 + 136,
3274 .htotal = 1024 + 24 + 136 + 160,
3275 .vdisplay = 600,
3276 .vsync_start = 600 + 3,
3277 .vsync_end = 600 + 3 + 6,
3278 .vtotal = 600 + 3 + 6 + 61,
3279 };
3280
3281 static const struct panel_desc samsung_ltn101nt05 = {
3282 .modes = &samsung_ltn101nt05_mode,
3283 .num_modes = 1,
3284 .bpc = 6,
3285 .size = {
3286 .width = 223,
3287 .height = 125,
3288 },
3289 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3290 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3291 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3292 };
3293
3294 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
3295 .clock = 76300,
3296 .hdisplay = 1366,
3297 .hsync_start = 1366 + 64,
3298 .hsync_end = 1366 + 64 + 48,
3299 .htotal = 1366 + 64 + 48 + 128,
3300 .vdisplay = 768,
3301 .vsync_start = 768 + 2,
3302 .vsync_end = 768 + 2 + 5,
3303 .vtotal = 768 + 2 + 5 + 17,
3304 };
3305
3306 static const struct panel_desc samsung_ltn140at29_301 = {
3307 .modes = &samsung_ltn140at29_301_mode,
3308 .num_modes = 1,
3309 .bpc = 6,
3310 .size = {
3311 .width = 320,
3312 .height = 187,
3313 },
3314 };
3315
3316 static const struct display_timing satoz_sat050at40h12r2_timing = {
3317 .pixelclock = {33300000, 33300000, 50000000},
3318 .hactive = {800, 800, 800},
3319 .hfront_porch = {16, 210, 354},
3320 .hback_porch = {46, 46, 46},
3321 .hsync_len = {1, 1, 40},
3322 .vactive = {480, 480, 480},
3323 .vfront_porch = {7, 22, 147},
3324 .vback_porch = {23, 23, 23},
3325 .vsync_len = {1, 1, 20},
3326 };
3327
3328 static const struct panel_desc satoz_sat050at40h12r2 = {
3329 .timings = &satoz_sat050at40h12r2_timing,
3330 .num_timings = 1,
3331 .bpc = 8,
3332 .size = {
3333 .width = 108,
3334 .height = 65,
3335 },
3336 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3337 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3338 };
3339
3340 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
3341 .clock = 168480,
3342 .hdisplay = 1920,
3343 .hsync_start = 1920 + 48,
3344 .hsync_end = 1920 + 48 + 32,
3345 .htotal = 1920 + 48 + 32 + 80,
3346 .vdisplay = 1280,
3347 .vsync_start = 1280 + 3,
3348 .vsync_end = 1280 + 3 + 10,
3349 .vtotal = 1280 + 3 + 10 + 57,
3350 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3351 };
3352
3353 static const struct panel_desc sharp_ld_d5116z01b = {
3354 .modes = &sharp_ld_d5116z01b_mode,
3355 .num_modes = 1,
3356 .bpc = 8,
3357 .size = {
3358 .width = 260,
3359 .height = 120,
3360 },
3361 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3362 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
3363 };
3364
3365 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3366 .clock = 33260,
3367 .hdisplay = 800,
3368 .hsync_start = 800 + 64,
3369 .hsync_end = 800 + 64 + 128,
3370 .htotal = 800 + 64 + 128 + 64,
3371 .vdisplay = 480,
3372 .vsync_start = 480 + 8,
3373 .vsync_end = 480 + 8 + 2,
3374 .vtotal = 480 + 8 + 2 + 35,
3375 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3376 };
3377
3378 static const struct panel_desc sharp_lq070y3dg3b = {
3379 .modes = &sharp_lq070y3dg3b_mode,
3380 .num_modes = 1,
3381 .bpc = 8,
3382 .size = {
3383 .width = 152, /* 152.4mm */
3384 .height = 91, /* 91.4mm */
3385 },
3386 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3387 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3388 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3389 };
3390
3391 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3392 .clock = 5500,
3393 .hdisplay = 240,
3394 .hsync_start = 240 + 16,
3395 .hsync_end = 240 + 16 + 7,
3396 .htotal = 240 + 16 + 7 + 5,
3397 .vdisplay = 320,
3398 .vsync_start = 320 + 9,
3399 .vsync_end = 320 + 9 + 1,
3400 .vtotal = 320 + 9 + 1 + 7,
3401 };
3402
3403 static const struct panel_desc sharp_lq035q7db03 = {
3404 .modes = &sharp_lq035q7db03_mode,
3405 .num_modes = 1,
3406 .bpc = 6,
3407 .size = {
3408 .width = 54,
3409 .height = 72,
3410 },
3411 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3412 };
3413
3414 static const struct display_timing sharp_lq101k1ly04_timing = {
3415 .pixelclock = { 60000000, 65000000, 80000000 },
3416 .hactive = { 1280, 1280, 1280 },
3417 .hfront_porch = { 20, 20, 20 },
3418 .hback_porch = { 20, 20, 20 },
3419 .hsync_len = { 10, 10, 10 },
3420 .vactive = { 800, 800, 800 },
3421 .vfront_porch = { 4, 4, 4 },
3422 .vback_porch = { 4, 4, 4 },
3423 .vsync_len = { 4, 4, 4 },
3424 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3425 };
3426
3427 static const struct panel_desc sharp_lq101k1ly04 = {
3428 .timings = &sharp_lq101k1ly04_timing,
3429 .num_timings = 1,
3430 .bpc = 8,
3431 .size = {
3432 .width = 217,
3433 .height = 136,
3434 },
3435 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3436 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3437 };
3438
3439 static const struct display_timing sharp_lq123p1jx31_timing = {
3440 .pixelclock = { 252750000, 252750000, 266604720 },
3441 .hactive = { 2400, 2400, 2400 },
3442 .hfront_porch = { 48, 48, 48 },
3443 .hback_porch = { 80, 80, 84 },
3444 .hsync_len = { 32, 32, 32 },
3445 .vactive = { 1600, 1600, 1600 },
3446 .vfront_porch = { 3, 3, 3 },
3447 .vback_porch = { 33, 33, 120 },
3448 .vsync_len = { 10, 10, 10 },
3449 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
3450 };
3451
3452 static const struct panel_desc sharp_lq123p1jx31 = {
3453 .timings = &sharp_lq123p1jx31_timing,
3454 .num_timings = 1,
3455 .bpc = 8,
3456 .size = {
3457 .width = 259,
3458 .height = 173,
3459 },
3460 .delay = {
3461 .prepare = 110,
3462 .enable = 50,
3463 .unprepare = 550,
3464 },
3465 };
3466
3467 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3468 { /* 50 Hz */
3469 .clock = 3000,
3470 .hdisplay = 240,
3471 .hsync_start = 240 + 58,
3472 .hsync_end = 240 + 58 + 1,
3473 .htotal = 240 + 58 + 1 + 1,
3474 .vdisplay = 160,
3475 .vsync_start = 160 + 24,
3476 .vsync_end = 160 + 24 + 10,
3477 .vtotal = 160 + 24 + 10 + 6,
3478 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3479 },
3480 { /* 60 Hz */
3481 .clock = 3000,
3482 .hdisplay = 240,
3483 .hsync_start = 240 + 8,
3484 .hsync_end = 240 + 8 + 1,
3485 .htotal = 240 + 8 + 1 + 1,
3486 .vdisplay = 160,
3487 .vsync_start = 160 + 24,
3488 .vsync_end = 160 + 24 + 10,
3489 .vtotal = 160 + 24 + 10 + 6,
3490 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3491 },
3492 };
3493
3494 static const struct panel_desc sharp_ls020b1dd01d = {
3495 .modes = sharp_ls020b1dd01d_modes,
3496 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3497 .bpc = 6,
3498 .size = {
3499 .width = 42,
3500 .height = 28,
3501 },
3502 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3503 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3504 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3505 | DRM_BUS_FLAG_SHARP_SIGNALS,
3506 };
3507
3508 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3509 .clock = 33300,
3510 .hdisplay = 800,
3511 .hsync_start = 800 + 1,
3512 .hsync_end = 800 + 1 + 64,
3513 .htotal = 800 + 1 + 64 + 64,
3514 .vdisplay = 480,
3515 .vsync_start = 480 + 1,
3516 .vsync_end = 480 + 1 + 23,
3517 .vtotal = 480 + 1 + 23 + 22,
3518 };
3519
3520 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3521 .modes = &shelly_sca07010_bfn_lnn_mode,
3522 .num_modes = 1,
3523 .size = {
3524 .width = 152,
3525 .height = 91,
3526 },
3527 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3528 };
3529
3530 static const struct drm_display_mode starry_kr070pe2t_mode = {
3531 .clock = 33000,
3532 .hdisplay = 800,
3533 .hsync_start = 800 + 209,
3534 .hsync_end = 800 + 209 + 1,
3535 .htotal = 800 + 209 + 1 + 45,
3536 .vdisplay = 480,
3537 .vsync_start = 480 + 22,
3538 .vsync_end = 480 + 22 + 1,
3539 .vtotal = 480 + 22 + 1 + 22,
3540 };
3541
3542 static const struct panel_desc starry_kr070pe2t = {
3543 .modes = &starry_kr070pe2t_mode,
3544 .num_modes = 1,
3545 .bpc = 8,
3546 .size = {
3547 .width = 152,
3548 .height = 86,
3549 },
3550 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3551 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3552 .connector_type = DRM_MODE_CONNECTOR_DPI,
3553 };
3554
3555 static const struct drm_display_mode starry_kr122ea0sra_mode = {
3556 .clock = 147000,
3557 .hdisplay = 1920,
3558 .hsync_start = 1920 + 16,
3559 .hsync_end = 1920 + 16 + 16,
3560 .htotal = 1920 + 16 + 16 + 32,
3561 .vdisplay = 1200,
3562 .vsync_start = 1200 + 15,
3563 .vsync_end = 1200 + 15 + 2,
3564 .vtotal = 1200 + 15 + 2 + 18,
3565 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3566 };
3567
3568 static const struct panel_desc starry_kr122ea0sra = {
3569 .modes = &starry_kr122ea0sra_mode,
3570 .num_modes = 1,
3571 .size = {
3572 .width = 263,
3573 .height = 164,
3574 },
3575 .delay = {
3576 .prepare = 10 + 200,
3577 .enable = 50,
3578 .unprepare = 10 + 500,
3579 },
3580 };
3581
3582 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3583 .clock = 30000,
3584 .hdisplay = 800,
3585 .hsync_start = 800 + 39,
3586 .hsync_end = 800 + 39 + 47,
3587 .htotal = 800 + 39 + 47 + 39,
3588 .vdisplay = 480,
3589 .vsync_start = 480 + 13,
3590 .vsync_end = 480 + 13 + 2,
3591 .vtotal = 480 + 13 + 2 + 29,
3592 };
3593
3594 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3595 .modes = &tfc_s9700rtwv43tr_01b_mode,
3596 .num_modes = 1,
3597 .bpc = 8,
3598 .size = {
3599 .width = 155,
3600 .height = 90,
3601 },
3602 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3603 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3604 };
3605
3606 static const struct display_timing tianma_tm070jdhg30_timing = {
3607 .pixelclock = { 62600000, 68200000, 78100000 },
3608 .hactive = { 1280, 1280, 1280 },
3609 .hfront_porch = { 15, 64, 159 },
3610 .hback_porch = { 5, 5, 5 },
3611 .hsync_len = { 1, 1, 256 },
3612 .vactive = { 800, 800, 800 },
3613 .vfront_porch = { 3, 40, 99 },
3614 .vback_porch = { 2, 2, 2 },
3615 .vsync_len = { 1, 1, 128 },
3616 .flags = DISPLAY_FLAGS_DE_HIGH,
3617 };
3618
3619 static const struct panel_desc tianma_tm070jdhg30 = {
3620 .timings = &tianma_tm070jdhg30_timing,
3621 .num_timings = 1,
3622 .bpc = 8,
3623 .size = {
3624 .width = 151,
3625 .height = 95,
3626 },
3627 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3628 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3629 };
3630
3631 static const struct panel_desc tianma_tm070jvhg33 = {
3632 .timings = &tianma_tm070jdhg30_timing,
3633 .num_timings = 1,
3634 .bpc = 8,
3635 .size = {
3636 .width = 150,
3637 .height = 94,
3638 },
3639 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3640 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3641 };
3642
3643 static const struct display_timing tianma_tm070rvhg71_timing = {
3644 .pixelclock = { 27700000, 29200000, 39600000 },
3645 .hactive = { 800, 800, 800 },
3646 .hfront_porch = { 12, 40, 212 },
3647 .hback_porch = { 88, 88, 88 },
3648 .hsync_len = { 1, 1, 40 },
3649 .vactive = { 480, 480, 480 },
3650 .vfront_porch = { 1, 13, 88 },
3651 .vback_porch = { 32, 32, 32 },
3652 .vsync_len = { 1, 1, 3 },
3653 .flags = DISPLAY_FLAGS_DE_HIGH,
3654 };
3655
3656 static const struct panel_desc tianma_tm070rvhg71 = {
3657 .timings = &tianma_tm070rvhg71_timing,
3658 .num_timings = 1,
3659 .bpc = 8,
3660 .size = {
3661 .width = 154,
3662 .height = 86,
3663 },
3664 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3665 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3666 };
3667
3668 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3669 {
3670 .clock = 10000,
3671 .hdisplay = 320,
3672 .hsync_start = 320 + 50,
3673 .hsync_end = 320 + 50 + 6,
3674 .htotal = 320 + 50 + 6 + 38,
3675 .vdisplay = 240,
3676 .vsync_start = 240 + 3,
3677 .vsync_end = 240 + 3 + 1,
3678 .vtotal = 240 + 3 + 1 + 17,
3679 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3680 },
3681 };
3682
3683 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3684 .modes = ti_nspire_cx_lcd_mode,
3685 .num_modes = 1,
3686 .bpc = 8,
3687 .size = {
3688 .width = 65,
3689 .height = 49,
3690 },
3691 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3692 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3693 };
3694
3695 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3696 {
3697 .clock = 10000,
3698 .hdisplay = 320,
3699 .hsync_start = 320 + 6,
3700 .hsync_end = 320 + 6 + 6,
3701 .htotal = 320 + 6 + 6 + 6,
3702 .vdisplay = 240,
3703 .vsync_start = 240 + 0,
3704 .vsync_end = 240 + 0 + 1,
3705 .vtotal = 240 + 0 + 1 + 0,
3706 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3707 },
3708 };
3709
3710 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3711 .modes = ti_nspire_classic_lcd_mode,
3712 .num_modes = 1,
3713 /* The grayscale panel has 8 bit for the color .. Y (black) */
3714 .bpc = 8,
3715 .size = {
3716 .width = 71,
3717 .height = 53,
3718 },
3719 /* This is the grayscale bus format */
3720 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3721 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3722 };
3723
3724 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3725 .clock = 79500,
3726 .hdisplay = 1280,
3727 .hsync_start = 1280 + 192,
3728 .hsync_end = 1280 + 192 + 128,
3729 .htotal = 1280 + 192 + 128 + 64,
3730 .vdisplay = 768,
3731 .vsync_start = 768 + 20,
3732 .vsync_end = 768 + 20 + 7,
3733 .vtotal = 768 + 20 + 7 + 3,
3734 };
3735
3736 static const struct panel_desc toshiba_lt089ac29000 = {
3737 .modes = &toshiba_lt089ac29000_mode,
3738 .num_modes = 1,
3739 .size = {
3740 .width = 194,
3741 .height = 116,
3742 },
3743 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3744 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3745 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3746 };
3747
3748 static const struct drm_display_mode tpk_f07a_0102_mode = {
3749 .clock = 33260,
3750 .hdisplay = 800,
3751 .hsync_start = 800 + 40,
3752 .hsync_end = 800 + 40 + 128,
3753 .htotal = 800 + 40 + 128 + 88,
3754 .vdisplay = 480,
3755 .vsync_start = 480 + 10,
3756 .vsync_end = 480 + 10 + 2,
3757 .vtotal = 480 + 10 + 2 + 33,
3758 };
3759
3760 static const struct panel_desc tpk_f07a_0102 = {
3761 .modes = &tpk_f07a_0102_mode,
3762 .num_modes = 1,
3763 .size = {
3764 .width = 152,
3765 .height = 91,
3766 },
3767 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3768 };
3769
3770 static const struct drm_display_mode tpk_f10a_0102_mode = {
3771 .clock = 45000,
3772 .hdisplay = 1024,
3773 .hsync_start = 1024 + 176,
3774 .hsync_end = 1024 + 176 + 5,
3775 .htotal = 1024 + 176 + 5 + 88,
3776 .vdisplay = 600,
3777 .vsync_start = 600 + 20,
3778 .vsync_end = 600 + 20 + 5,
3779 .vtotal = 600 + 20 + 5 + 25,
3780 };
3781
3782 static const struct panel_desc tpk_f10a_0102 = {
3783 .modes = &tpk_f10a_0102_mode,
3784 .num_modes = 1,
3785 .size = {
3786 .width = 223,
3787 .height = 125,
3788 },
3789 };
3790
3791 static const struct display_timing urt_umsh_8596md_timing = {
3792 .pixelclock = { 33260000, 33260000, 33260000 },
3793 .hactive = { 800, 800, 800 },
3794 .hfront_porch = { 41, 41, 41 },
3795 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3796 .hsync_len = { 71, 128, 128 },
3797 .vactive = { 480, 480, 480 },
3798 .vfront_porch = { 10, 10, 10 },
3799 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3800 .vsync_len = { 2, 2, 2 },
3801 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3802 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3803 };
3804
3805 static const struct panel_desc urt_umsh_8596md_lvds = {
3806 .timings = &urt_umsh_8596md_timing,
3807 .num_timings = 1,
3808 .bpc = 6,
3809 .size = {
3810 .width = 152,
3811 .height = 91,
3812 },
3813 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3814 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3815 };
3816
3817 static const struct panel_desc urt_umsh_8596md_parallel = {
3818 .timings = &urt_umsh_8596md_timing,
3819 .num_timings = 1,
3820 .bpc = 6,
3821 .size = {
3822 .width = 152,
3823 .height = 91,
3824 },
3825 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3826 };
3827
3828 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3829 .clock = 33333,
3830 .hdisplay = 800,
3831 .hsync_start = 800 + 210,
3832 .hsync_end = 800 + 210 + 20,
3833 .htotal = 800 + 210 + 20 + 46,
3834 .vdisplay = 480,
3835 .vsync_start = 480 + 22,
3836 .vsync_end = 480 + 22 + 10,
3837 .vtotal = 480 + 22 + 10 + 23,
3838 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3839 };
3840
3841 static const struct panel_desc vl050_8048nt_c01 = {
3842 .modes = &vl050_8048nt_c01_mode,
3843 .num_modes = 1,
3844 .bpc = 8,
3845 .size = {
3846 .width = 120,
3847 .height = 76,
3848 },
3849 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3850 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3851 };
3852
3853 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3854 .clock = 6410,
3855 .hdisplay = 320,
3856 .hsync_start = 320 + 20,
3857 .hsync_end = 320 + 20 + 30,
3858 .htotal = 320 + 20 + 30 + 38,
3859 .vdisplay = 240,
3860 .vsync_start = 240 + 4,
3861 .vsync_end = 240 + 4 + 3,
3862 .vtotal = 240 + 4 + 3 + 15,
3863 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3864 };
3865
3866 static const struct panel_desc winstar_wf35ltiacd = {
3867 .modes = &winstar_wf35ltiacd_mode,
3868 .num_modes = 1,
3869 .bpc = 8,
3870 .size = {
3871 .width = 70,
3872 .height = 53,
3873 },
3874 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3875 };
3876
3877 static const struct drm_display_mode arm_rtsm_mode[] = {
3878 {
3879 .clock = 65000,
3880 .hdisplay = 1024,
3881 .hsync_start = 1024 + 24,
3882 .hsync_end = 1024 + 24 + 136,
3883 .htotal = 1024 + 24 + 136 + 160,
3884 .vdisplay = 768,
3885 .vsync_start = 768 + 3,
3886 .vsync_end = 768 + 3 + 6,
3887 .vtotal = 768 + 3 + 6 + 29,
3888 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3889 },
3890 };
3891
3892 static const struct panel_desc arm_rtsm = {
3893 .modes = arm_rtsm_mode,
3894 .num_modes = 1,
3895 .bpc = 8,
3896 .size = {
3897 .width = 400,
3898 .height = 300,
3899 },
3900 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3901 };
3902
3903 static const struct of_device_id platform_of_match[] = {
3904 {
3905 .compatible = "ampire,am-1280800n3tzqw-t00h",
3906 .data = &ire_am_1280800n3tzqw_t00h,
3907 }, {
3908 .compatible = "ampire,am-480272h3tmqw-t01h",
3909 .data = &ire_am_480272h3tmqw_t01h,
3910 }, {
3911 .compatible = "ampire,am800480r3tmqwa1h",
3912 .data = &ire_am800480r3tmqwa1h,
3913 }, {
3914 .compatible = "arm,rtsm-display",
3915 .data = &arm_rtsm,
3916 }, {
3917 .compatible = "armadeus,st0700-adapt",
3918 .data = &armadeus_st0700_adapt,
3919 }, {
3920 .compatible = "auo,b101aw03",
3921 .data = &auo_b101aw03,
3922 }, {
3923 .compatible = "auo,b101ean01",
3924 .data = &auo_b101ean01,
3925 }, {
3926 .compatible = "auo,b101xtn01",
3927 .data = &auo_b101xtn01,
3928 }, {
3929 .compatible = "auo,b116xa01",
3930 .data = &auo_b116xak01,
3931 }, {
3932 .compatible = "auo,b116xw03",
3933 .data = &auo_b116xw03,
3934 }, {
3935 .compatible = "auo,b133htn01",
3936 .data = &auo_b133htn01,
3937 }, {
3938 .compatible = "auo,b133xtn01",
3939 .data = &auo_b133xtn01,
3940 }, {
3941 .compatible = "auo,g070vvn01",
3942 .data = &auo_g070vvn01,
3943 }, {
3944 .compatible = "auo,g101evn010",
3945 .data = &auo_g101evn010,
3946 }, {
3947 .compatible = "auo,g104sn02",
3948 .data = &auo_g104sn02,
3949 }, {
3950 .compatible = "auo,g121ean01",
3951 .data = &auo_g121ean01,
3952 }, {
3953 .compatible = "auo,g133han01",
3954 .data = &auo_g133han01,
3955 }, {
3956 .compatible = "auo,g156xtn01",
3957 .data = &auo_g156xtn01,
3958 }, {
3959 .compatible = "auo,g185han01",
3960 .data = &auo_g185han01,
3961 }, {
3962 .compatible = "auo,g190ean01",
3963 .data = &auo_g190ean01,
3964 }, {
3965 .compatible = "auo,p320hvn03",
3966 .data = &auo_p320hvn03,
3967 }, {
3968 .compatible = "auo,t215hvn01",
3969 .data = &auo_t215hvn01,
3970 }, {
3971 .compatible = "avic,tm070ddh03",
3972 .data = &avic_tm070ddh03,
3973 }, {
3974 .compatible = "bananapi,s070wv20-ct16",
3975 .data = &bananapi_s070wv20_ct16,
3976 }, {
3977 .compatible = "boe,hv070wsa-100",
3978 .data = &boe_hv070wsa
3979 }, {
3980 .compatible = "boe,nv101wxmn51",
3981 .data = &boe_nv101wxmn51,
3982 }, {
3983 .compatible = "boe,nv133fhm-n61",
3984 .data = &boe_nv133fhm_n61,
3985 }, {
3986 .compatible = "boe,nv133fhm-n62",
3987 .data = &boe_nv133fhm_n61,
3988 }, {
3989 .compatible = "boe,nv140fhmn49",
3990 .data = &boe_nv140fhmn49,
3991 }, {
3992 .compatible = "cdtech,s043wq26h-ct7",
3993 .data = &cdtech_s043wq26h_ct7,
3994 }, {
3995 .compatible = "cdtech,s070pws19hp-fc21",
3996 .data = &cdtech_s070pws19hp_fc21,
3997 }, {
3998 .compatible = "cdtech,s070swv29hg-dc44",
3999 .data = &cdtech_s070swv29hg_dc44,
4000 }, {
4001 .compatible = "cdtech,s070wv95-ct16",
4002 .data = &cdtech_s070wv95_ct16,
4003 }, {
4004 .compatible = "chefree,ch101olhlwh-002",
4005 .data = &chefree_ch101olhlwh_002,
4006 }, {
4007 .compatible = "chunghwa,claa070wp03xg",
4008 .data = &chunghwa_claa070wp03xg,
4009 }, {
4010 .compatible = "chunghwa,claa101wa01a",
4011 .data = &chunghwa_claa101wa01a
4012 }, {
4013 .compatible = "chunghwa,claa101wb01",
4014 .data = &chunghwa_claa101wb01
4015 }, {
4016 .compatible = "dataimage,scf0700c48ggu18",
4017 .data = &dataimage_scf0700c48ggu18,
4018 }, {
4019 .compatible = "dlc,dlc0700yzg-1",
4020 .data = &dlc_dlc0700yzg_1,
4021 }, {
4022 .compatible = "dlc,dlc1010gig",
4023 .data = &dlc_dlc1010gig,
4024 }, {
4025 .compatible = "edt,et035012dm6",
4026 .data = &edt_et035012dm6,
4027 }, {
4028 .compatible = "edt,etm043080dh6gp",
4029 .data = &edt_etm043080dh6gp,
4030 }, {
4031 .compatible = "edt,etm0430g0dh6",
4032 .data = &edt_etm0430g0dh6,
4033 }, {
4034 .compatible = "edt,et057090dhu",
4035 .data = &edt_et057090dhu,
4036 }, {
4037 .compatible = "edt,et070080dh6",
4038 .data = &edt_etm0700g0dh6,
4039 }, {
4040 .compatible = "edt,etm0700g0dh6",
4041 .data = &edt_etm0700g0dh6,
4042 }, {
4043 .compatible = "edt,etm0700g0bdh6",
4044 .data = &edt_etm0700g0bdh6,
4045 }, {
4046 .compatible = "edt,etm0700g0edh6",
4047 .data = &edt_etm0700g0bdh6,
4048 }, {
4049 .compatible = "evervision,vgg804821",
4050 .data = &evervision_vgg804821,
4051 }, {
4052 .compatible = "foxlink,fl500wvr00-a0t",
4053 .data = &foxlink_fl500wvr00_a0t,
4054 }, {
4055 .compatible = "frida,frd350h54004",
4056 .data = &frida_frd350h54004,
4057 }, {
4058 .compatible = "friendlyarm,hd702e",
4059 .data = &friendlyarm_hd702e,
4060 }, {
4061 .compatible = "giantplus,gpg482739qs5",
4062 .data = &giantplus_gpg482739qs5
4063 }, {
4064 .compatible = "giantplus,gpm940b0",
4065 .data = &giantplus_gpm940b0,
4066 }, {
4067 .compatible = "hannstar,hsd070pww1",
4068 .data = &hannstar_hsd070pww1,
4069 }, {
4070 .compatible = "hannstar,hsd100pxn1",
4071 .data = &hannstar_hsd100pxn1,
4072 }, {
4073 .compatible = "hit,tx23d38vm0caa",
4074 .data = &hitachi_tx23d38vm0caa
4075 }, {
4076 .compatible = "innolux,at043tn24",
4077 .data = &innolux_at043tn24,
4078 }, {
4079 .compatible = "innolux,at070tn92",
4080 .data = &innolux_at070tn92,
4081 }, {
4082 .compatible = "innolux,g070y2-l01",
4083 .data = &innolux_g070y2_l01,
4084 }, {
4085 .compatible = "innolux,g101ice-l01",
4086 .data = &innolux_g101ice_l01
4087 }, {
4088 .compatible = "innolux,g121i1-l01",
4089 .data = &innolux_g121i1_l01
4090 }, {
4091 .compatible = "innolux,g121x1-l03",
4092 .data = &innolux_g121x1_l03,
4093 }, {
4094 .compatible = "innolux,n116bge",
4095 .data = &innolux_n116bge,
4096 }, {
4097 .compatible = "innolux,n156bge-l21",
4098 .data = &innolux_n156bge_l21,
4099 }, {
4100 .compatible = "innolux,p120zdg-bf1",
4101 .data = &innolux_p120zdg_bf1,
4102 }, {
4103 .compatible = "innolux,zj070na-01p",
4104 .data = &innolux_zj070na_01p,
4105 }, {
4106 .compatible = "ivo,m133nwf4-r0",
4107 .data = &ivo_m133nwf4_r0,
4108 }, {
4109 .compatible = "kingdisplay,kd116n21-30nv-a010",
4110 .data = &kingdisplay_kd116n21_30nv_a010,
4111 }, {
4112 .compatible = "koe,tx14d24vm1bpa",
4113 .data = &koe_tx14d24vm1bpa,
4114 }, {
4115 .compatible = "koe,tx26d202vm0bwa",
4116 .data = &koe_tx26d202vm0bwa,
4117 }, {
4118 .compatible = "koe,tx31d200vm0baa",
4119 .data = &koe_tx31d200vm0baa,
4120 }, {
4121 .compatible = "kyo,tcg121xglp",
4122 .data = &kyo_tcg121xglp,
4123 }, {
4124 .compatible = "lemaker,bl035-rgb-002",
4125 .data = &lemaker_bl035_rgb_002,
4126 }, {
4127 .compatible = "lg,lb070wv8",
4128 .data = &lg_lb070wv8,
4129 }, {
4130 .compatible = "lg,lp079qx1-sp0v",
4131 .data = &lg_lp079qx1_sp0v,
4132 }, {
4133 .compatible = "lg,lp097qx1-spa1",
4134 .data = &lg_lp097qx1_spa1,
4135 }, {
4136 .compatible = "lg,lp120up1",
4137 .data = &lg_lp120up1,
4138 }, {
4139 .compatible = "lg,lp129qe",
4140 .data = &lg_lp129qe,
4141 }, {
4142 .compatible = "logicpd,type28",
4143 .data = &logicpd_type_28,
4144 }, {
4145 .compatible = "logictechno,lt161010-2nhc",
4146 .data = &logictechno_lt161010_2nh,
4147 }, {
4148 .compatible = "logictechno,lt161010-2nhr",
4149 .data = &logictechno_lt161010_2nh,
4150 }, {
4151 .compatible = "logictechno,lt170410-2whc",
4152 .data = &logictechno_lt170410_2whc,
4153 }, {
4154 .compatible = "mitsubishi,aa070mc01-ca1",
4155 .data = &mitsubishi_aa070mc01,
4156 }, {
4157 .compatible = "nec,nl12880bc20-05",
4158 .data = &nec_nl12880bc20_05,
4159 }, {
4160 .compatible = "nec,nl4827hc19-05b",
4161 .data = &nec_nl4827hc19_05b,
4162 }, {
4163 .compatible = "netron-dy,e231732",
4164 .data = &netron_dy_e231732,
4165 }, {
4166 .compatible = "neweast,wjfh116008a",
4167 .data = &neweast_wjfh116008a,
4168 }, {
4169 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4170 .data = &newhaven_nhd_43_480272ef_atxl,
4171 }, {
4172 .compatible = "nlt,nl192108ac18-02d",
4173 .data = &nlt_nl192108ac18_02d,
4174 }, {
4175 .compatible = "nvd,9128",
4176 .data = &nvd_9128,
4177 }, {
4178 .compatible = "okaya,rs800480t-7x0gp",
4179 .data = &okaya_rs800480t_7x0gp,
4180 }, {
4181 .compatible = "olimex,lcd-olinuxino-43-ts",
4182 .data = &olimex_lcd_olinuxino_43ts,
4183 }, {
4184 .compatible = "ontat,yx700wv03",
4185 .data = &ontat_yx700wv03,
4186 }, {
4187 .compatible = "ortustech,com37h3m05dtc",
4188 .data = &ortustech_com37h3m,
4189 }, {
4190 .compatible = "ortustech,com37h3m99dtc",
4191 .data = &ortustech_com37h3m,
4192 }, {
4193 .compatible = "ortustech,com43h4m85ulc",
4194 .data = &ortustech_com43h4m85ulc,
4195 }, {
4196 .compatible = "osddisplays,osd070t1718-19ts",
4197 .data = &osddisplays_osd070t1718_19ts,
4198 }, {
4199 .compatible = "pda,91-00156-a0",
4200 .data = &pda_91_00156_a0,
4201 }, {
4202 .compatible = "powertip,ph800480t013-idf02",
4203 .data = &powertip_ph800480t013_idf02,
4204 }, {
4205 .compatible = "qiaodian,qd43003c0-40",
4206 .data = &qd43003c0_40,
4207 }, {
4208 .compatible = "rocktech,rk070er9427",
4209 .data = &rocktech_rk070er9427,
4210 }, {
4211 .compatible = "rocktech,rk101ii01d-ct",
4212 .data = &rocktech_rk101ii01d_ct,
4213 }, {
4214 .compatible = "samsung,lsn122dl01-c01",
4215 .data = &samsung_lsn122dl01_c01,
4216 }, {
4217 .compatible = "samsung,ltn101nt05",
4218 .data = &samsung_ltn101nt05,
4219 }, {
4220 .compatible = "samsung,ltn140at29-301",
4221 .data = &samsung_ltn140at29_301,
4222 }, {
4223 .compatible = "satoz,sat050at40h12r2",
4224 .data = &satoz_sat050at40h12r2,
4225 }, {
4226 .compatible = "sharp,ld-d5116z01b",
4227 .data = &sharp_ld_d5116z01b,
4228 }, {
4229 .compatible = "sharp,lq035q7db03",
4230 .data = &sharp_lq035q7db03,
4231 }, {
4232 .compatible = "sharp,lq070y3dg3b",
4233 .data = &sharp_lq070y3dg3b,
4234 }, {
4235 .compatible = "sharp,lq101k1ly04",
4236 .data = &sharp_lq101k1ly04,
4237 }, {
4238 .compatible = "sharp,lq123p1jx31",
4239 .data = &sharp_lq123p1jx31,
4240 }, {
4241 .compatible = "sharp,ls020b1dd01d",
4242 .data = &sharp_ls020b1dd01d,
4243 }, {
4244 .compatible = "shelly,sca07010-bfn-lnn",
4245 .data = &shelly_sca07010_bfn_lnn,
4246 }, {
4247 .compatible = "starry,kr070pe2t",
4248 .data = &starry_kr070pe2t,
4249 }, {
4250 .compatible = "starry,kr122ea0sra",
4251 .data = &starry_kr122ea0sra,
4252 }, {
4253 .compatible = "tfc,s9700rtwv43tr-01b",
4254 .data = &tfc_s9700rtwv43tr_01b,
4255 }, {
4256 .compatible = "tianma,tm070jdhg30",
4257 .data = &tianma_tm070jdhg30,
4258 }, {
4259 .compatible = "tianma,tm070jvhg33",
4260 .data = &tianma_tm070jvhg33,
4261 }, {
4262 .compatible = "tianma,tm070rvhg71",
4263 .data = &tianma_tm070rvhg71,
4264 }, {
4265 .compatible = "ti,nspire-cx-lcd-panel",
4266 .data = &ti_nspire_cx_lcd_panel,
4267 }, {
4268 .compatible = "ti,nspire-classic-lcd-panel",
4269 .data = &ti_nspire_classic_lcd_panel,
4270 }, {
4271 .compatible = "toshiba,lt089ac29000",
4272 .data = &toshiba_lt089ac29000,
4273 }, {
4274 .compatible = "tpk,f07a-0102",
4275 .data = &tpk_f07a_0102,
4276 }, {
4277 .compatible = "tpk,f10a-0102",
4278 .data = &tpk_f10a_0102,
4279 }, {
4280 .compatible = "urt,umsh-8596md-t",
4281 .data = &urt_umsh_8596md_parallel,
4282 }, {
4283 .compatible = "urt,umsh-8596md-1t",
4284 .data = &urt_umsh_8596md_parallel,
4285 }, {
4286 .compatible = "urt,umsh-8596md-7t",
4287 .data = &urt_umsh_8596md_parallel,
4288 }, {
4289 .compatible = "urt,umsh-8596md-11t",
4290 .data = &urt_umsh_8596md_lvds,
4291 }, {
4292 .compatible = "urt,umsh-8596md-19t",
4293 .data = &urt_umsh_8596md_lvds,
4294 }, {
4295 .compatible = "urt,umsh-8596md-20t",
4296 .data = &urt_umsh_8596md_parallel,
4297 }, {
4298 .compatible = "vxt,vl050-8048nt-c01",
4299 .data = &vl050_8048nt_c01,
4300 }, {
4301 .compatible = "winstar,wf35ltiacd",
4302 .data = &winstar_wf35ltiacd,
4303 }, {
4304 /* Must be the last entry */
4305 .compatible = "panel-dpi",
4306 .data = &panel_dpi,
4307 }, {
4308 /* sentinel */
4309 }
4310 };
4311 MODULE_DEVICE_TABLE(of, platform_of_match);
4312
panel_simple_platform_probe(struct platform_device * pdev)4313 static int panel_simple_platform_probe(struct platform_device *pdev)
4314 {
4315 const struct of_device_id *id;
4316
4317 id = of_match_node(platform_of_match, pdev->dev.of_node);
4318 if (!id)
4319 return -ENODEV;
4320
4321 return panel_simple_probe(&pdev->dev, id->data);
4322 }
4323
panel_simple_platform_remove(struct platform_device * pdev)4324 static int panel_simple_platform_remove(struct platform_device *pdev)
4325 {
4326 return panel_simple_remove(&pdev->dev);
4327 }
4328
panel_simple_platform_shutdown(struct platform_device * pdev)4329 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4330 {
4331 panel_simple_shutdown(&pdev->dev);
4332 }
4333
4334 static struct platform_driver panel_simple_platform_driver = {
4335 .driver = {
4336 .name = "panel-simple",
4337 .of_match_table = platform_of_match,
4338 },
4339 .probe = panel_simple_platform_probe,
4340 .remove = panel_simple_platform_remove,
4341 .shutdown = panel_simple_platform_shutdown,
4342 };
4343
4344 struct panel_desc_dsi {
4345 struct panel_desc desc;
4346
4347 unsigned long flags;
4348 enum mipi_dsi_pixel_format format;
4349 unsigned int lanes;
4350 };
4351
4352 static const struct drm_display_mode auo_b080uan01_mode = {
4353 .clock = 154500,
4354 .hdisplay = 1200,
4355 .hsync_start = 1200 + 62,
4356 .hsync_end = 1200 + 62 + 4,
4357 .htotal = 1200 + 62 + 4 + 62,
4358 .vdisplay = 1920,
4359 .vsync_start = 1920 + 9,
4360 .vsync_end = 1920 + 9 + 2,
4361 .vtotal = 1920 + 9 + 2 + 8,
4362 };
4363
4364 static const struct panel_desc_dsi auo_b080uan01 = {
4365 .desc = {
4366 .modes = &auo_b080uan01_mode,
4367 .num_modes = 1,
4368 .bpc = 8,
4369 .size = {
4370 .width = 108,
4371 .height = 272,
4372 },
4373 .connector_type = DRM_MODE_CONNECTOR_DSI,
4374 },
4375 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4376 .format = MIPI_DSI_FMT_RGB888,
4377 .lanes = 4,
4378 };
4379
4380 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4381 .clock = 160000,
4382 .hdisplay = 1200,
4383 .hsync_start = 1200 + 120,
4384 .hsync_end = 1200 + 120 + 20,
4385 .htotal = 1200 + 120 + 20 + 21,
4386 .vdisplay = 1920,
4387 .vsync_start = 1920 + 21,
4388 .vsync_end = 1920 + 21 + 3,
4389 .vtotal = 1920 + 21 + 3 + 18,
4390 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4391 };
4392
4393 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4394 .desc = {
4395 .modes = &boe_tv080wum_nl0_mode,
4396 .num_modes = 1,
4397 .size = {
4398 .width = 107,
4399 .height = 172,
4400 },
4401 .connector_type = DRM_MODE_CONNECTOR_DSI,
4402 },
4403 .flags = MIPI_DSI_MODE_VIDEO |
4404 MIPI_DSI_MODE_VIDEO_BURST |
4405 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4406 .format = MIPI_DSI_FMT_RGB888,
4407 .lanes = 4,
4408 };
4409
4410 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4411 .clock = 71000,
4412 .hdisplay = 800,
4413 .hsync_start = 800 + 32,
4414 .hsync_end = 800 + 32 + 1,
4415 .htotal = 800 + 32 + 1 + 57,
4416 .vdisplay = 1280,
4417 .vsync_start = 1280 + 28,
4418 .vsync_end = 1280 + 28 + 1,
4419 .vtotal = 1280 + 28 + 1 + 14,
4420 };
4421
4422 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4423 .desc = {
4424 .modes = &lg_ld070wx3_sl01_mode,
4425 .num_modes = 1,
4426 .bpc = 8,
4427 .size = {
4428 .width = 94,
4429 .height = 151,
4430 },
4431 .connector_type = DRM_MODE_CONNECTOR_DSI,
4432 },
4433 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4434 .format = MIPI_DSI_FMT_RGB888,
4435 .lanes = 4,
4436 };
4437
4438 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4439 .clock = 67000,
4440 .hdisplay = 720,
4441 .hsync_start = 720 + 12,
4442 .hsync_end = 720 + 12 + 4,
4443 .htotal = 720 + 12 + 4 + 112,
4444 .vdisplay = 1280,
4445 .vsync_start = 1280 + 8,
4446 .vsync_end = 1280 + 8 + 4,
4447 .vtotal = 1280 + 8 + 4 + 12,
4448 };
4449
4450 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4451 .desc = {
4452 .modes = &lg_lh500wx1_sd03_mode,
4453 .num_modes = 1,
4454 .bpc = 8,
4455 .size = {
4456 .width = 62,
4457 .height = 110,
4458 },
4459 .connector_type = DRM_MODE_CONNECTOR_DSI,
4460 },
4461 .flags = MIPI_DSI_MODE_VIDEO,
4462 .format = MIPI_DSI_FMT_RGB888,
4463 .lanes = 4,
4464 };
4465
4466 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4467 .clock = 157200,
4468 .hdisplay = 1920,
4469 .hsync_start = 1920 + 154,
4470 .hsync_end = 1920 + 154 + 16,
4471 .htotal = 1920 + 154 + 16 + 32,
4472 .vdisplay = 1200,
4473 .vsync_start = 1200 + 17,
4474 .vsync_end = 1200 + 17 + 2,
4475 .vtotal = 1200 + 17 + 2 + 16,
4476 };
4477
4478 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4479 .desc = {
4480 .modes = &panasonic_vvx10f004b00_mode,
4481 .num_modes = 1,
4482 .bpc = 8,
4483 .size = {
4484 .width = 217,
4485 .height = 136,
4486 },
4487 .connector_type = DRM_MODE_CONNECTOR_DSI,
4488 },
4489 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4490 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4491 .format = MIPI_DSI_FMT_RGB888,
4492 .lanes = 4,
4493 };
4494
4495 static const struct drm_display_mode lg_acx467akm_7_mode = {
4496 .clock = 150000,
4497 .hdisplay = 1080,
4498 .hsync_start = 1080 + 2,
4499 .hsync_end = 1080 + 2 + 2,
4500 .htotal = 1080 + 2 + 2 + 2,
4501 .vdisplay = 1920,
4502 .vsync_start = 1920 + 2,
4503 .vsync_end = 1920 + 2 + 2,
4504 .vtotal = 1920 + 2 + 2 + 2,
4505 };
4506
4507 static const struct panel_desc_dsi lg_acx467akm_7 = {
4508 .desc = {
4509 .modes = &lg_acx467akm_7_mode,
4510 .num_modes = 1,
4511 .bpc = 8,
4512 .size = {
4513 .width = 62,
4514 .height = 110,
4515 },
4516 .connector_type = DRM_MODE_CONNECTOR_DSI,
4517 },
4518 .flags = 0,
4519 .format = MIPI_DSI_FMT_RGB888,
4520 .lanes = 4,
4521 };
4522
4523 static const struct drm_display_mode osd101t2045_53ts_mode = {
4524 .clock = 154500,
4525 .hdisplay = 1920,
4526 .hsync_start = 1920 + 112,
4527 .hsync_end = 1920 + 112 + 16,
4528 .htotal = 1920 + 112 + 16 + 32,
4529 .vdisplay = 1200,
4530 .vsync_start = 1200 + 16,
4531 .vsync_end = 1200 + 16 + 2,
4532 .vtotal = 1200 + 16 + 2 + 16,
4533 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4534 };
4535
4536 static const struct panel_desc_dsi osd101t2045_53ts = {
4537 .desc = {
4538 .modes = &osd101t2045_53ts_mode,
4539 .num_modes = 1,
4540 .bpc = 8,
4541 .size = {
4542 .width = 217,
4543 .height = 136,
4544 },
4545 .connector_type = DRM_MODE_CONNECTOR_DSI,
4546 },
4547 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4548 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4549 MIPI_DSI_MODE_EOT_PACKET,
4550 .format = MIPI_DSI_FMT_RGB888,
4551 .lanes = 4,
4552 };
4553
4554 static const struct of_device_id dsi_of_match[] = {
4555 {
4556 .compatible = "auo,b080uan01",
4557 .data = &auo_b080uan01
4558 }, {
4559 .compatible = "boe,tv080wum-nl0",
4560 .data = &boe_tv080wum_nl0
4561 }, {
4562 .compatible = "lg,ld070wx3-sl01",
4563 .data = &lg_ld070wx3_sl01
4564 }, {
4565 .compatible = "lg,lh500wx1-sd03",
4566 .data = &lg_lh500wx1_sd03
4567 }, {
4568 .compatible = "panasonic,vvx10f004b00",
4569 .data = &panasonic_vvx10f004b00
4570 }, {
4571 .compatible = "lg,acx467akm-7",
4572 .data = &lg_acx467akm_7
4573 }, {
4574 .compatible = "osddisplays,osd101t2045-53ts",
4575 .data = &osd101t2045_53ts
4576 }, {
4577 /* sentinel */
4578 }
4579 };
4580 MODULE_DEVICE_TABLE(of, dsi_of_match);
4581
panel_simple_dsi_probe(struct mipi_dsi_device * dsi)4582 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4583 {
4584 const struct panel_desc_dsi *desc;
4585 const struct of_device_id *id;
4586 int err;
4587
4588 id = of_match_node(dsi_of_match, dsi->dev.of_node);
4589 if (!id)
4590 return -ENODEV;
4591
4592 desc = id->data;
4593
4594 err = panel_simple_probe(&dsi->dev, &desc->desc);
4595 if (err < 0)
4596 return err;
4597
4598 dsi->mode_flags = desc->flags;
4599 dsi->format = desc->format;
4600 dsi->lanes = desc->lanes;
4601
4602 err = mipi_dsi_attach(dsi);
4603 if (err) {
4604 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
4605
4606 drm_panel_remove(&panel->base);
4607 }
4608
4609 return err;
4610 }
4611
panel_simple_dsi_remove(struct mipi_dsi_device * dsi)4612 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4613 {
4614 int err;
4615
4616 err = mipi_dsi_detach(dsi);
4617 if (err < 0)
4618 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4619
4620 return panel_simple_remove(&dsi->dev);
4621 }
4622
panel_simple_dsi_shutdown(struct mipi_dsi_device * dsi)4623 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4624 {
4625 panel_simple_shutdown(&dsi->dev);
4626 }
4627
4628 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4629 .driver = {
4630 .name = "panel-simple-dsi",
4631 .of_match_table = dsi_of_match,
4632 },
4633 .probe = panel_simple_dsi_probe,
4634 .remove = panel_simple_dsi_remove,
4635 .shutdown = panel_simple_dsi_shutdown,
4636 };
4637
panel_simple_init(void)4638 static int __init panel_simple_init(void)
4639 {
4640 int err;
4641
4642 err = platform_driver_register(&panel_simple_platform_driver);
4643 if (err < 0)
4644 return err;
4645
4646 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4647 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4648 if (err < 0)
4649 return err;
4650 }
4651
4652 return 0;
4653 }
4654 module_init(panel_simple_init);
4655
panel_simple_exit(void)4656 static void __exit panel_simple_exit(void)
4657 {
4658 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4659 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4660
4661 platform_driver_unregister(&panel_simple_platform_driver);
4662 }
4663 module_exit(panel_simple_exit);
4664
4665 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4666 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4667 MODULE_LICENSE("GPL and additional rights");
4668