1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
9 #define dev_fmt(fmt) pr_fmt(fmt)
10
11 #include <linux/ratelimit.h>
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/amba/bus.h>
15 #include <linux/platform_device.h>
16 #include <linux/pci-ats.h>
17 #include <linux/bitmap.h>
18 #include <linux/slab.h>
19 #include <linux/debugfs.h>
20 #include <linux/scatterlist.h>
21 #include <linux/dma-map-ops.h>
22 #include <linux/dma-direct.h>
23 #include <linux/dma-iommu.h>
24 #include <linux/iommu-helper.h>
25 #include <linux/delay.h>
26 #include <linux/amd-iommu.h>
27 #include <linux/notifier.h>
28 #include <linux/export.h>
29 #include <linux/irq.h>
30 #include <linux/msi.h>
31 #include <linux/irqdomain.h>
32 #include <linux/percpu.h>
33 #include <linux/iova.h>
34 #include <asm/irq_remapping.h>
35 #include <asm/io_apic.h>
36 #include <asm/apic.h>
37 #include <asm/hw_irq.h>
38 #include <asm/msidef.h>
39 #include <asm/proto.h>
40 #include <asm/iommu.h>
41 #include <asm/gart.h>
42 #include <asm/dma.h>
43
44 #include "amd_iommu.h"
45 #include "../irq_remapping.h"
46
47 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
48
49 #define LOOP_TIMEOUT 100000
50
51 /* IO virtual address start page frame number */
52 #define IOVA_START_PFN (1)
53 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
54
55 /* Reserved IOVA ranges */
56 #define MSI_RANGE_START (0xfee00000)
57 #define MSI_RANGE_END (0xfeefffff)
58 #define HT_RANGE_START (0xfd00000000ULL)
59 #define HT_RANGE_END (0xffffffffffULL)
60
61 /*
62 * This bitmap is used to advertise the page sizes our hardware support
63 * to the IOMMU core, which will then use this information to split
64 * physically contiguous memory regions it is mapping into page sizes
65 * that we support.
66 *
67 * 512GB Pages are not supported due to a hardware bug
68 */
69 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
70
71 #define DEFAULT_PGTABLE_LEVEL PAGE_MODE_3_LEVEL
72
73 static DEFINE_SPINLOCK(pd_bitmap_lock);
74
75 /* List of all available dev_data structures */
76 static LLIST_HEAD(dev_data_list);
77
78 LIST_HEAD(ioapic_map);
79 LIST_HEAD(hpet_map);
80 LIST_HEAD(acpihid_map);
81
82 /*
83 * Domain for untranslated devices - only allocated
84 * if iommu=pt passed on kernel cmd line.
85 */
86 const struct iommu_ops amd_iommu_ops;
87
88 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
89 int amd_iommu_max_glx_val = -1;
90
91 /*
92 * general struct to manage commands send to an IOMMU
93 */
94 struct iommu_cmd {
95 u32 data[4];
96 };
97
98 struct kmem_cache *amd_iommu_irq_cache;
99
100 static void update_domain(struct protection_domain *domain);
101 static void detach_device(struct device *dev);
102 static void update_and_flush_device_table(struct protection_domain *domain,
103 struct domain_pgtable *pgtable);
104
105 /****************************************************************************
106 *
107 * Helper functions
108 *
109 ****************************************************************************/
110
get_pci_device_id(struct device * dev)111 static inline u16 get_pci_device_id(struct device *dev)
112 {
113 struct pci_dev *pdev = to_pci_dev(dev);
114
115 return pci_dev_id(pdev);
116 }
117
get_acpihid_device_id(struct device * dev,struct acpihid_map_entry ** entry)118 static inline int get_acpihid_device_id(struct device *dev,
119 struct acpihid_map_entry **entry)
120 {
121 struct acpi_device *adev = ACPI_COMPANION(dev);
122 struct acpihid_map_entry *p;
123
124 if (!adev)
125 return -ENODEV;
126
127 list_for_each_entry(p, &acpihid_map, list) {
128 if (acpi_dev_hid_uid_match(adev, p->hid,
129 p->uid[0] ? p->uid : NULL)) {
130 if (entry)
131 *entry = p;
132 return p->devid;
133 }
134 }
135 return -EINVAL;
136 }
137
get_device_id(struct device * dev)138 static inline int get_device_id(struct device *dev)
139 {
140 int devid;
141
142 if (dev_is_pci(dev))
143 devid = get_pci_device_id(dev);
144 else
145 devid = get_acpihid_device_id(dev, NULL);
146
147 return devid;
148 }
149
to_pdomain(struct iommu_domain * dom)150 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
151 {
152 return container_of(dom, struct protection_domain, domain);
153 }
154
amd_iommu_domain_get_pgtable(struct protection_domain * domain,struct domain_pgtable * pgtable)155 static void amd_iommu_domain_get_pgtable(struct protection_domain *domain,
156 struct domain_pgtable *pgtable)
157 {
158 u64 pt_root = atomic64_read(&domain->pt_root);
159
160 pgtable->root = (u64 *)(pt_root & PAGE_MASK);
161 pgtable->mode = pt_root & 7; /* lowest 3 bits encode pgtable mode */
162 }
163
amd_iommu_domain_set_pt_root(struct protection_domain * domain,u64 root)164 static void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root)
165 {
166 atomic64_set(&domain->pt_root, root);
167 }
168
amd_iommu_domain_clr_pt_root(struct protection_domain * domain)169 static void amd_iommu_domain_clr_pt_root(struct protection_domain *domain)
170 {
171 amd_iommu_domain_set_pt_root(domain, 0);
172 }
173
amd_iommu_domain_set_pgtable(struct protection_domain * domain,u64 * root,int mode)174 static void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
175 u64 *root, int mode)
176 {
177 u64 pt_root;
178
179 /* lowest 3 bits encode pgtable mode */
180 pt_root = mode & 7;
181 pt_root |= (u64)root;
182
183 amd_iommu_domain_set_pt_root(domain, pt_root);
184 }
185
alloc_dev_data(u16 devid)186 static struct iommu_dev_data *alloc_dev_data(u16 devid)
187 {
188 struct iommu_dev_data *dev_data;
189
190 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
191 if (!dev_data)
192 return NULL;
193
194 spin_lock_init(&dev_data->lock);
195 dev_data->devid = devid;
196 ratelimit_default_init(&dev_data->rs);
197
198 llist_add(&dev_data->dev_data_list, &dev_data_list);
199 return dev_data;
200 }
201
search_dev_data(u16 devid)202 static struct iommu_dev_data *search_dev_data(u16 devid)
203 {
204 struct iommu_dev_data *dev_data;
205 struct llist_node *node;
206
207 if (llist_empty(&dev_data_list))
208 return NULL;
209
210 node = dev_data_list.first;
211 llist_for_each_entry(dev_data, node, dev_data_list) {
212 if (dev_data->devid == devid)
213 return dev_data;
214 }
215
216 return NULL;
217 }
218
clone_alias(struct pci_dev * pdev,u16 alias,void * data)219 static int clone_alias(struct pci_dev *pdev, u16 alias, void *data)
220 {
221 u16 devid = pci_dev_id(pdev);
222
223 if (devid == alias)
224 return 0;
225
226 amd_iommu_rlookup_table[alias] =
227 amd_iommu_rlookup_table[devid];
228 memcpy(amd_iommu_dev_table[alias].data,
229 amd_iommu_dev_table[devid].data,
230 sizeof(amd_iommu_dev_table[alias].data));
231
232 return 0;
233 }
234
clone_aliases(struct pci_dev * pdev)235 static void clone_aliases(struct pci_dev *pdev)
236 {
237 if (!pdev)
238 return;
239
240 /*
241 * The IVRS alias stored in the alias table may not be
242 * part of the PCI DMA aliases if it's bus differs
243 * from the original device.
244 */
245 clone_alias(pdev, amd_iommu_alias_table[pci_dev_id(pdev)], NULL);
246
247 pci_for_each_dma_alias(pdev, clone_alias, NULL);
248 }
249
setup_aliases(struct device * dev)250 static struct pci_dev *setup_aliases(struct device *dev)
251 {
252 struct pci_dev *pdev = to_pci_dev(dev);
253 u16 ivrs_alias;
254
255 /* For ACPI HID devices, there are no aliases */
256 if (!dev_is_pci(dev))
257 return NULL;
258
259 /*
260 * Add the IVRS alias to the pci aliases if it is on the same
261 * bus. The IVRS table may know about a quirk that we don't.
262 */
263 ivrs_alias = amd_iommu_alias_table[pci_dev_id(pdev)];
264 if (ivrs_alias != pci_dev_id(pdev) &&
265 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number)
266 pci_add_dma_alias(pdev, ivrs_alias & 0xff, 1);
267
268 clone_aliases(pdev);
269
270 return pdev;
271 }
272
find_dev_data(u16 devid)273 static struct iommu_dev_data *find_dev_data(u16 devid)
274 {
275 struct iommu_dev_data *dev_data;
276 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
277
278 dev_data = search_dev_data(devid);
279
280 if (dev_data == NULL) {
281 dev_data = alloc_dev_data(devid);
282 if (!dev_data)
283 return NULL;
284
285 if (translation_pre_enabled(iommu))
286 dev_data->defer_attach = true;
287 }
288
289 return dev_data;
290 }
291
292 /*
293 * Find or create an IOMMU group for a acpihid device.
294 */
acpihid_device_group(struct device * dev)295 static struct iommu_group *acpihid_device_group(struct device *dev)
296 {
297 struct acpihid_map_entry *p, *entry = NULL;
298 int devid;
299
300 devid = get_acpihid_device_id(dev, &entry);
301 if (devid < 0)
302 return ERR_PTR(devid);
303
304 list_for_each_entry(p, &acpihid_map, list) {
305 if ((devid == p->devid) && p->group)
306 entry->group = p->group;
307 }
308
309 if (!entry->group)
310 entry->group = generic_device_group(dev);
311 else
312 iommu_group_ref_get(entry->group);
313
314 return entry->group;
315 }
316
pci_iommuv2_capable(struct pci_dev * pdev)317 static bool pci_iommuv2_capable(struct pci_dev *pdev)
318 {
319 static const int caps[] = {
320 PCI_EXT_CAP_ID_PRI,
321 PCI_EXT_CAP_ID_PASID,
322 };
323 int i, pos;
324
325 if (!pci_ats_supported(pdev))
326 return false;
327
328 for (i = 0; i < 2; ++i) {
329 pos = pci_find_ext_capability(pdev, caps[i]);
330 if (pos == 0)
331 return false;
332 }
333
334 return true;
335 }
336
pdev_pri_erratum(struct pci_dev * pdev,u32 erratum)337 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
338 {
339 struct iommu_dev_data *dev_data;
340
341 dev_data = dev_iommu_priv_get(&pdev->dev);
342
343 return dev_data->errata & (1 << erratum) ? true : false;
344 }
345
346 /*
347 * This function checks if the driver got a valid device from the caller to
348 * avoid dereferencing invalid pointers.
349 */
check_device(struct device * dev)350 static bool check_device(struct device *dev)
351 {
352 int devid;
353
354 if (!dev)
355 return false;
356
357 devid = get_device_id(dev);
358 if (devid < 0)
359 return false;
360
361 /* Out of our scope? */
362 if (devid > amd_iommu_last_bdf)
363 return false;
364
365 if (amd_iommu_rlookup_table[devid] == NULL)
366 return false;
367
368 return true;
369 }
370
iommu_init_device(struct device * dev)371 static int iommu_init_device(struct device *dev)
372 {
373 struct iommu_dev_data *dev_data;
374 int devid;
375
376 if (dev_iommu_priv_get(dev))
377 return 0;
378
379 devid = get_device_id(dev);
380 if (devid < 0)
381 return devid;
382
383 dev_data = find_dev_data(devid);
384 if (!dev_data)
385 return -ENOMEM;
386
387 dev_data->pdev = setup_aliases(dev);
388
389 /*
390 * By default we use passthrough mode for IOMMUv2 capable device.
391 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
392 * invalid address), we ignore the capability for the device so
393 * it'll be forced to go into translation mode.
394 */
395 if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
396 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
397 struct amd_iommu *iommu;
398
399 iommu = amd_iommu_rlookup_table[dev_data->devid];
400 dev_data->iommu_v2 = iommu->is_iommu_v2;
401 }
402
403 dev_iommu_priv_set(dev, dev_data);
404
405 return 0;
406 }
407
iommu_ignore_device(struct device * dev)408 static void iommu_ignore_device(struct device *dev)
409 {
410 int devid;
411
412 devid = get_device_id(dev);
413 if (devid < 0)
414 return;
415
416 amd_iommu_rlookup_table[devid] = NULL;
417 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
418
419 setup_aliases(dev);
420 }
421
amd_iommu_uninit_device(struct device * dev)422 static void amd_iommu_uninit_device(struct device *dev)
423 {
424 struct iommu_dev_data *dev_data;
425
426 dev_data = dev_iommu_priv_get(dev);
427 if (!dev_data)
428 return;
429
430 if (dev_data->domain)
431 detach_device(dev);
432
433 dev_iommu_priv_set(dev, NULL);
434
435 /*
436 * We keep dev_data around for unplugged devices and reuse it when the
437 * device is re-plugged - not doing so would introduce a ton of races.
438 */
439 }
440
441 /*
442 * Helper function to get the first pte of a large mapping
443 */
first_pte_l7(u64 * pte,unsigned long * page_size,unsigned long * count)444 static u64 *first_pte_l7(u64 *pte, unsigned long *page_size,
445 unsigned long *count)
446 {
447 unsigned long pte_mask, pg_size, cnt;
448 u64 *fpte;
449
450 pg_size = PTE_PAGE_SIZE(*pte);
451 cnt = PAGE_SIZE_PTE_COUNT(pg_size);
452 pte_mask = ~((cnt << 3) - 1);
453 fpte = (u64 *)(((unsigned long)pte) & pte_mask);
454
455 if (page_size)
456 *page_size = pg_size;
457
458 if (count)
459 *count = cnt;
460
461 return fpte;
462 }
463
464 /****************************************************************************
465 *
466 * Interrupt handling functions
467 *
468 ****************************************************************************/
469
dump_dte_entry(u16 devid)470 static void dump_dte_entry(u16 devid)
471 {
472 int i;
473
474 for (i = 0; i < 4; ++i)
475 pr_err("DTE[%d]: %016llx\n", i,
476 amd_iommu_dev_table[devid].data[i]);
477 }
478
dump_command(unsigned long phys_addr)479 static void dump_command(unsigned long phys_addr)
480 {
481 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
482 int i;
483
484 for (i = 0; i < 4; ++i)
485 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
486 }
487
amd_iommu_report_rmp_hw_error(volatile u32 * event)488 static void amd_iommu_report_rmp_hw_error(volatile u32 *event)
489 {
490 struct iommu_dev_data *dev_data = NULL;
491 int devid, vmg_tag, flags;
492 struct pci_dev *pdev;
493 u64 spa;
494
495 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
496 vmg_tag = (event[1]) & 0xFFFF;
497 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
498 spa = ((u64)event[3] << 32) | (event[2] & 0xFFFFFFF8);
499
500 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
501 devid & 0xff);
502 if (pdev)
503 dev_data = dev_iommu_priv_get(&pdev->dev);
504
505 if (dev_data && __ratelimit(&dev_data->rs)) {
506 pci_err(pdev, "Event logged [RMP_HW_ERROR vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n",
507 vmg_tag, spa, flags);
508 } else {
509 pr_err_ratelimited("Event logged [RMP_HW_ERROR device=%02x:%02x.%x, vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n",
510 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
511 vmg_tag, spa, flags);
512 }
513
514 if (pdev)
515 pci_dev_put(pdev);
516 }
517
amd_iommu_report_rmp_fault(volatile u32 * event)518 static void amd_iommu_report_rmp_fault(volatile u32 *event)
519 {
520 struct iommu_dev_data *dev_data = NULL;
521 int devid, flags_rmp, vmg_tag, flags;
522 struct pci_dev *pdev;
523 u64 gpa;
524
525 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
526 flags_rmp = (event[0] >> EVENT_FLAGS_SHIFT) & 0xFF;
527 vmg_tag = (event[1]) & 0xFFFF;
528 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
529 gpa = ((u64)event[3] << 32) | event[2];
530
531 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
532 devid & 0xff);
533 if (pdev)
534 dev_data = dev_iommu_priv_get(&pdev->dev);
535
536 if (dev_data && __ratelimit(&dev_data->rs)) {
537 pci_err(pdev, "Event logged [RMP_PAGE_FAULT vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n",
538 vmg_tag, gpa, flags_rmp, flags);
539 } else {
540 pr_err_ratelimited("Event logged [RMP_PAGE_FAULT device=%02x:%02x.%x, vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n",
541 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
542 vmg_tag, gpa, flags_rmp, flags);
543 }
544
545 if (pdev)
546 pci_dev_put(pdev);
547 }
548
amd_iommu_report_page_fault(u16 devid,u16 domain_id,u64 address,int flags)549 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
550 u64 address, int flags)
551 {
552 struct iommu_dev_data *dev_data = NULL;
553 struct pci_dev *pdev;
554
555 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
556 devid & 0xff);
557 if (pdev)
558 dev_data = dev_iommu_priv_get(&pdev->dev);
559
560 if (dev_data && __ratelimit(&dev_data->rs)) {
561 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
562 domain_id, address, flags);
563 } else if (printk_ratelimit()) {
564 pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
565 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
566 domain_id, address, flags);
567 }
568
569 if (pdev)
570 pci_dev_put(pdev);
571 }
572
iommu_print_event(struct amd_iommu * iommu,void * __evt)573 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
574 {
575 struct device *dev = iommu->iommu.dev;
576 int type, devid, flags, tag;
577 volatile u32 *event = __evt;
578 int count = 0;
579 u64 address;
580 u32 pasid;
581
582 retry:
583 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
584 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
585 pasid = (event[0] & EVENT_DOMID_MASK_HI) |
586 (event[1] & EVENT_DOMID_MASK_LO);
587 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
588 address = (u64)(((u64)event[3]) << 32) | event[2];
589
590 if (type == 0) {
591 /* Did we hit the erratum? */
592 if (++count == LOOP_TIMEOUT) {
593 pr_err("No event written to event log\n");
594 return;
595 }
596 udelay(1);
597 goto retry;
598 }
599
600 if (type == EVENT_TYPE_IO_FAULT) {
601 amd_iommu_report_page_fault(devid, pasid, address, flags);
602 return;
603 }
604
605 switch (type) {
606 case EVENT_TYPE_ILL_DEV:
607 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
608 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
609 pasid, address, flags);
610 dump_dte_entry(devid);
611 break;
612 case EVENT_TYPE_DEV_TAB_ERR:
613 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
614 "address=0x%llx flags=0x%04x]\n",
615 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
616 address, flags);
617 break;
618 case EVENT_TYPE_PAGE_TAB_ERR:
619 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n",
620 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
621 pasid, address, flags);
622 break;
623 case EVENT_TYPE_ILL_CMD:
624 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
625 dump_command(address);
626 break;
627 case EVENT_TYPE_CMD_HARD_ERR:
628 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
629 address, flags);
630 break;
631 case EVENT_TYPE_IOTLB_INV_TO:
632 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n",
633 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
634 address);
635 break;
636 case EVENT_TYPE_INV_DEV_REQ:
637 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
638 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
639 pasid, address, flags);
640 break;
641 case EVENT_TYPE_RMP_FAULT:
642 amd_iommu_report_rmp_fault(event);
643 break;
644 case EVENT_TYPE_RMP_HW_ERR:
645 amd_iommu_report_rmp_hw_error(event);
646 break;
647 case EVENT_TYPE_INV_PPR_REQ:
648 pasid = PPR_PASID(*((u64 *)__evt));
649 tag = event[1] & 0x03FF;
650 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
651 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
652 pasid, address, flags, tag);
653 break;
654 default:
655 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
656 event[0], event[1], event[2], event[3]);
657 }
658
659 memset(__evt, 0, 4 * sizeof(u32));
660 }
661
iommu_poll_events(struct amd_iommu * iommu)662 static void iommu_poll_events(struct amd_iommu *iommu)
663 {
664 u32 head, tail;
665
666 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
667 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
668
669 while (head != tail) {
670 iommu_print_event(iommu, iommu->evt_buf + head);
671 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
672 }
673
674 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
675 }
676
iommu_handle_ppr_entry(struct amd_iommu * iommu,u64 * raw)677 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
678 {
679 struct amd_iommu_fault fault;
680
681 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
682 pr_err_ratelimited("Unknown PPR request received\n");
683 return;
684 }
685
686 fault.address = raw[1];
687 fault.pasid = PPR_PASID(raw[0]);
688 fault.device_id = PPR_DEVID(raw[0]);
689 fault.tag = PPR_TAG(raw[0]);
690 fault.flags = PPR_FLAGS(raw[0]);
691
692 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
693 }
694
iommu_poll_ppr_log(struct amd_iommu * iommu)695 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
696 {
697 u32 head, tail;
698
699 if (iommu->ppr_log == NULL)
700 return;
701
702 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
703 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
704
705 while (head != tail) {
706 volatile u64 *raw;
707 u64 entry[2];
708 int i;
709
710 raw = (u64 *)(iommu->ppr_log + head);
711
712 /*
713 * Hardware bug: Interrupt may arrive before the entry is
714 * written to memory. If this happens we need to wait for the
715 * entry to arrive.
716 */
717 for (i = 0; i < LOOP_TIMEOUT; ++i) {
718 if (PPR_REQ_TYPE(raw[0]) != 0)
719 break;
720 udelay(1);
721 }
722
723 /* Avoid memcpy function-call overhead */
724 entry[0] = raw[0];
725 entry[1] = raw[1];
726
727 /*
728 * To detect the hardware bug we need to clear the entry
729 * back to zero.
730 */
731 raw[0] = raw[1] = 0UL;
732
733 /* Update head pointer of hardware ring-buffer */
734 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
735 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
736
737 /* Handle PPR entry */
738 iommu_handle_ppr_entry(iommu, entry);
739
740 /* Refresh ring-buffer information */
741 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
742 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
743 }
744 }
745
746 #ifdef CONFIG_IRQ_REMAP
747 static int (*iommu_ga_log_notifier)(u32);
748
amd_iommu_register_ga_log_notifier(int (* notifier)(u32))749 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
750 {
751 iommu_ga_log_notifier = notifier;
752
753 return 0;
754 }
755 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
756
iommu_poll_ga_log(struct amd_iommu * iommu)757 static void iommu_poll_ga_log(struct amd_iommu *iommu)
758 {
759 u32 head, tail, cnt = 0;
760
761 if (iommu->ga_log == NULL)
762 return;
763
764 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
765 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
766
767 while (head != tail) {
768 volatile u64 *raw;
769 u64 log_entry;
770
771 raw = (u64 *)(iommu->ga_log + head);
772 cnt++;
773
774 /* Avoid memcpy function-call overhead */
775 log_entry = *raw;
776
777 /* Update head pointer of hardware ring-buffer */
778 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
779 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
780
781 /* Handle GA entry */
782 switch (GA_REQ_TYPE(log_entry)) {
783 case GA_GUEST_NR:
784 if (!iommu_ga_log_notifier)
785 break;
786
787 pr_debug("%s: devid=%#x, ga_tag=%#x\n",
788 __func__, GA_DEVID(log_entry),
789 GA_TAG(log_entry));
790
791 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
792 pr_err("GA log notifier failed.\n");
793 break;
794 default:
795 break;
796 }
797 }
798 }
799
800 static void
amd_iommu_set_pci_msi_domain(struct device * dev,struct amd_iommu * iommu)801 amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu)
802 {
803 if (!irq_remapping_enabled || !dev_is_pci(dev) ||
804 pci_dev_has_special_msi_domain(to_pci_dev(dev)))
805 return;
806
807 dev_set_msi_domain(dev, iommu->msi_domain);
808 }
809
810 #else /* CONFIG_IRQ_REMAP */
811 static inline void
amd_iommu_set_pci_msi_domain(struct device * dev,struct amd_iommu * iommu)812 amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu) { }
813 #endif /* !CONFIG_IRQ_REMAP */
814
815 #define AMD_IOMMU_INT_MASK \
816 (MMIO_STATUS_EVT_INT_MASK | \
817 MMIO_STATUS_PPR_INT_MASK | \
818 MMIO_STATUS_GALOG_INT_MASK)
819
amd_iommu_int_thread(int irq,void * data)820 irqreturn_t amd_iommu_int_thread(int irq, void *data)
821 {
822 struct amd_iommu *iommu = (struct amd_iommu *) data;
823 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
824
825 while (status & AMD_IOMMU_INT_MASK) {
826 /* Enable EVT and PPR and GA interrupts again */
827 writel(AMD_IOMMU_INT_MASK,
828 iommu->mmio_base + MMIO_STATUS_OFFSET);
829
830 if (status & MMIO_STATUS_EVT_INT_MASK) {
831 pr_devel("Processing IOMMU Event Log\n");
832 iommu_poll_events(iommu);
833 }
834
835 if (status & MMIO_STATUS_PPR_INT_MASK) {
836 pr_devel("Processing IOMMU PPR Log\n");
837 iommu_poll_ppr_log(iommu);
838 }
839
840 #ifdef CONFIG_IRQ_REMAP
841 if (status & MMIO_STATUS_GALOG_INT_MASK) {
842 pr_devel("Processing IOMMU GA Log\n");
843 iommu_poll_ga_log(iommu);
844 }
845 #endif
846
847 /*
848 * Hardware bug: ERBT1312
849 * When re-enabling interrupt (by writing 1
850 * to clear the bit), the hardware might also try to set
851 * the interrupt bit in the event status register.
852 * In this scenario, the bit will be set, and disable
853 * subsequent interrupts.
854 *
855 * Workaround: The IOMMU driver should read back the
856 * status register and check if the interrupt bits are cleared.
857 * If not, driver will need to go through the interrupt handler
858 * again and re-clear the bits
859 */
860 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
861 }
862 return IRQ_HANDLED;
863 }
864
amd_iommu_int_handler(int irq,void * data)865 irqreturn_t amd_iommu_int_handler(int irq, void *data)
866 {
867 return IRQ_WAKE_THREAD;
868 }
869
870 /****************************************************************************
871 *
872 * IOMMU command queuing functions
873 *
874 ****************************************************************************/
875
wait_on_sem(struct amd_iommu * iommu,u64 data)876 static int wait_on_sem(struct amd_iommu *iommu, u64 data)
877 {
878 int i = 0;
879
880 while (*iommu->cmd_sem != data && i < LOOP_TIMEOUT) {
881 udelay(1);
882 i += 1;
883 }
884
885 if (i == LOOP_TIMEOUT) {
886 pr_alert("Completion-Wait loop timed out\n");
887 return -EIO;
888 }
889
890 return 0;
891 }
892
copy_cmd_to_buffer(struct amd_iommu * iommu,struct iommu_cmd * cmd)893 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
894 struct iommu_cmd *cmd)
895 {
896 u8 *target;
897 u32 tail;
898
899 /* Copy command to buffer */
900 tail = iommu->cmd_buf_tail;
901 target = iommu->cmd_buf + tail;
902 memcpy(target, cmd, sizeof(*cmd));
903
904 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
905 iommu->cmd_buf_tail = tail;
906
907 /* Tell the IOMMU about it */
908 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
909 }
910
build_completion_wait(struct iommu_cmd * cmd,struct amd_iommu * iommu,u64 data)911 static void build_completion_wait(struct iommu_cmd *cmd,
912 struct amd_iommu *iommu,
913 u64 data)
914 {
915 u64 paddr = iommu_virt_to_phys((void *)iommu->cmd_sem);
916
917 memset(cmd, 0, sizeof(*cmd));
918 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
919 cmd->data[1] = upper_32_bits(paddr);
920 cmd->data[2] = data;
921 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
922 }
923
build_inv_dte(struct iommu_cmd * cmd,u16 devid)924 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
925 {
926 memset(cmd, 0, sizeof(*cmd));
927 cmd->data[0] = devid;
928 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
929 }
930
build_inv_iommu_pages(struct iommu_cmd * cmd,u64 address,size_t size,u16 domid,int pde)931 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
932 size_t size, u16 domid, int pde)
933 {
934 u64 pages;
935 bool s;
936
937 pages = iommu_num_pages(address, size, PAGE_SIZE);
938 s = false;
939
940 if (pages > 1) {
941 /*
942 * If we have to flush more than one page, flush all
943 * TLB entries for this domain
944 */
945 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
946 s = true;
947 }
948
949 address &= PAGE_MASK;
950
951 memset(cmd, 0, sizeof(*cmd));
952 cmd->data[1] |= domid;
953 cmd->data[2] = lower_32_bits(address);
954 cmd->data[3] = upper_32_bits(address);
955 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
956 if (s) /* size bit - we flush more than one 4kb page */
957 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
958 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
959 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
960 }
961
build_inv_iotlb_pages(struct iommu_cmd * cmd,u16 devid,int qdep,u64 address,size_t size)962 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
963 u64 address, size_t size)
964 {
965 u64 pages;
966 bool s;
967
968 pages = iommu_num_pages(address, size, PAGE_SIZE);
969 s = false;
970
971 if (pages > 1) {
972 /*
973 * If we have to flush more than one page, flush all
974 * TLB entries for this domain
975 */
976 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
977 s = true;
978 }
979
980 address &= PAGE_MASK;
981
982 memset(cmd, 0, sizeof(*cmd));
983 cmd->data[0] = devid;
984 cmd->data[0] |= (qdep & 0xff) << 24;
985 cmd->data[1] = devid;
986 cmd->data[2] = lower_32_bits(address);
987 cmd->data[3] = upper_32_bits(address);
988 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
989 if (s)
990 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
991 }
992
build_inv_iommu_pasid(struct iommu_cmd * cmd,u16 domid,u32 pasid,u64 address,bool size)993 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, u32 pasid,
994 u64 address, bool size)
995 {
996 memset(cmd, 0, sizeof(*cmd));
997
998 address &= ~(0xfffULL);
999
1000 cmd->data[0] = pasid;
1001 cmd->data[1] = domid;
1002 cmd->data[2] = lower_32_bits(address);
1003 cmd->data[3] = upper_32_bits(address);
1004 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
1005 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
1006 if (size)
1007 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
1008 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
1009 }
1010
build_inv_iotlb_pasid(struct iommu_cmd * cmd,u16 devid,u32 pasid,int qdep,u64 address,bool size)1011 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, u32 pasid,
1012 int qdep, u64 address, bool size)
1013 {
1014 memset(cmd, 0, sizeof(*cmd));
1015
1016 address &= ~(0xfffULL);
1017
1018 cmd->data[0] = devid;
1019 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
1020 cmd->data[0] |= (qdep & 0xff) << 24;
1021 cmd->data[1] = devid;
1022 cmd->data[1] |= (pasid & 0xff) << 16;
1023 cmd->data[2] = lower_32_bits(address);
1024 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
1025 cmd->data[3] = upper_32_bits(address);
1026 if (size)
1027 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
1028 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
1029 }
1030
build_complete_ppr(struct iommu_cmd * cmd,u16 devid,u32 pasid,int status,int tag,bool gn)1031 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, u32 pasid,
1032 int status, int tag, bool gn)
1033 {
1034 memset(cmd, 0, sizeof(*cmd));
1035
1036 cmd->data[0] = devid;
1037 if (gn) {
1038 cmd->data[1] = pasid;
1039 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
1040 }
1041 cmd->data[3] = tag & 0x1ff;
1042 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1043
1044 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1045 }
1046
build_inv_all(struct iommu_cmd * cmd)1047 static void build_inv_all(struct iommu_cmd *cmd)
1048 {
1049 memset(cmd, 0, sizeof(*cmd));
1050 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1051 }
1052
build_inv_irt(struct iommu_cmd * cmd,u16 devid)1053 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1054 {
1055 memset(cmd, 0, sizeof(*cmd));
1056 cmd->data[0] = devid;
1057 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1058 }
1059
1060 /*
1061 * Writes the command to the IOMMUs command buffer and informs the
1062 * hardware about the new command.
1063 */
__iommu_queue_command_sync(struct amd_iommu * iommu,struct iommu_cmd * cmd,bool sync)1064 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1065 struct iommu_cmd *cmd,
1066 bool sync)
1067 {
1068 unsigned int count = 0;
1069 u32 left, next_tail;
1070
1071 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1072 again:
1073 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1074
1075 if (left <= 0x20) {
1076 /* Skip udelay() the first time around */
1077 if (count++) {
1078 if (count == LOOP_TIMEOUT) {
1079 pr_err("Command buffer timeout\n");
1080 return -EIO;
1081 }
1082
1083 udelay(1);
1084 }
1085
1086 /* Update head and recheck remaining space */
1087 iommu->cmd_buf_head = readl(iommu->mmio_base +
1088 MMIO_CMD_HEAD_OFFSET);
1089
1090 goto again;
1091 }
1092
1093 copy_cmd_to_buffer(iommu, cmd);
1094
1095 /* Do we need to make sure all commands are processed? */
1096 iommu->need_sync = sync;
1097
1098 return 0;
1099 }
1100
iommu_queue_command_sync(struct amd_iommu * iommu,struct iommu_cmd * cmd,bool sync)1101 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1102 struct iommu_cmd *cmd,
1103 bool sync)
1104 {
1105 unsigned long flags;
1106 int ret;
1107
1108 raw_spin_lock_irqsave(&iommu->lock, flags);
1109 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1110 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1111
1112 return ret;
1113 }
1114
iommu_queue_command(struct amd_iommu * iommu,struct iommu_cmd * cmd)1115 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1116 {
1117 return iommu_queue_command_sync(iommu, cmd, true);
1118 }
1119
1120 /*
1121 * This function queues a completion wait command into the command
1122 * buffer of an IOMMU
1123 */
iommu_completion_wait(struct amd_iommu * iommu)1124 static int iommu_completion_wait(struct amd_iommu *iommu)
1125 {
1126 struct iommu_cmd cmd;
1127 unsigned long flags;
1128 int ret;
1129 u64 data;
1130
1131 if (!iommu->need_sync)
1132 return 0;
1133
1134 raw_spin_lock_irqsave(&iommu->lock, flags);
1135
1136 data = ++iommu->cmd_sem_val;
1137 build_completion_wait(&cmd, iommu, data);
1138
1139 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1140 if (ret)
1141 goto out_unlock;
1142
1143 ret = wait_on_sem(iommu, data);
1144
1145 out_unlock:
1146 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1147
1148 return ret;
1149 }
1150
iommu_flush_dte(struct amd_iommu * iommu,u16 devid)1151 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1152 {
1153 struct iommu_cmd cmd;
1154
1155 build_inv_dte(&cmd, devid);
1156
1157 return iommu_queue_command(iommu, &cmd);
1158 }
1159
amd_iommu_flush_dte_all(struct amd_iommu * iommu)1160 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1161 {
1162 u32 devid;
1163
1164 for (devid = 0; devid <= 0xffff; ++devid)
1165 iommu_flush_dte(iommu, devid);
1166
1167 iommu_completion_wait(iommu);
1168 }
1169
1170 /*
1171 * This function uses heavy locking and may disable irqs for some time. But
1172 * this is no issue because it is only called during resume.
1173 */
amd_iommu_flush_tlb_all(struct amd_iommu * iommu)1174 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1175 {
1176 u32 dom_id;
1177
1178 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1179 struct iommu_cmd cmd;
1180 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1181 dom_id, 1);
1182 iommu_queue_command(iommu, &cmd);
1183 }
1184
1185 iommu_completion_wait(iommu);
1186 }
1187
amd_iommu_flush_tlb_domid(struct amd_iommu * iommu,u32 dom_id)1188 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)
1189 {
1190 struct iommu_cmd cmd;
1191
1192 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1193 dom_id, 1);
1194 iommu_queue_command(iommu, &cmd);
1195
1196 iommu_completion_wait(iommu);
1197 }
1198
amd_iommu_flush_all(struct amd_iommu * iommu)1199 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1200 {
1201 struct iommu_cmd cmd;
1202
1203 build_inv_all(&cmd);
1204
1205 iommu_queue_command(iommu, &cmd);
1206 iommu_completion_wait(iommu);
1207 }
1208
iommu_flush_irt(struct amd_iommu * iommu,u16 devid)1209 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1210 {
1211 struct iommu_cmd cmd;
1212
1213 build_inv_irt(&cmd, devid);
1214
1215 iommu_queue_command(iommu, &cmd);
1216 }
1217
amd_iommu_flush_irt_all(struct amd_iommu * iommu)1218 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1219 {
1220 u32 devid;
1221
1222 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1223 iommu_flush_irt(iommu, devid);
1224
1225 iommu_completion_wait(iommu);
1226 }
1227
iommu_flush_all_caches(struct amd_iommu * iommu)1228 void iommu_flush_all_caches(struct amd_iommu *iommu)
1229 {
1230 if (iommu_feature(iommu, FEATURE_IA)) {
1231 amd_iommu_flush_all(iommu);
1232 } else {
1233 amd_iommu_flush_dte_all(iommu);
1234 amd_iommu_flush_irt_all(iommu);
1235 amd_iommu_flush_tlb_all(iommu);
1236 }
1237 }
1238
1239 /*
1240 * Command send function for flushing on-device TLB
1241 */
device_flush_iotlb(struct iommu_dev_data * dev_data,u64 address,size_t size)1242 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1243 u64 address, size_t size)
1244 {
1245 struct amd_iommu *iommu;
1246 struct iommu_cmd cmd;
1247 int qdep;
1248
1249 qdep = dev_data->ats.qdep;
1250 iommu = amd_iommu_rlookup_table[dev_data->devid];
1251
1252 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1253
1254 return iommu_queue_command(iommu, &cmd);
1255 }
1256
device_flush_dte_alias(struct pci_dev * pdev,u16 alias,void * data)1257 static int device_flush_dte_alias(struct pci_dev *pdev, u16 alias, void *data)
1258 {
1259 struct amd_iommu *iommu = data;
1260
1261 return iommu_flush_dte(iommu, alias);
1262 }
1263
1264 /*
1265 * Command send function for invalidating a device table entry
1266 */
device_flush_dte(struct iommu_dev_data * dev_data)1267 static int device_flush_dte(struct iommu_dev_data *dev_data)
1268 {
1269 struct amd_iommu *iommu;
1270 u16 alias;
1271 int ret;
1272
1273 iommu = amd_iommu_rlookup_table[dev_data->devid];
1274
1275 if (dev_data->pdev)
1276 ret = pci_for_each_dma_alias(dev_data->pdev,
1277 device_flush_dte_alias, iommu);
1278 else
1279 ret = iommu_flush_dte(iommu, dev_data->devid);
1280 if (ret)
1281 return ret;
1282
1283 alias = amd_iommu_alias_table[dev_data->devid];
1284 if (alias != dev_data->devid) {
1285 ret = iommu_flush_dte(iommu, alias);
1286 if (ret)
1287 return ret;
1288 }
1289
1290 if (dev_data->ats.enabled)
1291 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1292
1293 return ret;
1294 }
1295
1296 /*
1297 * TLB invalidation function which is called from the mapping functions.
1298 * It invalidates a single PTE if the range to flush is within a single
1299 * page. Otherwise it flushes the whole TLB of the IOMMU.
1300 */
__domain_flush_pages(struct protection_domain * domain,u64 address,size_t size,int pde)1301 static void __domain_flush_pages(struct protection_domain *domain,
1302 u64 address, size_t size, int pde)
1303 {
1304 struct iommu_dev_data *dev_data;
1305 struct iommu_cmd cmd;
1306 int ret = 0, i;
1307
1308 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1309
1310 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1311 if (!domain->dev_iommu[i])
1312 continue;
1313
1314 /*
1315 * Devices of this domain are behind this IOMMU
1316 * We need a TLB flush
1317 */
1318 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1319 }
1320
1321 list_for_each_entry(dev_data, &domain->dev_list, list) {
1322
1323 if (!dev_data->ats.enabled)
1324 continue;
1325
1326 ret |= device_flush_iotlb(dev_data, address, size);
1327 }
1328
1329 WARN_ON(ret);
1330 }
1331
domain_flush_pages(struct protection_domain * domain,u64 address,size_t size)1332 static void domain_flush_pages(struct protection_domain *domain,
1333 u64 address, size_t size)
1334 {
1335 __domain_flush_pages(domain, address, size, 0);
1336 }
1337
1338 /* Flush the whole IO/TLB for a given protection domain - including PDE */
domain_flush_tlb_pde(struct protection_domain * domain)1339 static void domain_flush_tlb_pde(struct protection_domain *domain)
1340 {
1341 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1342 }
1343
domain_flush_complete(struct protection_domain * domain)1344 static void domain_flush_complete(struct protection_domain *domain)
1345 {
1346 int i;
1347
1348 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1349 if (domain && !domain->dev_iommu[i])
1350 continue;
1351
1352 /*
1353 * Devices of this domain are behind this IOMMU
1354 * We need to wait for completion of all commands.
1355 */
1356 iommu_completion_wait(amd_iommus[i]);
1357 }
1358 }
1359
1360 /* Flush the not present cache if it exists */
domain_flush_np_cache(struct protection_domain * domain,dma_addr_t iova,size_t size)1361 static void domain_flush_np_cache(struct protection_domain *domain,
1362 dma_addr_t iova, size_t size)
1363 {
1364 if (unlikely(amd_iommu_np_cache)) {
1365 unsigned long flags;
1366
1367 spin_lock_irqsave(&domain->lock, flags);
1368 domain_flush_pages(domain, iova, size);
1369 domain_flush_complete(domain);
1370 spin_unlock_irqrestore(&domain->lock, flags);
1371 }
1372 }
1373
1374
1375 /*
1376 * This function flushes the DTEs for all devices in domain
1377 */
domain_flush_devices(struct protection_domain * domain)1378 static void domain_flush_devices(struct protection_domain *domain)
1379 {
1380 struct iommu_dev_data *dev_data;
1381
1382 list_for_each_entry(dev_data, &domain->dev_list, list)
1383 device_flush_dte(dev_data);
1384 }
1385
1386 /****************************************************************************
1387 *
1388 * The functions below are used the create the page table mappings for
1389 * unity mapped regions.
1390 *
1391 ****************************************************************************/
1392
free_page_list(struct page * freelist)1393 static void free_page_list(struct page *freelist)
1394 {
1395 while (freelist != NULL) {
1396 unsigned long p = (unsigned long)page_address(freelist);
1397 freelist = freelist->freelist;
1398 free_page(p);
1399 }
1400 }
1401
free_pt_page(unsigned long pt,struct page * freelist)1402 static struct page *free_pt_page(unsigned long pt, struct page *freelist)
1403 {
1404 struct page *p = virt_to_page((void *)pt);
1405
1406 p->freelist = freelist;
1407
1408 return p;
1409 }
1410
1411 #define DEFINE_FREE_PT_FN(LVL, FN) \
1412 static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \
1413 { \
1414 unsigned long p; \
1415 u64 *pt; \
1416 int i; \
1417 \
1418 pt = (u64 *)__pt; \
1419 \
1420 for (i = 0; i < 512; ++i) { \
1421 /* PTE present? */ \
1422 if (!IOMMU_PTE_PRESENT(pt[i])) \
1423 continue; \
1424 \
1425 /* Large PTE? */ \
1426 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1427 PM_PTE_LEVEL(pt[i]) == 7) \
1428 continue; \
1429 \
1430 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1431 freelist = FN(p, freelist); \
1432 } \
1433 \
1434 return free_pt_page((unsigned long)pt, freelist); \
1435 }
1436
DEFINE_FREE_PT_FN(l2,free_pt_page)1437 DEFINE_FREE_PT_FN(l2, free_pt_page)
1438 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1439 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1440 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1441 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1442
1443 static struct page *free_sub_pt(unsigned long root, int mode,
1444 struct page *freelist)
1445 {
1446 switch (mode) {
1447 case PAGE_MODE_NONE:
1448 case PAGE_MODE_7_LEVEL:
1449 break;
1450 case PAGE_MODE_1_LEVEL:
1451 freelist = free_pt_page(root, freelist);
1452 break;
1453 case PAGE_MODE_2_LEVEL:
1454 freelist = free_pt_l2(root, freelist);
1455 break;
1456 case PAGE_MODE_3_LEVEL:
1457 freelist = free_pt_l3(root, freelist);
1458 break;
1459 case PAGE_MODE_4_LEVEL:
1460 freelist = free_pt_l4(root, freelist);
1461 break;
1462 case PAGE_MODE_5_LEVEL:
1463 freelist = free_pt_l5(root, freelist);
1464 break;
1465 case PAGE_MODE_6_LEVEL:
1466 freelist = free_pt_l6(root, freelist);
1467 break;
1468 default:
1469 BUG();
1470 }
1471
1472 return freelist;
1473 }
1474
free_pagetable(struct domain_pgtable * pgtable)1475 static void free_pagetable(struct domain_pgtable *pgtable)
1476 {
1477 struct page *freelist = NULL;
1478 unsigned long root;
1479
1480 if (pgtable->mode == PAGE_MODE_NONE)
1481 return;
1482
1483 BUG_ON(pgtable->mode < PAGE_MODE_NONE ||
1484 pgtable->mode > PAGE_MODE_6_LEVEL);
1485
1486 root = (unsigned long)pgtable->root;
1487 freelist = free_sub_pt(root, pgtable->mode, freelist);
1488
1489 free_page_list(freelist);
1490 }
1491
1492 /*
1493 * This function is used to add another level to an IO page table. Adding
1494 * another level increases the size of the address space by 9 bits to a size up
1495 * to 64 bits.
1496 */
increase_address_space(struct protection_domain * domain,unsigned long address,gfp_t gfp)1497 static bool increase_address_space(struct protection_domain *domain,
1498 unsigned long address,
1499 gfp_t gfp)
1500 {
1501 struct domain_pgtable pgtable;
1502 unsigned long flags;
1503 bool ret = true;
1504 u64 *pte;
1505
1506 pte = (void *)get_zeroed_page(gfp);
1507 if (!pte)
1508 return false;
1509
1510 spin_lock_irqsave(&domain->lock, flags);
1511
1512 amd_iommu_domain_get_pgtable(domain, &pgtable);
1513
1514 if (address <= PM_LEVEL_SIZE(pgtable.mode))
1515 goto out;
1516
1517 ret = false;
1518 if (WARN_ON_ONCE(pgtable.mode == PAGE_MODE_6_LEVEL))
1519 goto out;
1520
1521 *pte = PM_LEVEL_PDE(pgtable.mode, iommu_virt_to_phys(pgtable.root));
1522
1523 pgtable.root = pte;
1524 pgtable.mode += 1;
1525 update_and_flush_device_table(domain, &pgtable);
1526 domain_flush_complete(domain);
1527
1528 /*
1529 * Device Table needs to be updated and flushed before the new root can
1530 * be published.
1531 */
1532 amd_iommu_domain_set_pgtable(domain, pte, pgtable.mode);
1533
1534 pte = NULL;
1535 ret = true;
1536
1537 out:
1538 spin_unlock_irqrestore(&domain->lock, flags);
1539 free_page((unsigned long)pte);
1540
1541 return ret;
1542 }
1543
alloc_pte(struct protection_domain * domain,unsigned long address,unsigned long page_size,u64 ** pte_page,gfp_t gfp,bool * updated)1544 static u64 *alloc_pte(struct protection_domain *domain,
1545 unsigned long address,
1546 unsigned long page_size,
1547 u64 **pte_page,
1548 gfp_t gfp,
1549 bool *updated)
1550 {
1551 struct domain_pgtable pgtable;
1552 int level, end_lvl;
1553 u64 *pte, *page;
1554
1555 BUG_ON(!is_power_of_2(page_size));
1556
1557 amd_iommu_domain_get_pgtable(domain, &pgtable);
1558
1559 while (address > PM_LEVEL_SIZE(pgtable.mode)) {
1560 /*
1561 * Return an error if there is no memory to update the
1562 * page-table.
1563 */
1564 if (!increase_address_space(domain, address, gfp))
1565 return NULL;
1566
1567 /* Read new values to check if update was successful */
1568 amd_iommu_domain_get_pgtable(domain, &pgtable);
1569 }
1570
1571
1572 level = pgtable.mode - 1;
1573 pte = &pgtable.root[PM_LEVEL_INDEX(level, address)];
1574 address = PAGE_SIZE_ALIGN(address, page_size);
1575 end_lvl = PAGE_SIZE_LEVEL(page_size);
1576
1577 while (level > end_lvl) {
1578 u64 __pte, __npte;
1579 int pte_level;
1580
1581 __pte = *pte;
1582 pte_level = PM_PTE_LEVEL(__pte);
1583
1584 /*
1585 * If we replace a series of large PTEs, we need
1586 * to tear down all of them.
1587 */
1588 if (IOMMU_PTE_PRESENT(__pte) &&
1589 pte_level == PAGE_MODE_7_LEVEL) {
1590 unsigned long count, i;
1591 u64 *lpte;
1592
1593 lpte = first_pte_l7(pte, NULL, &count);
1594
1595 /*
1596 * Unmap the replicated PTEs that still match the
1597 * original large mapping
1598 */
1599 for (i = 0; i < count; ++i)
1600 cmpxchg64(&lpte[i], __pte, 0ULL);
1601
1602 *updated = true;
1603 continue;
1604 }
1605
1606 if (!IOMMU_PTE_PRESENT(__pte) ||
1607 pte_level == PAGE_MODE_NONE) {
1608 page = (u64 *)get_zeroed_page(gfp);
1609
1610 if (!page)
1611 return NULL;
1612
1613 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1614
1615 /* pte could have been changed somewhere. */
1616 if (cmpxchg64(pte, __pte, __npte) != __pte)
1617 free_page((unsigned long)page);
1618 else if (IOMMU_PTE_PRESENT(__pte))
1619 *updated = true;
1620
1621 continue;
1622 }
1623
1624 /* No level skipping support yet */
1625 if (pte_level != level)
1626 return NULL;
1627
1628 level -= 1;
1629
1630 pte = IOMMU_PTE_PAGE(__pte);
1631
1632 if (pte_page && level == end_lvl)
1633 *pte_page = pte;
1634
1635 pte = &pte[PM_LEVEL_INDEX(level, address)];
1636 }
1637
1638 return pte;
1639 }
1640
1641 /*
1642 * This function checks if there is a PTE for a given dma address. If
1643 * there is one, it returns the pointer to it.
1644 */
fetch_pte(struct protection_domain * domain,unsigned long address,unsigned long * page_size)1645 static u64 *fetch_pte(struct protection_domain *domain,
1646 unsigned long address,
1647 unsigned long *page_size)
1648 {
1649 struct domain_pgtable pgtable;
1650 int level;
1651 u64 *pte;
1652
1653 *page_size = 0;
1654
1655 amd_iommu_domain_get_pgtable(domain, &pgtable);
1656
1657 if (address > PM_LEVEL_SIZE(pgtable.mode))
1658 return NULL;
1659
1660 level = pgtable.mode - 1;
1661 pte = &pgtable.root[PM_LEVEL_INDEX(level, address)];
1662 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1663
1664 while (level > 0) {
1665
1666 /* Not Present */
1667 if (!IOMMU_PTE_PRESENT(*pte))
1668 return NULL;
1669
1670 /* Large PTE */
1671 if (PM_PTE_LEVEL(*pte) == 7 ||
1672 PM_PTE_LEVEL(*pte) == 0)
1673 break;
1674
1675 /* No level skipping support yet */
1676 if (PM_PTE_LEVEL(*pte) != level)
1677 return NULL;
1678
1679 level -= 1;
1680
1681 /* Walk to the next level */
1682 pte = IOMMU_PTE_PAGE(*pte);
1683 pte = &pte[PM_LEVEL_INDEX(level, address)];
1684 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1685 }
1686
1687 /*
1688 * If we have a series of large PTEs, make
1689 * sure to return a pointer to the first one.
1690 */
1691 if (PM_PTE_LEVEL(*pte) == PAGE_MODE_7_LEVEL)
1692 pte = first_pte_l7(pte, page_size, NULL);
1693
1694 return pte;
1695 }
1696
free_clear_pte(u64 * pte,u64 pteval,struct page * freelist)1697 static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist)
1698 {
1699 unsigned long pt;
1700 int mode;
1701
1702 while (cmpxchg64(pte, pteval, 0) != pteval) {
1703 pr_warn("AMD-Vi: IOMMU pte changed since we read it\n");
1704 pteval = *pte;
1705 }
1706
1707 if (!IOMMU_PTE_PRESENT(pteval))
1708 return freelist;
1709
1710 pt = (unsigned long)IOMMU_PTE_PAGE(pteval);
1711 mode = IOMMU_PTE_MODE(pteval);
1712
1713 return free_sub_pt(pt, mode, freelist);
1714 }
1715
1716 /*
1717 * Generic mapping functions. It maps a physical address into a DMA
1718 * address space. It allocates the page table pages if necessary.
1719 * In the future it can be extended to a generic mapping function
1720 * supporting all features of AMD IOMMU page tables like level skipping
1721 * and full 64 bit address spaces.
1722 */
iommu_map_page(struct protection_domain * dom,unsigned long bus_addr,unsigned long phys_addr,unsigned long page_size,int prot,gfp_t gfp)1723 static int iommu_map_page(struct protection_domain *dom,
1724 unsigned long bus_addr,
1725 unsigned long phys_addr,
1726 unsigned long page_size,
1727 int prot,
1728 gfp_t gfp)
1729 {
1730 struct page *freelist = NULL;
1731 bool updated = false;
1732 u64 __pte, *pte;
1733 int ret, i, count;
1734
1735 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1736 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1737
1738 ret = -EINVAL;
1739 if (!(prot & IOMMU_PROT_MASK))
1740 goto out;
1741
1742 count = PAGE_SIZE_PTE_COUNT(page_size);
1743 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp, &updated);
1744
1745 ret = -ENOMEM;
1746 if (!pte)
1747 goto out;
1748
1749 for (i = 0; i < count; ++i)
1750 freelist = free_clear_pte(&pte[i], pte[i], freelist);
1751
1752 if (freelist != NULL)
1753 updated = true;
1754
1755 if (count > 1) {
1756 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1757 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1758 } else
1759 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1760
1761 if (prot & IOMMU_PROT_IR)
1762 __pte |= IOMMU_PTE_IR;
1763 if (prot & IOMMU_PROT_IW)
1764 __pte |= IOMMU_PTE_IW;
1765
1766 for (i = 0; i < count; ++i)
1767 pte[i] = __pte;
1768
1769 ret = 0;
1770
1771 out:
1772 if (updated) {
1773 unsigned long flags;
1774
1775 spin_lock_irqsave(&dom->lock, flags);
1776 /*
1777 * Flush domain TLB(s) and wait for completion. Any Device-Table
1778 * Updates and flushing already happened in
1779 * increase_address_space().
1780 */
1781 domain_flush_tlb_pde(dom);
1782 domain_flush_complete(dom);
1783 spin_unlock_irqrestore(&dom->lock, flags);
1784 }
1785
1786 /* Everything flushed out, free pages now */
1787 free_page_list(freelist);
1788
1789 return ret;
1790 }
1791
iommu_unmap_page(struct protection_domain * dom,unsigned long bus_addr,unsigned long page_size)1792 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1793 unsigned long bus_addr,
1794 unsigned long page_size)
1795 {
1796 unsigned long long unmapped;
1797 unsigned long unmap_size;
1798 u64 *pte;
1799
1800 BUG_ON(!is_power_of_2(page_size));
1801
1802 unmapped = 0;
1803
1804 while (unmapped < page_size) {
1805
1806 pte = fetch_pte(dom, bus_addr, &unmap_size);
1807
1808 if (pte) {
1809 int i, count;
1810
1811 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1812 for (i = 0; i < count; i++)
1813 pte[i] = 0ULL;
1814 }
1815
1816 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1817 unmapped += unmap_size;
1818 }
1819
1820 BUG_ON(unmapped && !is_power_of_2(unmapped));
1821
1822 return unmapped;
1823 }
1824
1825 /****************************************************************************
1826 *
1827 * The next functions belong to the domain allocation. A domain is
1828 * allocated for every IOMMU as the default domain. If device isolation
1829 * is enabled, every device get its own domain. The most important thing
1830 * about domains is the page table mapping the DMA address space they
1831 * contain.
1832 *
1833 ****************************************************************************/
1834
domain_id_alloc(void)1835 static u16 domain_id_alloc(void)
1836 {
1837 int id;
1838
1839 spin_lock(&pd_bitmap_lock);
1840 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1841 BUG_ON(id == 0);
1842 if (id > 0 && id < MAX_DOMAIN_ID)
1843 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1844 else
1845 id = 0;
1846 spin_unlock(&pd_bitmap_lock);
1847
1848 return id;
1849 }
1850
domain_id_free(int id)1851 static void domain_id_free(int id)
1852 {
1853 spin_lock(&pd_bitmap_lock);
1854 if (id > 0 && id < MAX_DOMAIN_ID)
1855 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1856 spin_unlock(&pd_bitmap_lock);
1857 }
1858
free_gcr3_tbl_level1(u64 * tbl)1859 static void free_gcr3_tbl_level1(u64 *tbl)
1860 {
1861 u64 *ptr;
1862 int i;
1863
1864 for (i = 0; i < 512; ++i) {
1865 if (!(tbl[i] & GCR3_VALID))
1866 continue;
1867
1868 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1869
1870 free_page((unsigned long)ptr);
1871 }
1872 }
1873
free_gcr3_tbl_level2(u64 * tbl)1874 static void free_gcr3_tbl_level2(u64 *tbl)
1875 {
1876 u64 *ptr;
1877 int i;
1878
1879 for (i = 0; i < 512; ++i) {
1880 if (!(tbl[i] & GCR3_VALID))
1881 continue;
1882
1883 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1884
1885 free_gcr3_tbl_level1(ptr);
1886 }
1887 }
1888
free_gcr3_table(struct protection_domain * domain)1889 static void free_gcr3_table(struct protection_domain *domain)
1890 {
1891 if (domain->glx == 2)
1892 free_gcr3_tbl_level2(domain->gcr3_tbl);
1893 else if (domain->glx == 1)
1894 free_gcr3_tbl_level1(domain->gcr3_tbl);
1895 else
1896 BUG_ON(domain->glx != 0);
1897
1898 free_page((unsigned long)domain->gcr3_tbl);
1899 }
1900
set_dte_entry(u16 devid,struct protection_domain * domain,struct domain_pgtable * pgtable,bool ats,bool ppr)1901 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1902 struct domain_pgtable *pgtable,
1903 bool ats, bool ppr)
1904 {
1905 u64 pte_root = 0;
1906 u64 flags = 0;
1907 u32 old_domid;
1908
1909 if (pgtable->mode != PAGE_MODE_NONE)
1910 pte_root = iommu_virt_to_phys(pgtable->root);
1911
1912 pte_root |= (pgtable->mode & DEV_ENTRY_MODE_MASK)
1913 << DEV_ENTRY_MODE_SHIFT;
1914 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1915
1916 flags = amd_iommu_dev_table[devid].data[1];
1917
1918 if (ats)
1919 flags |= DTE_FLAG_IOTLB;
1920
1921 if (ppr) {
1922 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1923
1924 if (iommu_feature(iommu, FEATURE_EPHSUP))
1925 pte_root |= 1ULL << DEV_ENTRY_PPR;
1926 }
1927
1928 if (domain->flags & PD_IOMMUV2_MASK) {
1929 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1930 u64 glx = domain->glx;
1931 u64 tmp;
1932
1933 pte_root |= DTE_FLAG_GV;
1934 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1935
1936 /* First mask out possible old values for GCR3 table */
1937 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1938 flags &= ~tmp;
1939
1940 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1941 flags &= ~tmp;
1942
1943 /* Encode GCR3 table into DTE */
1944 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1945 pte_root |= tmp;
1946
1947 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1948 flags |= tmp;
1949
1950 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1951 flags |= tmp;
1952 }
1953
1954 flags &= ~DEV_DOMID_MASK;
1955 flags |= domain->id;
1956
1957 old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK;
1958 amd_iommu_dev_table[devid].data[1] = flags;
1959 amd_iommu_dev_table[devid].data[0] = pte_root;
1960
1961 /*
1962 * A kdump kernel might be replacing a domain ID that was copied from
1963 * the previous kernel--if so, it needs to flush the translation cache
1964 * entries for the old domain ID that is being overwritten
1965 */
1966 if (old_domid) {
1967 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1968
1969 amd_iommu_flush_tlb_domid(iommu, old_domid);
1970 }
1971 }
1972
clear_dte_entry(u16 devid)1973 static void clear_dte_entry(u16 devid)
1974 {
1975 /* remove entry from the device table seen by the hardware */
1976 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1977 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1978
1979 amd_iommu_apply_erratum_63(devid);
1980 }
1981
do_attach(struct iommu_dev_data * dev_data,struct protection_domain * domain)1982 static void do_attach(struct iommu_dev_data *dev_data,
1983 struct protection_domain *domain)
1984 {
1985 struct domain_pgtable pgtable;
1986 struct amd_iommu *iommu;
1987 bool ats;
1988
1989 iommu = amd_iommu_rlookup_table[dev_data->devid];
1990 ats = dev_data->ats.enabled;
1991
1992 /* Update data structures */
1993 dev_data->domain = domain;
1994 list_add(&dev_data->list, &domain->dev_list);
1995
1996 /* Do reference counting */
1997 domain->dev_iommu[iommu->index] += 1;
1998 domain->dev_cnt += 1;
1999
2000 /* Update device table */
2001 amd_iommu_domain_get_pgtable(domain, &pgtable);
2002 set_dte_entry(dev_data->devid, domain, &pgtable,
2003 ats, dev_data->iommu_v2);
2004 clone_aliases(dev_data->pdev);
2005
2006 device_flush_dte(dev_data);
2007 }
2008
do_detach(struct iommu_dev_data * dev_data)2009 static void do_detach(struct iommu_dev_data *dev_data)
2010 {
2011 struct protection_domain *domain = dev_data->domain;
2012 struct amd_iommu *iommu;
2013
2014 iommu = amd_iommu_rlookup_table[dev_data->devid];
2015
2016 /* Update data structures */
2017 dev_data->domain = NULL;
2018 list_del(&dev_data->list);
2019 clear_dte_entry(dev_data->devid);
2020 clone_aliases(dev_data->pdev);
2021
2022 /* Flush the DTE entry */
2023 device_flush_dte(dev_data);
2024
2025 /* Flush IOTLB */
2026 domain_flush_tlb_pde(domain);
2027
2028 /* Wait for the flushes to finish */
2029 domain_flush_complete(domain);
2030
2031 /* decrease reference counters - needs to happen after the flushes */
2032 domain->dev_iommu[iommu->index] -= 1;
2033 domain->dev_cnt -= 1;
2034 }
2035
pdev_iommuv2_disable(struct pci_dev * pdev)2036 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2037 {
2038 pci_disable_ats(pdev);
2039 pci_disable_pri(pdev);
2040 pci_disable_pasid(pdev);
2041 }
2042
2043 /* FIXME: Change generic reset-function to do the same */
pri_reset_while_enabled(struct pci_dev * pdev)2044 static int pri_reset_while_enabled(struct pci_dev *pdev)
2045 {
2046 u16 control;
2047 int pos;
2048
2049 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2050 if (!pos)
2051 return -EINVAL;
2052
2053 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2054 control |= PCI_PRI_CTRL_RESET;
2055 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2056
2057 return 0;
2058 }
2059
pdev_iommuv2_enable(struct pci_dev * pdev)2060 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2061 {
2062 bool reset_enable;
2063 int reqs, ret;
2064
2065 /* FIXME: Hardcode number of outstanding requests for now */
2066 reqs = 32;
2067 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2068 reqs = 1;
2069 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2070
2071 /* Only allow access to user-accessible pages */
2072 ret = pci_enable_pasid(pdev, 0);
2073 if (ret)
2074 goto out_err;
2075
2076 /* First reset the PRI state of the device */
2077 ret = pci_reset_pri(pdev);
2078 if (ret)
2079 goto out_err;
2080
2081 /* Enable PRI */
2082 ret = pci_enable_pri(pdev, reqs);
2083 if (ret)
2084 goto out_err;
2085
2086 if (reset_enable) {
2087 ret = pri_reset_while_enabled(pdev);
2088 if (ret)
2089 goto out_err;
2090 }
2091
2092 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2093 if (ret)
2094 goto out_err;
2095
2096 return 0;
2097
2098 out_err:
2099 pci_disable_pri(pdev);
2100 pci_disable_pasid(pdev);
2101
2102 return ret;
2103 }
2104
2105 /*
2106 * If a device is not yet associated with a domain, this function makes the
2107 * device visible in the domain
2108 */
attach_device(struct device * dev,struct protection_domain * domain)2109 static int attach_device(struct device *dev,
2110 struct protection_domain *domain)
2111 {
2112 struct iommu_dev_data *dev_data;
2113 struct pci_dev *pdev;
2114 unsigned long flags;
2115 int ret;
2116
2117 spin_lock_irqsave(&domain->lock, flags);
2118
2119 dev_data = dev_iommu_priv_get(dev);
2120
2121 spin_lock(&dev_data->lock);
2122
2123 ret = -EBUSY;
2124 if (dev_data->domain != NULL)
2125 goto out;
2126
2127 if (!dev_is_pci(dev))
2128 goto skip_ats_check;
2129
2130 pdev = to_pci_dev(dev);
2131 if (domain->flags & PD_IOMMUV2_MASK) {
2132 struct iommu_domain *def_domain = iommu_get_dma_domain(dev);
2133
2134 ret = -EINVAL;
2135 if (def_domain->type != IOMMU_DOMAIN_IDENTITY)
2136 goto out;
2137
2138 if (dev_data->iommu_v2) {
2139 if (pdev_iommuv2_enable(pdev) != 0)
2140 goto out;
2141
2142 dev_data->ats.enabled = true;
2143 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2144 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
2145 }
2146 } else if (amd_iommu_iotlb_sup &&
2147 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2148 dev_data->ats.enabled = true;
2149 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2150 }
2151
2152 skip_ats_check:
2153 ret = 0;
2154
2155 do_attach(dev_data, domain);
2156
2157 /*
2158 * We might boot into a crash-kernel here. The crashed kernel
2159 * left the caches in the IOMMU dirty. So we have to flush
2160 * here to evict all dirty stuff.
2161 */
2162 domain_flush_tlb_pde(domain);
2163
2164 domain_flush_complete(domain);
2165
2166 out:
2167 spin_unlock(&dev_data->lock);
2168
2169 spin_unlock_irqrestore(&domain->lock, flags);
2170
2171 return ret;
2172 }
2173
2174 /*
2175 * Removes a device from a protection domain (with devtable_lock held)
2176 */
detach_device(struct device * dev)2177 static void detach_device(struct device *dev)
2178 {
2179 struct protection_domain *domain;
2180 struct iommu_dev_data *dev_data;
2181 unsigned long flags;
2182
2183 dev_data = dev_iommu_priv_get(dev);
2184 domain = dev_data->domain;
2185
2186 spin_lock_irqsave(&domain->lock, flags);
2187
2188 spin_lock(&dev_data->lock);
2189
2190 /*
2191 * First check if the device is still attached. It might already
2192 * be detached from its domain because the generic
2193 * iommu_detach_group code detached it and we try again here in
2194 * our alias handling.
2195 */
2196 if (WARN_ON(!dev_data->domain))
2197 goto out;
2198
2199 do_detach(dev_data);
2200
2201 if (!dev_is_pci(dev))
2202 goto out;
2203
2204 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2205 pdev_iommuv2_disable(to_pci_dev(dev));
2206 else if (dev_data->ats.enabled)
2207 pci_disable_ats(to_pci_dev(dev));
2208
2209 dev_data->ats.enabled = false;
2210
2211 out:
2212 spin_unlock(&dev_data->lock);
2213
2214 spin_unlock_irqrestore(&domain->lock, flags);
2215 }
2216
amd_iommu_probe_device(struct device * dev)2217 static struct iommu_device *amd_iommu_probe_device(struct device *dev)
2218 {
2219 struct iommu_device *iommu_dev;
2220 struct amd_iommu *iommu;
2221 int ret, devid;
2222
2223 if (!check_device(dev))
2224 return ERR_PTR(-ENODEV);
2225
2226 devid = get_device_id(dev);
2227 if (devid < 0)
2228 return ERR_PTR(devid);
2229
2230 iommu = amd_iommu_rlookup_table[devid];
2231
2232 if (dev_iommu_priv_get(dev))
2233 return &iommu->iommu;
2234
2235 ret = iommu_init_device(dev);
2236 if (ret) {
2237 if (ret != -ENOTSUPP)
2238 dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
2239 iommu_dev = ERR_PTR(ret);
2240 iommu_ignore_device(dev);
2241 } else {
2242 amd_iommu_set_pci_msi_domain(dev, iommu);
2243 iommu_dev = &iommu->iommu;
2244 }
2245
2246 iommu_completion_wait(iommu);
2247
2248 return iommu_dev;
2249 }
2250
amd_iommu_probe_finalize(struct device * dev)2251 static void amd_iommu_probe_finalize(struct device *dev)
2252 {
2253 struct iommu_domain *domain;
2254
2255 /* Domains are initialized for this device - have a look what we ended up with */
2256 domain = iommu_get_domain_for_dev(dev);
2257 if (domain->type == IOMMU_DOMAIN_DMA)
2258 iommu_setup_dma_ops(dev, IOVA_START_PFN << PAGE_SHIFT, 0);
2259 }
2260
amd_iommu_release_device(struct device * dev)2261 static void amd_iommu_release_device(struct device *dev)
2262 {
2263 int devid = get_device_id(dev);
2264 struct amd_iommu *iommu;
2265
2266 if (!check_device(dev))
2267 return;
2268
2269 iommu = amd_iommu_rlookup_table[devid];
2270
2271 amd_iommu_uninit_device(dev);
2272 iommu_completion_wait(iommu);
2273 }
2274
amd_iommu_device_group(struct device * dev)2275 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2276 {
2277 if (dev_is_pci(dev))
2278 return pci_device_group(dev);
2279
2280 return acpihid_device_group(dev);
2281 }
2282
amd_iommu_domain_get_attr(struct iommu_domain * domain,enum iommu_attr attr,void * data)2283 static int amd_iommu_domain_get_attr(struct iommu_domain *domain,
2284 enum iommu_attr attr, void *data)
2285 {
2286 switch (domain->type) {
2287 case IOMMU_DOMAIN_UNMANAGED:
2288 return -ENODEV;
2289 case IOMMU_DOMAIN_DMA:
2290 switch (attr) {
2291 case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE:
2292 *(int *)data = !amd_iommu_unmap_flush;
2293 return 0;
2294 default:
2295 return -ENODEV;
2296 }
2297 break;
2298 default:
2299 return -EINVAL;
2300 }
2301 }
2302
2303 /*****************************************************************************
2304 *
2305 * The next functions belong to the dma_ops mapping/unmapping code.
2306 *
2307 *****************************************************************************/
2308
update_device_table(struct protection_domain * domain,struct domain_pgtable * pgtable)2309 static void update_device_table(struct protection_domain *domain,
2310 struct domain_pgtable *pgtable)
2311 {
2312 struct iommu_dev_data *dev_data;
2313
2314 list_for_each_entry(dev_data, &domain->dev_list, list) {
2315 set_dte_entry(dev_data->devid, domain, pgtable,
2316 dev_data->ats.enabled, dev_data->iommu_v2);
2317 clone_aliases(dev_data->pdev);
2318 }
2319 }
2320
update_and_flush_device_table(struct protection_domain * domain,struct domain_pgtable * pgtable)2321 static void update_and_flush_device_table(struct protection_domain *domain,
2322 struct domain_pgtable *pgtable)
2323 {
2324 update_device_table(domain, pgtable);
2325 domain_flush_devices(domain);
2326 }
2327
update_domain(struct protection_domain * domain)2328 static void update_domain(struct protection_domain *domain)
2329 {
2330 struct domain_pgtable pgtable;
2331
2332 /* Update device table */
2333 amd_iommu_domain_get_pgtable(domain, &pgtable);
2334 update_and_flush_device_table(domain, &pgtable);
2335
2336 /* Flush domain TLB(s) and wait for completion */
2337 domain_flush_tlb_pde(domain);
2338 domain_flush_complete(domain);
2339 }
2340
amd_iommu_init_api(void)2341 int __init amd_iommu_init_api(void)
2342 {
2343 int ret, err = 0;
2344
2345 ret = iova_cache_get();
2346 if (ret)
2347 return ret;
2348
2349 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2350 if (err)
2351 return err;
2352 #ifdef CONFIG_ARM_AMBA
2353 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2354 if (err)
2355 return err;
2356 #endif
2357 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2358 if (err)
2359 return err;
2360
2361 return 0;
2362 }
2363
amd_iommu_init_dma_ops(void)2364 int __init amd_iommu_init_dma_ops(void)
2365 {
2366 swiotlb = (iommu_default_passthrough() || sme_me_mask) ? 1 : 0;
2367
2368 if (amd_iommu_unmap_flush)
2369 pr_info("IO/TLB flush on unmap enabled\n");
2370 else
2371 pr_info("Lazy IO/TLB flushing enabled\n");
2372
2373 return 0;
2374
2375 }
2376
2377 /*****************************************************************************
2378 *
2379 * The following functions belong to the exported interface of AMD IOMMU
2380 *
2381 * This interface allows access to lower level functions of the IOMMU
2382 * like protection domain handling and assignement of devices to domains
2383 * which is not possible with the dma_ops interface.
2384 *
2385 *****************************************************************************/
2386
cleanup_domain(struct protection_domain * domain)2387 static void cleanup_domain(struct protection_domain *domain)
2388 {
2389 struct iommu_dev_data *entry;
2390 unsigned long flags;
2391
2392 spin_lock_irqsave(&domain->lock, flags);
2393
2394 while (!list_empty(&domain->dev_list)) {
2395 entry = list_first_entry(&domain->dev_list,
2396 struct iommu_dev_data, list);
2397 BUG_ON(!entry->domain);
2398 do_detach(entry);
2399 }
2400
2401 spin_unlock_irqrestore(&domain->lock, flags);
2402 }
2403
protection_domain_free(struct protection_domain * domain)2404 static void protection_domain_free(struct protection_domain *domain)
2405 {
2406 struct domain_pgtable pgtable;
2407
2408 if (!domain)
2409 return;
2410
2411 if (domain->id)
2412 domain_id_free(domain->id);
2413
2414 amd_iommu_domain_get_pgtable(domain, &pgtable);
2415 amd_iommu_domain_clr_pt_root(domain);
2416 free_pagetable(&pgtable);
2417
2418 kfree(domain);
2419 }
2420
protection_domain_init(struct protection_domain * domain,int mode)2421 static int protection_domain_init(struct protection_domain *domain, int mode)
2422 {
2423 u64 *pt_root = NULL;
2424
2425 BUG_ON(mode < PAGE_MODE_NONE || mode > PAGE_MODE_6_LEVEL);
2426
2427 spin_lock_init(&domain->lock);
2428 domain->id = domain_id_alloc();
2429 if (!domain->id)
2430 return -ENOMEM;
2431 INIT_LIST_HEAD(&domain->dev_list);
2432
2433 if (mode != PAGE_MODE_NONE) {
2434 pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2435 if (!pt_root)
2436 return -ENOMEM;
2437 }
2438
2439 amd_iommu_domain_set_pgtable(domain, pt_root, mode);
2440
2441 return 0;
2442 }
2443
protection_domain_alloc(int mode)2444 static struct protection_domain *protection_domain_alloc(int mode)
2445 {
2446 struct protection_domain *domain;
2447
2448 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2449 if (!domain)
2450 return NULL;
2451
2452 if (protection_domain_init(domain, mode))
2453 goto out_err;
2454
2455 return domain;
2456
2457 out_err:
2458 kfree(domain);
2459
2460 return NULL;
2461 }
2462
amd_iommu_domain_alloc(unsigned type)2463 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2464 {
2465 struct protection_domain *domain;
2466 int mode = DEFAULT_PGTABLE_LEVEL;
2467
2468 if (type == IOMMU_DOMAIN_IDENTITY)
2469 mode = PAGE_MODE_NONE;
2470
2471 domain = protection_domain_alloc(mode);
2472 if (!domain)
2473 return NULL;
2474
2475 domain->domain.geometry.aperture_start = 0;
2476 domain->domain.geometry.aperture_end = ~0ULL;
2477 domain->domain.geometry.force_aperture = true;
2478
2479 if (type == IOMMU_DOMAIN_DMA &&
2480 iommu_get_dma_cookie(&domain->domain) == -ENOMEM)
2481 goto free_domain;
2482
2483 return &domain->domain;
2484
2485 free_domain:
2486 protection_domain_free(domain);
2487
2488 return NULL;
2489 }
2490
amd_iommu_domain_free(struct iommu_domain * dom)2491 static void amd_iommu_domain_free(struct iommu_domain *dom)
2492 {
2493 struct protection_domain *domain;
2494
2495 domain = to_pdomain(dom);
2496
2497 if (domain->dev_cnt > 0)
2498 cleanup_domain(domain);
2499
2500 BUG_ON(domain->dev_cnt != 0);
2501
2502 if (!dom)
2503 return;
2504
2505 if (dom->type == IOMMU_DOMAIN_DMA)
2506 iommu_put_dma_cookie(&domain->domain);
2507
2508 if (domain->flags & PD_IOMMUV2_MASK)
2509 free_gcr3_table(domain);
2510
2511 protection_domain_free(domain);
2512 }
2513
amd_iommu_detach_device(struct iommu_domain * dom,struct device * dev)2514 static void amd_iommu_detach_device(struct iommu_domain *dom,
2515 struct device *dev)
2516 {
2517 struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
2518 struct amd_iommu *iommu;
2519 int devid;
2520
2521 if (!check_device(dev))
2522 return;
2523
2524 devid = get_device_id(dev);
2525 if (devid < 0)
2526 return;
2527
2528 if (dev_data->domain != NULL)
2529 detach_device(dev);
2530
2531 iommu = amd_iommu_rlookup_table[devid];
2532 if (!iommu)
2533 return;
2534
2535 #ifdef CONFIG_IRQ_REMAP
2536 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2537 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2538 dev_data->use_vapic = 0;
2539 #endif
2540
2541 iommu_completion_wait(iommu);
2542 }
2543
amd_iommu_attach_device(struct iommu_domain * dom,struct device * dev)2544 static int amd_iommu_attach_device(struct iommu_domain *dom,
2545 struct device *dev)
2546 {
2547 struct protection_domain *domain = to_pdomain(dom);
2548 struct iommu_dev_data *dev_data;
2549 struct amd_iommu *iommu;
2550 int ret;
2551
2552 if (!check_device(dev))
2553 return -EINVAL;
2554
2555 dev_data = dev_iommu_priv_get(dev);
2556 dev_data->defer_attach = false;
2557
2558 iommu = amd_iommu_rlookup_table[dev_data->devid];
2559 if (!iommu)
2560 return -EINVAL;
2561
2562 if (dev_data->domain)
2563 detach_device(dev);
2564
2565 ret = attach_device(dev, domain);
2566
2567 #ifdef CONFIG_IRQ_REMAP
2568 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
2569 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
2570 dev_data->use_vapic = 1;
2571 else
2572 dev_data->use_vapic = 0;
2573 }
2574 #endif
2575
2576 iommu_completion_wait(iommu);
2577
2578 return ret;
2579 }
2580
amd_iommu_map(struct iommu_domain * dom,unsigned long iova,phys_addr_t paddr,size_t page_size,int iommu_prot,gfp_t gfp)2581 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2582 phys_addr_t paddr, size_t page_size, int iommu_prot,
2583 gfp_t gfp)
2584 {
2585 struct protection_domain *domain = to_pdomain(dom);
2586 struct domain_pgtable pgtable;
2587 int prot = 0;
2588 int ret;
2589
2590 amd_iommu_domain_get_pgtable(domain, &pgtable);
2591 if (pgtable.mode == PAGE_MODE_NONE)
2592 return -EINVAL;
2593
2594 if (iommu_prot & IOMMU_READ)
2595 prot |= IOMMU_PROT_IR;
2596 if (iommu_prot & IOMMU_WRITE)
2597 prot |= IOMMU_PROT_IW;
2598
2599 ret = iommu_map_page(domain, iova, paddr, page_size, prot, gfp);
2600
2601 domain_flush_np_cache(domain, iova, page_size);
2602
2603 return ret;
2604 }
2605
amd_iommu_unmap(struct iommu_domain * dom,unsigned long iova,size_t page_size,struct iommu_iotlb_gather * gather)2606 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2607 size_t page_size,
2608 struct iommu_iotlb_gather *gather)
2609 {
2610 struct protection_domain *domain = to_pdomain(dom);
2611 struct domain_pgtable pgtable;
2612
2613 amd_iommu_domain_get_pgtable(domain, &pgtable);
2614 if (pgtable.mode == PAGE_MODE_NONE)
2615 return 0;
2616
2617 return iommu_unmap_page(domain, iova, page_size);
2618 }
2619
amd_iommu_iova_to_phys(struct iommu_domain * dom,dma_addr_t iova)2620 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2621 dma_addr_t iova)
2622 {
2623 struct protection_domain *domain = to_pdomain(dom);
2624 unsigned long offset_mask, pte_pgsize;
2625 struct domain_pgtable pgtable;
2626 u64 *pte, __pte;
2627
2628 amd_iommu_domain_get_pgtable(domain, &pgtable);
2629 if (pgtable.mode == PAGE_MODE_NONE)
2630 return iova;
2631
2632 pte = fetch_pte(domain, iova, &pte_pgsize);
2633
2634 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2635 return 0;
2636
2637 offset_mask = pte_pgsize - 1;
2638 __pte = __sme_clr(*pte & PM_ADDR_MASK);
2639
2640 return (__pte & ~offset_mask) | (iova & offset_mask);
2641 }
2642
amd_iommu_capable(enum iommu_cap cap)2643 static bool amd_iommu_capable(enum iommu_cap cap)
2644 {
2645 switch (cap) {
2646 case IOMMU_CAP_CACHE_COHERENCY:
2647 return true;
2648 case IOMMU_CAP_INTR_REMAP:
2649 return (irq_remapping_enabled == 1);
2650 case IOMMU_CAP_NOEXEC:
2651 return false;
2652 default:
2653 break;
2654 }
2655
2656 return false;
2657 }
2658
amd_iommu_get_resv_regions(struct device * dev,struct list_head * head)2659 static void amd_iommu_get_resv_regions(struct device *dev,
2660 struct list_head *head)
2661 {
2662 struct iommu_resv_region *region;
2663 struct unity_map_entry *entry;
2664 int devid;
2665
2666 devid = get_device_id(dev);
2667 if (devid < 0)
2668 return;
2669
2670 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
2671 int type, prot = 0;
2672 size_t length;
2673
2674 if (devid < entry->devid_start || devid > entry->devid_end)
2675 continue;
2676
2677 type = IOMMU_RESV_DIRECT;
2678 length = entry->address_end - entry->address_start;
2679 if (entry->prot & IOMMU_PROT_IR)
2680 prot |= IOMMU_READ;
2681 if (entry->prot & IOMMU_PROT_IW)
2682 prot |= IOMMU_WRITE;
2683 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
2684 /* Exclusion range */
2685 type = IOMMU_RESV_RESERVED;
2686
2687 region = iommu_alloc_resv_region(entry->address_start,
2688 length, prot, type);
2689 if (!region) {
2690 dev_err(dev, "Out of memory allocating dm-regions\n");
2691 return;
2692 }
2693 list_add_tail(®ion->list, head);
2694 }
2695
2696 region = iommu_alloc_resv_region(MSI_RANGE_START,
2697 MSI_RANGE_END - MSI_RANGE_START + 1,
2698 0, IOMMU_RESV_MSI);
2699 if (!region)
2700 return;
2701 list_add_tail(®ion->list, head);
2702
2703 region = iommu_alloc_resv_region(HT_RANGE_START,
2704 HT_RANGE_END - HT_RANGE_START + 1,
2705 0, IOMMU_RESV_RESERVED);
2706 if (!region)
2707 return;
2708 list_add_tail(®ion->list, head);
2709 }
2710
amd_iommu_is_attach_deferred(struct iommu_domain * domain,struct device * dev)2711 bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
2712 struct device *dev)
2713 {
2714 struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
2715
2716 return dev_data->defer_attach;
2717 }
2718 EXPORT_SYMBOL_GPL(amd_iommu_is_attach_deferred);
2719
amd_iommu_flush_iotlb_all(struct iommu_domain * domain)2720 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
2721 {
2722 struct protection_domain *dom = to_pdomain(domain);
2723 unsigned long flags;
2724
2725 spin_lock_irqsave(&dom->lock, flags);
2726 domain_flush_tlb_pde(dom);
2727 domain_flush_complete(dom);
2728 spin_unlock_irqrestore(&dom->lock, flags);
2729 }
2730
amd_iommu_iotlb_sync(struct iommu_domain * domain,struct iommu_iotlb_gather * gather)2731 static void amd_iommu_iotlb_sync(struct iommu_domain *domain,
2732 struct iommu_iotlb_gather *gather)
2733 {
2734 amd_iommu_flush_iotlb_all(domain);
2735 }
2736
amd_iommu_def_domain_type(struct device * dev)2737 static int amd_iommu_def_domain_type(struct device *dev)
2738 {
2739 struct iommu_dev_data *dev_data;
2740
2741 dev_data = dev_iommu_priv_get(dev);
2742 if (!dev_data)
2743 return 0;
2744
2745 /*
2746 * Do not identity map IOMMUv2 capable devices when memory encryption is
2747 * active, because some of those devices (AMD GPUs) don't have the
2748 * encryption bit in their DMA-mask and require remapping.
2749 */
2750 if (!mem_encrypt_active() && dev_data->iommu_v2)
2751 return IOMMU_DOMAIN_IDENTITY;
2752
2753 return 0;
2754 }
2755
2756 const struct iommu_ops amd_iommu_ops = {
2757 .capable = amd_iommu_capable,
2758 .domain_alloc = amd_iommu_domain_alloc,
2759 .domain_free = amd_iommu_domain_free,
2760 .attach_dev = amd_iommu_attach_device,
2761 .detach_dev = amd_iommu_detach_device,
2762 .map = amd_iommu_map,
2763 .unmap = amd_iommu_unmap,
2764 .iova_to_phys = amd_iommu_iova_to_phys,
2765 .probe_device = amd_iommu_probe_device,
2766 .release_device = amd_iommu_release_device,
2767 .probe_finalize = amd_iommu_probe_finalize,
2768 .device_group = amd_iommu_device_group,
2769 .domain_get_attr = amd_iommu_domain_get_attr,
2770 .get_resv_regions = amd_iommu_get_resv_regions,
2771 .put_resv_regions = generic_iommu_put_resv_regions,
2772 .is_attach_deferred = amd_iommu_is_attach_deferred,
2773 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
2774 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
2775 .iotlb_sync = amd_iommu_iotlb_sync,
2776 .def_domain_type = amd_iommu_def_domain_type,
2777 };
2778
2779 /*****************************************************************************
2780 *
2781 * The next functions do a basic initialization of IOMMU for pass through
2782 * mode
2783 *
2784 * In passthrough mode the IOMMU is initialized and enabled but not used for
2785 * DMA-API translation.
2786 *
2787 *****************************************************************************/
2788
2789 /* IOMMUv2 specific functions */
amd_iommu_register_ppr_notifier(struct notifier_block * nb)2790 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
2791 {
2792 return atomic_notifier_chain_register(&ppr_notifier, nb);
2793 }
2794 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
2795
amd_iommu_unregister_ppr_notifier(struct notifier_block * nb)2796 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
2797 {
2798 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
2799 }
2800 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
2801
amd_iommu_domain_direct_map(struct iommu_domain * dom)2802 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
2803 {
2804 struct protection_domain *domain = to_pdomain(dom);
2805 struct domain_pgtable pgtable;
2806 unsigned long flags;
2807
2808 spin_lock_irqsave(&domain->lock, flags);
2809
2810 /* First save pgtable configuration*/
2811 amd_iommu_domain_get_pgtable(domain, &pgtable);
2812
2813 /* Remove page-table from domain */
2814 amd_iommu_domain_clr_pt_root(domain);
2815
2816 /* Make changes visible to IOMMUs */
2817 update_domain(domain);
2818
2819 /* Page-table is not visible to IOMMU anymore, so free it */
2820 free_pagetable(&pgtable);
2821
2822 spin_unlock_irqrestore(&domain->lock, flags);
2823 }
2824 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
2825
amd_iommu_domain_enable_v2(struct iommu_domain * dom,int pasids)2826 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
2827 {
2828 struct protection_domain *domain = to_pdomain(dom);
2829 unsigned long flags;
2830 int levels, ret;
2831
2832 if (pasids <= 0 || pasids > (PASID_MASK + 1))
2833 return -EINVAL;
2834
2835 /* Number of GCR3 table levels required */
2836 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
2837 levels += 1;
2838
2839 if (levels > amd_iommu_max_glx_val)
2840 return -EINVAL;
2841
2842 spin_lock_irqsave(&domain->lock, flags);
2843
2844 /*
2845 * Save us all sanity checks whether devices already in the
2846 * domain support IOMMUv2. Just force that the domain has no
2847 * devices attached when it is switched into IOMMUv2 mode.
2848 */
2849 ret = -EBUSY;
2850 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
2851 goto out;
2852
2853 ret = -ENOMEM;
2854 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
2855 if (domain->gcr3_tbl == NULL)
2856 goto out;
2857
2858 domain->glx = levels;
2859 domain->flags |= PD_IOMMUV2_MASK;
2860
2861 update_domain(domain);
2862
2863 ret = 0;
2864
2865 out:
2866 spin_unlock_irqrestore(&domain->lock, flags);
2867
2868 return ret;
2869 }
2870 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
2871
__flush_pasid(struct protection_domain * domain,u32 pasid,u64 address,bool size)2872 static int __flush_pasid(struct protection_domain *domain, u32 pasid,
2873 u64 address, bool size)
2874 {
2875 struct iommu_dev_data *dev_data;
2876 struct iommu_cmd cmd;
2877 int i, ret;
2878
2879 if (!(domain->flags & PD_IOMMUV2_MASK))
2880 return -EINVAL;
2881
2882 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
2883
2884 /*
2885 * IOMMU TLB needs to be flushed before Device TLB to
2886 * prevent device TLB refill from IOMMU TLB
2887 */
2888 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
2889 if (domain->dev_iommu[i] == 0)
2890 continue;
2891
2892 ret = iommu_queue_command(amd_iommus[i], &cmd);
2893 if (ret != 0)
2894 goto out;
2895 }
2896
2897 /* Wait until IOMMU TLB flushes are complete */
2898 domain_flush_complete(domain);
2899
2900 /* Now flush device TLBs */
2901 list_for_each_entry(dev_data, &domain->dev_list, list) {
2902 struct amd_iommu *iommu;
2903 int qdep;
2904
2905 /*
2906 There might be non-IOMMUv2 capable devices in an IOMMUv2
2907 * domain.
2908 */
2909 if (!dev_data->ats.enabled)
2910 continue;
2911
2912 qdep = dev_data->ats.qdep;
2913 iommu = amd_iommu_rlookup_table[dev_data->devid];
2914
2915 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
2916 qdep, address, size);
2917
2918 ret = iommu_queue_command(iommu, &cmd);
2919 if (ret != 0)
2920 goto out;
2921 }
2922
2923 /* Wait until all device TLBs are flushed */
2924 domain_flush_complete(domain);
2925
2926 ret = 0;
2927
2928 out:
2929
2930 return ret;
2931 }
2932
__amd_iommu_flush_page(struct protection_domain * domain,u32 pasid,u64 address)2933 static int __amd_iommu_flush_page(struct protection_domain *domain, u32 pasid,
2934 u64 address)
2935 {
2936 return __flush_pasid(domain, pasid, address, false);
2937 }
2938
amd_iommu_flush_page(struct iommu_domain * dom,u32 pasid,u64 address)2939 int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
2940 u64 address)
2941 {
2942 struct protection_domain *domain = to_pdomain(dom);
2943 unsigned long flags;
2944 int ret;
2945
2946 spin_lock_irqsave(&domain->lock, flags);
2947 ret = __amd_iommu_flush_page(domain, pasid, address);
2948 spin_unlock_irqrestore(&domain->lock, flags);
2949
2950 return ret;
2951 }
2952 EXPORT_SYMBOL(amd_iommu_flush_page);
2953
__amd_iommu_flush_tlb(struct protection_domain * domain,u32 pasid)2954 static int __amd_iommu_flush_tlb(struct protection_domain *domain, u32 pasid)
2955 {
2956 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
2957 true);
2958 }
2959
amd_iommu_flush_tlb(struct iommu_domain * dom,u32 pasid)2960 int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid)
2961 {
2962 struct protection_domain *domain = to_pdomain(dom);
2963 unsigned long flags;
2964 int ret;
2965
2966 spin_lock_irqsave(&domain->lock, flags);
2967 ret = __amd_iommu_flush_tlb(domain, pasid);
2968 spin_unlock_irqrestore(&domain->lock, flags);
2969
2970 return ret;
2971 }
2972 EXPORT_SYMBOL(amd_iommu_flush_tlb);
2973
__get_gcr3_pte(u64 * root,int level,u32 pasid,bool alloc)2974 static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc)
2975 {
2976 int index;
2977 u64 *pte;
2978
2979 while (true) {
2980
2981 index = (pasid >> (9 * level)) & 0x1ff;
2982 pte = &root[index];
2983
2984 if (level == 0)
2985 break;
2986
2987 if (!(*pte & GCR3_VALID)) {
2988 if (!alloc)
2989 return NULL;
2990
2991 root = (void *)get_zeroed_page(GFP_ATOMIC);
2992 if (root == NULL)
2993 return NULL;
2994
2995 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
2996 }
2997
2998 root = iommu_phys_to_virt(*pte & PAGE_MASK);
2999
3000 level -= 1;
3001 }
3002
3003 return pte;
3004 }
3005
__set_gcr3(struct protection_domain * domain,u32 pasid,unsigned long cr3)3006 static int __set_gcr3(struct protection_domain *domain, u32 pasid,
3007 unsigned long cr3)
3008 {
3009 struct domain_pgtable pgtable;
3010 u64 *pte;
3011
3012 amd_iommu_domain_get_pgtable(domain, &pgtable);
3013 if (pgtable.mode != PAGE_MODE_NONE)
3014 return -EINVAL;
3015
3016 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3017 if (pte == NULL)
3018 return -ENOMEM;
3019
3020 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3021
3022 return __amd_iommu_flush_tlb(domain, pasid);
3023 }
3024
__clear_gcr3(struct protection_domain * domain,u32 pasid)3025 static int __clear_gcr3(struct protection_domain *domain, u32 pasid)
3026 {
3027 struct domain_pgtable pgtable;
3028 u64 *pte;
3029
3030 amd_iommu_domain_get_pgtable(domain, &pgtable);
3031 if (pgtable.mode != PAGE_MODE_NONE)
3032 return -EINVAL;
3033
3034 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3035 if (pte == NULL)
3036 return 0;
3037
3038 *pte = 0;
3039
3040 return __amd_iommu_flush_tlb(domain, pasid);
3041 }
3042
amd_iommu_domain_set_gcr3(struct iommu_domain * dom,u32 pasid,unsigned long cr3)3043 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
3044 unsigned long cr3)
3045 {
3046 struct protection_domain *domain = to_pdomain(dom);
3047 unsigned long flags;
3048 int ret;
3049
3050 spin_lock_irqsave(&domain->lock, flags);
3051 ret = __set_gcr3(domain, pasid, cr3);
3052 spin_unlock_irqrestore(&domain->lock, flags);
3053
3054 return ret;
3055 }
3056 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3057
amd_iommu_domain_clear_gcr3(struct iommu_domain * dom,u32 pasid)3058 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid)
3059 {
3060 struct protection_domain *domain = to_pdomain(dom);
3061 unsigned long flags;
3062 int ret;
3063
3064 spin_lock_irqsave(&domain->lock, flags);
3065 ret = __clear_gcr3(domain, pasid);
3066 spin_unlock_irqrestore(&domain->lock, flags);
3067
3068 return ret;
3069 }
3070 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3071
amd_iommu_complete_ppr(struct pci_dev * pdev,u32 pasid,int status,int tag)3072 int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
3073 int status, int tag)
3074 {
3075 struct iommu_dev_data *dev_data;
3076 struct amd_iommu *iommu;
3077 struct iommu_cmd cmd;
3078
3079 dev_data = dev_iommu_priv_get(&pdev->dev);
3080 iommu = amd_iommu_rlookup_table[dev_data->devid];
3081
3082 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3083 tag, dev_data->pri_tlp);
3084
3085 return iommu_queue_command(iommu, &cmd);
3086 }
3087 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3088
amd_iommu_get_v2_domain(struct pci_dev * pdev)3089 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3090 {
3091 struct protection_domain *pdomain;
3092 struct iommu_dev_data *dev_data;
3093 struct device *dev = &pdev->dev;
3094 struct iommu_domain *io_domain;
3095
3096 if (!check_device(dev))
3097 return NULL;
3098
3099 dev_data = dev_iommu_priv_get(&pdev->dev);
3100 pdomain = dev_data->domain;
3101 io_domain = iommu_get_domain_for_dev(dev);
3102
3103 if (pdomain == NULL && dev_data->defer_attach) {
3104 dev_data->defer_attach = false;
3105 pdomain = to_pdomain(io_domain);
3106 attach_device(dev, pdomain);
3107 }
3108
3109 if (pdomain == NULL)
3110 return NULL;
3111
3112 if (io_domain->type != IOMMU_DOMAIN_DMA)
3113 return NULL;
3114
3115 /* Only return IOMMUv2 domains */
3116 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3117 return NULL;
3118
3119 return &pdomain->domain;
3120 }
3121 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3122
amd_iommu_enable_device_erratum(struct pci_dev * pdev,u32 erratum)3123 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3124 {
3125 struct iommu_dev_data *dev_data;
3126
3127 if (!amd_iommu_v2_supported())
3128 return;
3129
3130 dev_data = dev_iommu_priv_get(&pdev->dev);
3131 dev_data->errata |= (1 << erratum);
3132 }
3133 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3134
amd_iommu_device_info(struct pci_dev * pdev,struct amd_iommu_device_info * info)3135 int amd_iommu_device_info(struct pci_dev *pdev,
3136 struct amd_iommu_device_info *info)
3137 {
3138 int max_pasids;
3139 int pos;
3140
3141 if (pdev == NULL || info == NULL)
3142 return -EINVAL;
3143
3144 if (!amd_iommu_v2_supported())
3145 return -EINVAL;
3146
3147 memset(info, 0, sizeof(*info));
3148
3149 if (pci_ats_supported(pdev))
3150 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3151
3152 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3153 if (pos)
3154 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3155
3156 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3157 if (pos) {
3158 int features;
3159
3160 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3161 max_pasids = min(max_pasids, (1 << 20));
3162
3163 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3164 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3165
3166 features = pci_pasid_features(pdev);
3167 if (features & PCI_PASID_CAP_EXEC)
3168 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3169 if (features & PCI_PASID_CAP_PRIV)
3170 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3171 }
3172
3173 return 0;
3174 }
3175 EXPORT_SYMBOL(amd_iommu_device_info);
3176
3177 #ifdef CONFIG_IRQ_REMAP
3178
3179 /*****************************************************************************
3180 *
3181 * Interrupt Remapping Implementation
3182 *
3183 *****************************************************************************/
3184
3185 static struct irq_chip amd_ir_chip;
3186 static DEFINE_SPINLOCK(iommu_table_lock);
3187
set_dte_irq_entry(u16 devid,struct irq_remap_table * table)3188 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3189 {
3190 u64 dte;
3191
3192 dte = amd_iommu_dev_table[devid].data[2];
3193 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3194 dte |= iommu_virt_to_phys(table->table);
3195 dte |= DTE_IRQ_REMAP_INTCTL;
3196 dte |= DTE_IRQ_TABLE_LEN;
3197 dte |= DTE_IRQ_REMAP_ENABLE;
3198
3199 amd_iommu_dev_table[devid].data[2] = dte;
3200 }
3201
get_irq_table(u16 devid)3202 static struct irq_remap_table *get_irq_table(u16 devid)
3203 {
3204 struct irq_remap_table *table;
3205
3206 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3207 "%s: no iommu for devid %x\n", __func__, devid))
3208 return NULL;
3209
3210 table = irq_lookup_table[devid];
3211 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3212 return NULL;
3213
3214 return table;
3215 }
3216
__alloc_irq_table(void)3217 static struct irq_remap_table *__alloc_irq_table(void)
3218 {
3219 struct irq_remap_table *table;
3220
3221 table = kzalloc(sizeof(*table), GFP_KERNEL);
3222 if (!table)
3223 return NULL;
3224
3225 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3226 if (!table->table) {
3227 kfree(table);
3228 return NULL;
3229 }
3230 raw_spin_lock_init(&table->lock);
3231
3232 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3233 memset(table->table, 0,
3234 MAX_IRQS_PER_TABLE * sizeof(u32));
3235 else
3236 memset(table->table, 0,
3237 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3238 return table;
3239 }
3240
set_remap_table_entry(struct amd_iommu * iommu,u16 devid,struct irq_remap_table * table)3241 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3242 struct irq_remap_table *table)
3243 {
3244 irq_lookup_table[devid] = table;
3245 set_dte_irq_entry(devid, table);
3246 iommu_flush_dte(iommu, devid);
3247 }
3248
set_remap_table_entry_alias(struct pci_dev * pdev,u16 alias,void * data)3249 static int set_remap_table_entry_alias(struct pci_dev *pdev, u16 alias,
3250 void *data)
3251 {
3252 struct irq_remap_table *table = data;
3253
3254 irq_lookup_table[alias] = table;
3255 set_dte_irq_entry(alias, table);
3256
3257 iommu_flush_dte(amd_iommu_rlookup_table[alias], alias);
3258
3259 return 0;
3260 }
3261
alloc_irq_table(u16 devid,struct pci_dev * pdev)3262 static struct irq_remap_table *alloc_irq_table(u16 devid, struct pci_dev *pdev)
3263 {
3264 struct irq_remap_table *table = NULL;
3265 struct irq_remap_table *new_table = NULL;
3266 struct amd_iommu *iommu;
3267 unsigned long flags;
3268 u16 alias;
3269
3270 spin_lock_irqsave(&iommu_table_lock, flags);
3271
3272 iommu = amd_iommu_rlookup_table[devid];
3273 if (!iommu)
3274 goto out_unlock;
3275
3276 table = irq_lookup_table[devid];
3277 if (table)
3278 goto out_unlock;
3279
3280 alias = amd_iommu_alias_table[devid];
3281 table = irq_lookup_table[alias];
3282 if (table) {
3283 set_remap_table_entry(iommu, devid, table);
3284 goto out_wait;
3285 }
3286 spin_unlock_irqrestore(&iommu_table_lock, flags);
3287
3288 /* Nothing there yet, allocate new irq remapping table */
3289 new_table = __alloc_irq_table();
3290 if (!new_table)
3291 return NULL;
3292
3293 spin_lock_irqsave(&iommu_table_lock, flags);
3294
3295 table = irq_lookup_table[devid];
3296 if (table)
3297 goto out_unlock;
3298
3299 table = irq_lookup_table[alias];
3300 if (table) {
3301 set_remap_table_entry(iommu, devid, table);
3302 goto out_wait;
3303 }
3304
3305 table = new_table;
3306 new_table = NULL;
3307
3308 if (pdev)
3309 pci_for_each_dma_alias(pdev, set_remap_table_entry_alias,
3310 table);
3311 else
3312 set_remap_table_entry(iommu, devid, table);
3313
3314 if (devid != alias)
3315 set_remap_table_entry(iommu, alias, table);
3316
3317 out_wait:
3318 iommu_completion_wait(iommu);
3319
3320 out_unlock:
3321 spin_unlock_irqrestore(&iommu_table_lock, flags);
3322
3323 if (new_table) {
3324 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3325 kfree(new_table);
3326 }
3327 return table;
3328 }
3329
alloc_irq_index(u16 devid,int count,bool align,struct pci_dev * pdev)3330 static int alloc_irq_index(u16 devid, int count, bool align,
3331 struct pci_dev *pdev)
3332 {
3333 struct irq_remap_table *table;
3334 int index, c, alignment = 1;
3335 unsigned long flags;
3336 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3337
3338 if (!iommu)
3339 return -ENODEV;
3340
3341 table = alloc_irq_table(devid, pdev);
3342 if (!table)
3343 return -ENODEV;
3344
3345 if (align)
3346 alignment = roundup_pow_of_two(count);
3347
3348 raw_spin_lock_irqsave(&table->lock, flags);
3349
3350 /* Scan table for free entries */
3351 for (index = ALIGN(table->min_index, alignment), c = 0;
3352 index < MAX_IRQS_PER_TABLE;) {
3353 if (!iommu->irte_ops->is_allocated(table, index)) {
3354 c += 1;
3355 } else {
3356 c = 0;
3357 index = ALIGN(index + 1, alignment);
3358 continue;
3359 }
3360
3361 if (c == count) {
3362 for (; c != 0; --c)
3363 iommu->irte_ops->set_allocated(table, index - c + 1);
3364
3365 index -= count - 1;
3366 goto out;
3367 }
3368
3369 index++;
3370 }
3371
3372 index = -ENOSPC;
3373
3374 out:
3375 raw_spin_unlock_irqrestore(&table->lock, flags);
3376
3377 return index;
3378 }
3379
modify_irte_ga(u16 devid,int index,struct irte_ga * irte,struct amd_ir_data * data)3380 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3381 struct amd_ir_data *data)
3382 {
3383 bool ret;
3384 struct irq_remap_table *table;
3385 struct amd_iommu *iommu;
3386 unsigned long flags;
3387 struct irte_ga *entry;
3388
3389 iommu = amd_iommu_rlookup_table[devid];
3390 if (iommu == NULL)
3391 return -EINVAL;
3392
3393 table = get_irq_table(devid);
3394 if (!table)
3395 return -ENOMEM;
3396
3397 raw_spin_lock_irqsave(&table->lock, flags);
3398
3399 entry = (struct irte_ga *)table->table;
3400 entry = &entry[index];
3401
3402 ret = cmpxchg_double(&entry->lo.val, &entry->hi.val,
3403 entry->lo.val, entry->hi.val,
3404 irte->lo.val, irte->hi.val);
3405 /*
3406 * We use cmpxchg16 to atomically update the 128-bit IRTE,
3407 * and it cannot be updated by the hardware or other processors
3408 * behind us, so the return value of cmpxchg16 should be the
3409 * same as the old value.
3410 */
3411 WARN_ON(!ret);
3412
3413 if (data)
3414 data->ref = entry;
3415
3416 raw_spin_unlock_irqrestore(&table->lock, flags);
3417
3418 iommu_flush_irt(iommu, devid);
3419 iommu_completion_wait(iommu);
3420
3421 return 0;
3422 }
3423
modify_irte(u16 devid,int index,union irte * irte)3424 static int modify_irte(u16 devid, int index, union irte *irte)
3425 {
3426 struct irq_remap_table *table;
3427 struct amd_iommu *iommu;
3428 unsigned long flags;
3429
3430 iommu = amd_iommu_rlookup_table[devid];
3431 if (iommu == NULL)
3432 return -EINVAL;
3433
3434 table = get_irq_table(devid);
3435 if (!table)
3436 return -ENOMEM;
3437
3438 raw_spin_lock_irqsave(&table->lock, flags);
3439 table->table[index] = irte->val;
3440 raw_spin_unlock_irqrestore(&table->lock, flags);
3441
3442 iommu_flush_irt(iommu, devid);
3443 iommu_completion_wait(iommu);
3444
3445 return 0;
3446 }
3447
free_irte(u16 devid,int index)3448 static void free_irte(u16 devid, int index)
3449 {
3450 struct irq_remap_table *table;
3451 struct amd_iommu *iommu;
3452 unsigned long flags;
3453
3454 iommu = amd_iommu_rlookup_table[devid];
3455 if (iommu == NULL)
3456 return;
3457
3458 table = get_irq_table(devid);
3459 if (!table)
3460 return;
3461
3462 raw_spin_lock_irqsave(&table->lock, flags);
3463 iommu->irte_ops->clear_allocated(table, index);
3464 raw_spin_unlock_irqrestore(&table->lock, flags);
3465
3466 iommu_flush_irt(iommu, devid);
3467 iommu_completion_wait(iommu);
3468 }
3469
irte_prepare(void * entry,u32 delivery_mode,u32 dest_mode,u8 vector,u32 dest_apicid,int devid)3470 static void irte_prepare(void *entry,
3471 u32 delivery_mode, u32 dest_mode,
3472 u8 vector, u32 dest_apicid, int devid)
3473 {
3474 union irte *irte = (union irte *) entry;
3475
3476 irte->val = 0;
3477 irte->fields.vector = vector;
3478 irte->fields.int_type = delivery_mode;
3479 irte->fields.destination = dest_apicid;
3480 irte->fields.dm = dest_mode;
3481 irte->fields.valid = 1;
3482 }
3483
irte_ga_prepare(void * entry,u32 delivery_mode,u32 dest_mode,u8 vector,u32 dest_apicid,int devid)3484 static void irte_ga_prepare(void *entry,
3485 u32 delivery_mode, u32 dest_mode,
3486 u8 vector, u32 dest_apicid, int devid)
3487 {
3488 struct irte_ga *irte = (struct irte_ga *) entry;
3489
3490 irte->lo.val = 0;
3491 irte->hi.val = 0;
3492 irte->lo.fields_remap.int_type = delivery_mode;
3493 irte->lo.fields_remap.dm = dest_mode;
3494 irte->hi.fields.vector = vector;
3495 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3496 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3497 irte->lo.fields_remap.valid = 1;
3498 }
3499
irte_activate(void * entry,u16 devid,u16 index)3500 static void irte_activate(void *entry, u16 devid, u16 index)
3501 {
3502 union irte *irte = (union irte *) entry;
3503
3504 irte->fields.valid = 1;
3505 modify_irte(devid, index, irte);
3506 }
3507
irte_ga_activate(void * entry,u16 devid,u16 index)3508 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3509 {
3510 struct irte_ga *irte = (struct irte_ga *) entry;
3511
3512 irte->lo.fields_remap.valid = 1;
3513 modify_irte_ga(devid, index, irte, NULL);
3514 }
3515
irte_deactivate(void * entry,u16 devid,u16 index)3516 static void irte_deactivate(void *entry, u16 devid, u16 index)
3517 {
3518 union irte *irte = (union irte *) entry;
3519
3520 irte->fields.valid = 0;
3521 modify_irte(devid, index, irte);
3522 }
3523
irte_ga_deactivate(void * entry,u16 devid,u16 index)3524 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3525 {
3526 struct irte_ga *irte = (struct irte_ga *) entry;
3527
3528 irte->lo.fields_remap.valid = 0;
3529 modify_irte_ga(devid, index, irte, NULL);
3530 }
3531
irte_set_affinity(void * entry,u16 devid,u16 index,u8 vector,u32 dest_apicid)3532 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3533 u8 vector, u32 dest_apicid)
3534 {
3535 union irte *irte = (union irte *) entry;
3536
3537 irte->fields.vector = vector;
3538 irte->fields.destination = dest_apicid;
3539 modify_irte(devid, index, irte);
3540 }
3541
irte_ga_set_affinity(void * entry,u16 devid,u16 index,u8 vector,u32 dest_apicid)3542 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3543 u8 vector, u32 dest_apicid)
3544 {
3545 struct irte_ga *irte = (struct irte_ga *) entry;
3546
3547 if (!irte->lo.fields_remap.guest_mode) {
3548 irte->hi.fields.vector = vector;
3549 irte->lo.fields_remap.destination =
3550 APICID_TO_IRTE_DEST_LO(dest_apicid);
3551 irte->hi.fields.destination =
3552 APICID_TO_IRTE_DEST_HI(dest_apicid);
3553 modify_irte_ga(devid, index, irte, NULL);
3554 }
3555 }
3556
3557 #define IRTE_ALLOCATED (~1U)
irte_set_allocated(struct irq_remap_table * table,int index)3558 static void irte_set_allocated(struct irq_remap_table *table, int index)
3559 {
3560 table->table[index] = IRTE_ALLOCATED;
3561 }
3562
irte_ga_set_allocated(struct irq_remap_table * table,int index)3563 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3564 {
3565 struct irte_ga *ptr = (struct irte_ga *)table->table;
3566 struct irte_ga *irte = &ptr[index];
3567
3568 memset(&irte->lo.val, 0, sizeof(u64));
3569 memset(&irte->hi.val, 0, sizeof(u64));
3570 irte->hi.fields.vector = 0xff;
3571 }
3572
irte_is_allocated(struct irq_remap_table * table,int index)3573 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3574 {
3575 union irte *ptr = (union irte *)table->table;
3576 union irte *irte = &ptr[index];
3577
3578 return irte->val != 0;
3579 }
3580
irte_ga_is_allocated(struct irq_remap_table * table,int index)3581 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3582 {
3583 struct irte_ga *ptr = (struct irte_ga *)table->table;
3584 struct irte_ga *irte = &ptr[index];
3585
3586 return irte->hi.fields.vector != 0;
3587 }
3588
irte_clear_allocated(struct irq_remap_table * table,int index)3589 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3590 {
3591 table->table[index] = 0;
3592 }
3593
irte_ga_clear_allocated(struct irq_remap_table * table,int index)3594 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3595 {
3596 struct irte_ga *ptr = (struct irte_ga *)table->table;
3597 struct irte_ga *irte = &ptr[index];
3598
3599 memset(&irte->lo.val, 0, sizeof(u64));
3600 memset(&irte->hi.val, 0, sizeof(u64));
3601 }
3602
get_devid(struct irq_alloc_info * info)3603 static int get_devid(struct irq_alloc_info *info)
3604 {
3605 switch (info->type) {
3606 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3607 case X86_IRQ_ALLOC_TYPE_IOAPIC_GET_PARENT:
3608 return get_ioapic_devid(info->devid);
3609 case X86_IRQ_ALLOC_TYPE_HPET:
3610 case X86_IRQ_ALLOC_TYPE_HPET_GET_PARENT:
3611 return get_hpet_devid(info->devid);
3612 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
3613 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
3614 return get_device_id(msi_desc_to_dev(info->desc));
3615 default:
3616 WARN_ON_ONCE(1);
3617 return -1;
3618 }
3619 }
3620
get_irq_domain_for_devid(struct irq_alloc_info * info,int devid)3621 static struct irq_domain *get_irq_domain_for_devid(struct irq_alloc_info *info,
3622 int devid)
3623 {
3624 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3625
3626 if (!iommu)
3627 return NULL;
3628
3629 switch (info->type) {
3630 case X86_IRQ_ALLOC_TYPE_IOAPIC_GET_PARENT:
3631 case X86_IRQ_ALLOC_TYPE_HPET_GET_PARENT:
3632 return iommu->ir_domain;
3633 default:
3634 WARN_ON_ONCE(1);
3635 return NULL;
3636 }
3637 }
3638
get_irq_domain(struct irq_alloc_info * info)3639 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
3640 {
3641 int devid;
3642
3643 if (!info)
3644 return NULL;
3645
3646 devid = get_devid(info);
3647 if (devid < 0)
3648 return NULL;
3649 return get_irq_domain_for_devid(info, devid);
3650 }
3651
3652 struct irq_remap_ops amd_iommu_irq_ops = {
3653 .prepare = amd_iommu_prepare,
3654 .enable = amd_iommu_enable,
3655 .disable = amd_iommu_disable,
3656 .reenable = amd_iommu_reenable,
3657 .enable_faulting = amd_iommu_enable_faulting,
3658 .get_irq_domain = get_irq_domain,
3659 };
3660
irq_remapping_prepare_irte(struct amd_ir_data * data,struct irq_cfg * irq_cfg,struct irq_alloc_info * info,int devid,int index,int sub_handle)3661 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
3662 struct irq_cfg *irq_cfg,
3663 struct irq_alloc_info *info,
3664 int devid, int index, int sub_handle)
3665 {
3666 struct irq_2_irte *irte_info = &data->irq_2_irte;
3667 struct msi_msg *msg = &data->msi_entry;
3668 struct IO_APIC_route_entry *entry;
3669 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3670
3671 if (!iommu)
3672 return;
3673
3674 data->irq_2_irte.devid = devid;
3675 data->irq_2_irte.index = index + sub_handle;
3676 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
3677 apic->irq_dest_mode, irq_cfg->vector,
3678 irq_cfg->dest_apicid, devid);
3679
3680 switch (info->type) {
3681 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3682 /* Setup IOAPIC entry */
3683 entry = info->ioapic.entry;
3684 info->ioapic.entry = NULL;
3685 memset(entry, 0, sizeof(*entry));
3686 entry->vector = index;
3687 entry->mask = 0;
3688 entry->trigger = info->ioapic.trigger;
3689 entry->polarity = info->ioapic.polarity;
3690 /* Mask level triggered irqs. */
3691 if (info->ioapic.trigger)
3692 entry->mask = 1;
3693 break;
3694
3695 case X86_IRQ_ALLOC_TYPE_HPET:
3696 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
3697 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
3698 msg->address_hi = MSI_ADDR_BASE_HI;
3699 msg->address_lo = MSI_ADDR_BASE_LO;
3700 msg->data = irte_info->index;
3701 break;
3702
3703 default:
3704 BUG_ON(1);
3705 break;
3706 }
3707 }
3708
3709 struct amd_irte_ops irte_32_ops = {
3710 .prepare = irte_prepare,
3711 .activate = irte_activate,
3712 .deactivate = irte_deactivate,
3713 .set_affinity = irte_set_affinity,
3714 .set_allocated = irte_set_allocated,
3715 .is_allocated = irte_is_allocated,
3716 .clear_allocated = irte_clear_allocated,
3717 };
3718
3719 struct amd_irte_ops irte_128_ops = {
3720 .prepare = irte_ga_prepare,
3721 .activate = irte_ga_activate,
3722 .deactivate = irte_ga_deactivate,
3723 .set_affinity = irte_ga_set_affinity,
3724 .set_allocated = irte_ga_set_allocated,
3725 .is_allocated = irte_ga_is_allocated,
3726 .clear_allocated = irte_ga_clear_allocated,
3727 };
3728
irq_remapping_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)3729 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
3730 unsigned int nr_irqs, void *arg)
3731 {
3732 struct irq_alloc_info *info = arg;
3733 struct irq_data *irq_data;
3734 struct amd_ir_data *data = NULL;
3735 struct irq_cfg *cfg;
3736 int i, ret, devid;
3737 int index;
3738
3739 if (!info)
3740 return -EINVAL;
3741 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI &&
3742 info->type != X86_IRQ_ALLOC_TYPE_PCI_MSIX)
3743 return -EINVAL;
3744
3745 /*
3746 * With IRQ remapping enabled, don't need contiguous CPU vectors
3747 * to support multiple MSI interrupts.
3748 */
3749 if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI)
3750 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
3751
3752 devid = get_devid(info);
3753 if (devid < 0)
3754 return -EINVAL;
3755
3756 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
3757 if (ret < 0)
3758 return ret;
3759
3760 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
3761 struct irq_remap_table *table;
3762 struct amd_iommu *iommu;
3763
3764 table = alloc_irq_table(devid, NULL);
3765 if (table) {
3766 if (!table->min_index) {
3767 /*
3768 * Keep the first 32 indexes free for IOAPIC
3769 * interrupts.
3770 */
3771 table->min_index = 32;
3772 iommu = amd_iommu_rlookup_table[devid];
3773 for (i = 0; i < 32; ++i)
3774 iommu->irte_ops->set_allocated(table, i);
3775 }
3776 WARN_ON(table->min_index != 32);
3777 index = info->ioapic.pin;
3778 } else {
3779 index = -ENOMEM;
3780 }
3781 } else if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI ||
3782 info->type == X86_IRQ_ALLOC_TYPE_PCI_MSIX) {
3783 bool align = (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI);
3784
3785 index = alloc_irq_index(devid, nr_irqs, align,
3786 msi_desc_to_pci_dev(info->desc));
3787 } else {
3788 index = alloc_irq_index(devid, nr_irqs, false, NULL);
3789 }
3790
3791 if (index < 0) {
3792 pr_warn("Failed to allocate IRTE\n");
3793 ret = index;
3794 goto out_free_parent;
3795 }
3796
3797 for (i = 0; i < nr_irqs; i++) {
3798 irq_data = irq_domain_get_irq_data(domain, virq + i);
3799 cfg = irq_data ? irqd_cfg(irq_data) : NULL;
3800 if (!cfg) {
3801 ret = -EINVAL;
3802 goto out_free_data;
3803 }
3804
3805 ret = -ENOMEM;
3806 data = kzalloc(sizeof(*data), GFP_KERNEL);
3807 if (!data)
3808 goto out_free_data;
3809
3810 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3811 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
3812 else
3813 data->entry = kzalloc(sizeof(struct irte_ga),
3814 GFP_KERNEL);
3815 if (!data->entry) {
3816 kfree(data);
3817 goto out_free_data;
3818 }
3819
3820 irq_data->hwirq = (devid << 16) + i;
3821 irq_data->chip_data = data;
3822 irq_data->chip = &amd_ir_chip;
3823 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
3824 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
3825 }
3826
3827 return 0;
3828
3829 out_free_data:
3830 for (i--; i >= 0; i--) {
3831 irq_data = irq_domain_get_irq_data(domain, virq + i);
3832 if (irq_data)
3833 kfree(irq_data->chip_data);
3834 }
3835 for (i = 0; i < nr_irqs; i++)
3836 free_irte(devid, index + i);
3837 out_free_parent:
3838 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3839 return ret;
3840 }
3841
irq_remapping_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)3842 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
3843 unsigned int nr_irqs)
3844 {
3845 struct irq_2_irte *irte_info;
3846 struct irq_data *irq_data;
3847 struct amd_ir_data *data;
3848 int i;
3849
3850 for (i = 0; i < nr_irqs; i++) {
3851 irq_data = irq_domain_get_irq_data(domain, virq + i);
3852 if (irq_data && irq_data->chip_data) {
3853 data = irq_data->chip_data;
3854 irte_info = &data->irq_2_irte;
3855 free_irte(irte_info->devid, irte_info->index);
3856 kfree(data->entry);
3857 kfree(data);
3858 }
3859 }
3860 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3861 }
3862
3863 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
3864 struct amd_ir_data *ir_data,
3865 struct irq_2_irte *irte_info,
3866 struct irq_cfg *cfg);
3867
irq_remapping_activate(struct irq_domain * domain,struct irq_data * irq_data,bool reserve)3868 static int irq_remapping_activate(struct irq_domain *domain,
3869 struct irq_data *irq_data, bool reserve)
3870 {
3871 struct amd_ir_data *data = irq_data->chip_data;
3872 struct irq_2_irte *irte_info = &data->irq_2_irte;
3873 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3874 struct irq_cfg *cfg = irqd_cfg(irq_data);
3875
3876 if (!iommu)
3877 return 0;
3878
3879 iommu->irte_ops->activate(data->entry, irte_info->devid,
3880 irte_info->index);
3881 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
3882 return 0;
3883 }
3884
irq_remapping_deactivate(struct irq_domain * domain,struct irq_data * irq_data)3885 static void irq_remapping_deactivate(struct irq_domain *domain,
3886 struct irq_data *irq_data)
3887 {
3888 struct amd_ir_data *data = irq_data->chip_data;
3889 struct irq_2_irte *irte_info = &data->irq_2_irte;
3890 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3891
3892 if (iommu)
3893 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
3894 irte_info->index);
3895 }
3896
3897 static const struct irq_domain_ops amd_ir_domain_ops = {
3898 .alloc = irq_remapping_alloc,
3899 .free = irq_remapping_free,
3900 .activate = irq_remapping_activate,
3901 .deactivate = irq_remapping_deactivate,
3902 };
3903
amd_iommu_activate_guest_mode(void * data)3904 int amd_iommu_activate_guest_mode(void *data)
3905 {
3906 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3907 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3908 u64 valid;
3909
3910 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3911 !entry || entry->lo.fields_vapic.guest_mode)
3912 return 0;
3913
3914 valid = entry->lo.fields_vapic.valid;
3915
3916 entry->lo.val = 0;
3917 entry->hi.val = 0;
3918
3919 entry->lo.fields_vapic.valid = valid;
3920 entry->lo.fields_vapic.guest_mode = 1;
3921 entry->lo.fields_vapic.ga_log_intr = 1;
3922 entry->hi.fields.ga_root_ptr = ir_data->ga_root_ptr;
3923 entry->hi.fields.vector = ir_data->ga_vector;
3924 entry->lo.fields_vapic.ga_tag = ir_data->ga_tag;
3925
3926 return modify_irte_ga(ir_data->irq_2_irte.devid,
3927 ir_data->irq_2_irte.index, entry, ir_data);
3928 }
3929 EXPORT_SYMBOL(amd_iommu_activate_guest_mode);
3930
amd_iommu_deactivate_guest_mode(void * data)3931 int amd_iommu_deactivate_guest_mode(void *data)
3932 {
3933 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3934 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3935 struct irq_cfg *cfg = ir_data->cfg;
3936 u64 valid;
3937
3938 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3939 !entry || !entry->lo.fields_vapic.guest_mode)
3940 return 0;
3941
3942 valid = entry->lo.fields_remap.valid;
3943
3944 entry->lo.val = 0;
3945 entry->hi.val = 0;
3946
3947 entry->lo.fields_remap.valid = valid;
3948 entry->lo.fields_remap.dm = apic->irq_dest_mode;
3949 entry->lo.fields_remap.int_type = apic->irq_delivery_mode;
3950 entry->hi.fields.vector = cfg->vector;
3951 entry->lo.fields_remap.destination =
3952 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
3953 entry->hi.fields.destination =
3954 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
3955
3956 return modify_irte_ga(ir_data->irq_2_irte.devid,
3957 ir_data->irq_2_irte.index, entry, ir_data);
3958 }
3959 EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode);
3960
amd_ir_set_vcpu_affinity(struct irq_data * data,void * vcpu_info)3961 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
3962 {
3963 int ret;
3964 struct amd_iommu *iommu;
3965 struct amd_iommu_pi_data *pi_data = vcpu_info;
3966 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
3967 struct amd_ir_data *ir_data = data->chip_data;
3968 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3969 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
3970
3971 /* Note:
3972 * This device has never been set up for guest mode.
3973 * we should not modify the IRTE
3974 */
3975 if (!dev_data || !dev_data->use_vapic)
3976 return 0;
3977
3978 ir_data->cfg = irqd_cfg(data);
3979 pi_data->ir_data = ir_data;
3980
3981 /* Note:
3982 * SVM tries to set up for VAPIC mode, but we are in
3983 * legacy mode. So, we force legacy mode instead.
3984 */
3985 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3986 pr_debug("%s: Fall back to using intr legacy remap\n",
3987 __func__);
3988 pi_data->is_guest_mode = false;
3989 }
3990
3991 iommu = amd_iommu_rlookup_table[irte_info->devid];
3992 if (iommu == NULL)
3993 return -EINVAL;
3994
3995 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
3996 if (pi_data->is_guest_mode) {
3997 ir_data->ga_root_ptr = (pi_data->base >> 12);
3998 ir_data->ga_vector = vcpu_pi_info->vector;
3999 ir_data->ga_tag = pi_data->ga_tag;
4000 ret = amd_iommu_activate_guest_mode(ir_data);
4001 if (!ret)
4002 ir_data->cached_ga_tag = pi_data->ga_tag;
4003 } else {
4004 ret = amd_iommu_deactivate_guest_mode(ir_data);
4005
4006 /*
4007 * This communicates the ga_tag back to the caller
4008 * so that it can do all the necessary clean up.
4009 */
4010 if (!ret)
4011 ir_data->cached_ga_tag = 0;
4012 }
4013
4014 return ret;
4015 }
4016
4017
amd_ir_update_irte(struct irq_data * irqd,struct amd_iommu * iommu,struct amd_ir_data * ir_data,struct irq_2_irte * irte_info,struct irq_cfg * cfg)4018 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4019 struct amd_ir_data *ir_data,
4020 struct irq_2_irte *irte_info,
4021 struct irq_cfg *cfg)
4022 {
4023
4024 /*
4025 * Atomically updates the IRTE with the new destination, vector
4026 * and flushes the interrupt entry cache.
4027 */
4028 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4029 irte_info->index, cfg->vector,
4030 cfg->dest_apicid);
4031 }
4032
amd_ir_set_affinity(struct irq_data * data,const struct cpumask * mask,bool force)4033 static int amd_ir_set_affinity(struct irq_data *data,
4034 const struct cpumask *mask, bool force)
4035 {
4036 struct amd_ir_data *ir_data = data->chip_data;
4037 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4038 struct irq_cfg *cfg = irqd_cfg(data);
4039 struct irq_data *parent = data->parent_data;
4040 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4041 int ret;
4042
4043 if (!iommu)
4044 return -ENODEV;
4045
4046 ret = parent->chip->irq_set_affinity(parent, mask, force);
4047 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4048 return ret;
4049
4050 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4051 /*
4052 * After this point, all the interrupts will start arriving
4053 * at the new destination. So, time to cleanup the previous
4054 * vector allocation.
4055 */
4056 send_cleanup_vector(cfg);
4057
4058 return IRQ_SET_MASK_OK_DONE;
4059 }
4060
ir_compose_msi_msg(struct irq_data * irq_data,struct msi_msg * msg)4061 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4062 {
4063 struct amd_ir_data *ir_data = irq_data->chip_data;
4064
4065 *msg = ir_data->msi_entry;
4066 }
4067
4068 static struct irq_chip amd_ir_chip = {
4069 .name = "AMD-IR",
4070 .irq_ack = apic_ack_irq,
4071 .irq_set_affinity = amd_ir_set_affinity,
4072 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4073 .irq_compose_msi_msg = ir_compose_msi_msg,
4074 };
4075
amd_iommu_create_irq_domain(struct amd_iommu * iommu)4076 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4077 {
4078 struct fwnode_handle *fn;
4079
4080 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4081 if (!fn)
4082 return -ENOMEM;
4083 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4084 if (!iommu->ir_domain) {
4085 irq_domain_free_fwnode(fn);
4086 return -ENOMEM;
4087 }
4088
4089 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4090 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4091 "AMD-IR-MSI",
4092 iommu->index);
4093 return 0;
4094 }
4095
amd_iommu_update_ga(int cpu,bool is_run,void * data)4096 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4097 {
4098 unsigned long flags;
4099 struct amd_iommu *iommu;
4100 struct irq_remap_table *table;
4101 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4102 int devid = ir_data->irq_2_irte.devid;
4103 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4104 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4105
4106 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4107 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4108 return 0;
4109
4110 iommu = amd_iommu_rlookup_table[devid];
4111 if (!iommu)
4112 return -ENODEV;
4113
4114 table = get_irq_table(devid);
4115 if (!table)
4116 return -ENODEV;
4117
4118 raw_spin_lock_irqsave(&table->lock, flags);
4119
4120 if (ref->lo.fields_vapic.guest_mode) {
4121 if (cpu >= 0) {
4122 ref->lo.fields_vapic.destination =
4123 APICID_TO_IRTE_DEST_LO(cpu);
4124 ref->hi.fields.destination =
4125 APICID_TO_IRTE_DEST_HI(cpu);
4126 }
4127 ref->lo.fields_vapic.is_run = is_run;
4128 barrier();
4129 }
4130
4131 raw_spin_unlock_irqrestore(&table->lock, flags);
4132
4133 iommu_flush_irt(iommu, devid);
4134 iommu_completion_wait(iommu);
4135 return 0;
4136 }
4137 EXPORT_SYMBOL(amd_iommu_update_ga);
4138 #endif
4139