1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Mediatek MT7530 DSA Switch driver
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
5 */
6 #include <linux/etherdevice.h>
7 #include <linux/if_bridge.h>
8 #include <linux/iopoll.h>
9 #include <linux/mdio.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/module.h>
12 #include <linux/netdevice.h>
13 #include <linux/of_mdio.h>
14 #include <linux/of_net.h>
15 #include <linux/of_platform.h>
16 #include <linux/phylink.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/reset.h>
20 #include <linux/gpio/consumer.h>
21 #include <net/dsa.h>
22
23 #include "mt7530.h"
24
25 /* String, offset, and register size in bytes if different from 4 bytes */
26 static const struct mt7530_mib_desc mt7530_mib[] = {
27 MIB_DESC(1, 0x00, "TxDrop"),
28 MIB_DESC(1, 0x04, "TxCrcErr"),
29 MIB_DESC(1, 0x08, "TxUnicast"),
30 MIB_DESC(1, 0x0c, "TxMulticast"),
31 MIB_DESC(1, 0x10, "TxBroadcast"),
32 MIB_DESC(1, 0x14, "TxCollision"),
33 MIB_DESC(1, 0x18, "TxSingleCollision"),
34 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
35 MIB_DESC(1, 0x20, "TxDeferred"),
36 MIB_DESC(1, 0x24, "TxLateCollision"),
37 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
38 MIB_DESC(1, 0x2c, "TxPause"),
39 MIB_DESC(1, 0x30, "TxPktSz64"),
40 MIB_DESC(1, 0x34, "TxPktSz65To127"),
41 MIB_DESC(1, 0x38, "TxPktSz128To255"),
42 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
43 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
44 MIB_DESC(1, 0x44, "Tx1024ToMax"),
45 MIB_DESC(2, 0x48, "TxBytes"),
46 MIB_DESC(1, 0x60, "RxDrop"),
47 MIB_DESC(1, 0x64, "RxFiltering"),
48 MIB_DESC(1, 0x68, "RxUnicast"),
49 MIB_DESC(1, 0x6c, "RxMulticast"),
50 MIB_DESC(1, 0x70, "RxBroadcast"),
51 MIB_DESC(1, 0x74, "RxAlignErr"),
52 MIB_DESC(1, 0x78, "RxCrcErr"),
53 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
54 MIB_DESC(1, 0x80, "RxFragErr"),
55 MIB_DESC(1, 0x84, "RxOverSzErr"),
56 MIB_DESC(1, 0x88, "RxJabberErr"),
57 MIB_DESC(1, 0x8c, "RxPause"),
58 MIB_DESC(1, 0x90, "RxPktSz64"),
59 MIB_DESC(1, 0x94, "RxPktSz65To127"),
60 MIB_DESC(1, 0x98, "RxPktSz128To255"),
61 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
62 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
63 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
64 MIB_DESC(2, 0xa8, "RxBytes"),
65 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
66 MIB_DESC(1, 0xb4, "RxIngressDrop"),
67 MIB_DESC(1, 0xb8, "RxArlDrop"),
68 };
69
70 static int
core_read_mmd_indirect(struct mt7530_priv * priv,int prtad,int devad)71 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
72 {
73 struct mii_bus *bus = priv->bus;
74 int value, ret;
75
76 /* Write the desired MMD Devad */
77 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
78 if (ret < 0)
79 goto err;
80
81 /* Write the desired MMD register address */
82 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
83 if (ret < 0)
84 goto err;
85
86 /* Select the Function : DATA with no post increment */
87 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
88 if (ret < 0)
89 goto err;
90
91 /* Read the content of the MMD's selected register */
92 value = bus->read(bus, 0, MII_MMD_DATA);
93
94 return value;
95 err:
96 dev_err(&bus->dev, "failed to read mmd register\n");
97
98 return ret;
99 }
100
101 static int
core_write_mmd_indirect(struct mt7530_priv * priv,int prtad,int devad,u32 data)102 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
103 int devad, u32 data)
104 {
105 struct mii_bus *bus = priv->bus;
106 int ret;
107
108 /* Write the desired MMD Devad */
109 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
110 if (ret < 0)
111 goto err;
112
113 /* Write the desired MMD register address */
114 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
115 if (ret < 0)
116 goto err;
117
118 /* Select the Function : DATA with no post increment */
119 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
120 if (ret < 0)
121 goto err;
122
123 /* Write the data into MMD's selected register */
124 ret = bus->write(bus, 0, MII_MMD_DATA, data);
125 err:
126 if (ret < 0)
127 dev_err(&bus->dev,
128 "failed to write mmd register\n");
129 return ret;
130 }
131
132 static void
core_write(struct mt7530_priv * priv,u32 reg,u32 val)133 core_write(struct mt7530_priv *priv, u32 reg, u32 val)
134 {
135 struct mii_bus *bus = priv->bus;
136
137 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
138
139 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
140
141 mutex_unlock(&bus->mdio_lock);
142 }
143
144 static void
core_rmw(struct mt7530_priv * priv,u32 reg,u32 mask,u32 set)145 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
146 {
147 struct mii_bus *bus = priv->bus;
148 u32 val;
149
150 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
151
152 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
153 val &= ~mask;
154 val |= set;
155 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
156
157 mutex_unlock(&bus->mdio_lock);
158 }
159
160 static void
core_set(struct mt7530_priv * priv,u32 reg,u32 val)161 core_set(struct mt7530_priv *priv, u32 reg, u32 val)
162 {
163 core_rmw(priv, reg, 0, val);
164 }
165
166 static void
core_clear(struct mt7530_priv * priv,u32 reg,u32 val)167 core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
168 {
169 core_rmw(priv, reg, val, 0);
170 }
171
172 static int
mt7530_mii_write(struct mt7530_priv * priv,u32 reg,u32 val)173 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
174 {
175 struct mii_bus *bus = priv->bus;
176 u16 page, r, lo, hi;
177 int ret;
178
179 page = (reg >> 6) & 0x3ff;
180 r = (reg >> 2) & 0xf;
181 lo = val & 0xffff;
182 hi = val >> 16;
183
184 /* MT7530 uses 31 as the pseudo port */
185 ret = bus->write(bus, 0x1f, 0x1f, page);
186 if (ret < 0)
187 goto err;
188
189 ret = bus->write(bus, 0x1f, r, lo);
190 if (ret < 0)
191 goto err;
192
193 ret = bus->write(bus, 0x1f, 0x10, hi);
194 err:
195 if (ret < 0)
196 dev_err(&bus->dev,
197 "failed to write mt7530 register\n");
198 return ret;
199 }
200
201 static u32
mt7530_mii_read(struct mt7530_priv * priv,u32 reg)202 mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
203 {
204 struct mii_bus *bus = priv->bus;
205 u16 page, r, lo, hi;
206 int ret;
207
208 page = (reg >> 6) & 0x3ff;
209 r = (reg >> 2) & 0xf;
210
211 /* MT7530 uses 31 as the pseudo port */
212 ret = bus->write(bus, 0x1f, 0x1f, page);
213 if (ret < 0) {
214 dev_err(&bus->dev,
215 "failed to read mt7530 register\n");
216 return ret;
217 }
218
219 lo = bus->read(bus, 0x1f, r);
220 hi = bus->read(bus, 0x1f, 0x10);
221
222 return (hi << 16) | (lo & 0xffff);
223 }
224
225 static void
mt7530_write(struct mt7530_priv * priv,u32 reg,u32 val)226 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
227 {
228 struct mii_bus *bus = priv->bus;
229
230 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
231
232 mt7530_mii_write(priv, reg, val);
233
234 mutex_unlock(&bus->mdio_lock);
235 }
236
237 static u32
_mt7530_unlocked_read(struct mt7530_dummy_poll * p)238 _mt7530_unlocked_read(struct mt7530_dummy_poll *p)
239 {
240 return mt7530_mii_read(p->priv, p->reg);
241 }
242
243 static u32
_mt7530_read(struct mt7530_dummy_poll * p)244 _mt7530_read(struct mt7530_dummy_poll *p)
245 {
246 struct mii_bus *bus = p->priv->bus;
247 u32 val;
248
249 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
250
251 val = mt7530_mii_read(p->priv, p->reg);
252
253 mutex_unlock(&bus->mdio_lock);
254
255 return val;
256 }
257
258 static u32
mt7530_read(struct mt7530_priv * priv,u32 reg)259 mt7530_read(struct mt7530_priv *priv, u32 reg)
260 {
261 struct mt7530_dummy_poll p;
262
263 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
264 return _mt7530_read(&p);
265 }
266
267 static void
mt7530_rmw(struct mt7530_priv * priv,u32 reg,u32 mask,u32 set)268 mt7530_rmw(struct mt7530_priv *priv, u32 reg,
269 u32 mask, u32 set)
270 {
271 struct mii_bus *bus = priv->bus;
272 u32 val;
273
274 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
275
276 val = mt7530_mii_read(priv, reg);
277 val &= ~mask;
278 val |= set;
279 mt7530_mii_write(priv, reg, val);
280
281 mutex_unlock(&bus->mdio_lock);
282 }
283
284 static void
mt7530_set(struct mt7530_priv * priv,u32 reg,u32 val)285 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
286 {
287 mt7530_rmw(priv, reg, 0, val);
288 }
289
290 static void
mt7530_clear(struct mt7530_priv * priv,u32 reg,u32 val)291 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
292 {
293 mt7530_rmw(priv, reg, val, 0);
294 }
295
296 static int
mt7530_fdb_cmd(struct mt7530_priv * priv,enum mt7530_fdb_cmd cmd,u32 * rsp)297 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
298 {
299 u32 val;
300 int ret;
301 struct mt7530_dummy_poll p;
302
303 /* Set the command operating upon the MAC address entries */
304 val = ATC_BUSY | ATC_MAT(0) | cmd;
305 mt7530_write(priv, MT7530_ATC, val);
306
307 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
308 ret = readx_poll_timeout(_mt7530_read, &p, val,
309 !(val & ATC_BUSY), 20, 20000);
310 if (ret < 0) {
311 dev_err(priv->dev, "reset timeout\n");
312 return ret;
313 }
314
315 /* Additional sanity for read command if the specified
316 * entry is invalid
317 */
318 val = mt7530_read(priv, MT7530_ATC);
319 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
320 return -EINVAL;
321
322 if (rsp)
323 *rsp = val;
324
325 return 0;
326 }
327
328 static void
mt7530_fdb_read(struct mt7530_priv * priv,struct mt7530_fdb * fdb)329 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
330 {
331 u32 reg[3];
332 int i;
333
334 /* Read from ARL table into an array */
335 for (i = 0; i < 3; i++) {
336 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
337
338 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
339 __func__, __LINE__, i, reg[i]);
340 }
341
342 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
343 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
344 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
345 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
346 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
347 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
348 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
349 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
350 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
351 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
352 }
353
354 static void
mt7530_fdb_write(struct mt7530_priv * priv,u16 vid,u8 port_mask,const u8 * mac,u8 aging,u8 type)355 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
356 u8 port_mask, const u8 *mac,
357 u8 aging, u8 type)
358 {
359 u32 reg[3] = { 0 };
360 int i;
361
362 reg[1] |= vid & CVID_MASK;
363 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
364 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
365 /* STATIC_ENT indicate that entry is static wouldn't
366 * be aged out and STATIC_EMP specified as erasing an
367 * entry
368 */
369 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
370 reg[1] |= mac[5] << MAC_BYTE_5;
371 reg[1] |= mac[4] << MAC_BYTE_4;
372 reg[0] |= mac[3] << MAC_BYTE_3;
373 reg[0] |= mac[2] << MAC_BYTE_2;
374 reg[0] |= mac[1] << MAC_BYTE_1;
375 reg[0] |= mac[0] << MAC_BYTE_0;
376
377 /* Write array into the ARL table */
378 for (i = 0; i < 3; i++)
379 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
380 }
381
382 /* Setup TX circuit including relevant PAD and driving */
383 static int
mt7530_pad_clk_setup(struct dsa_switch * ds,phy_interface_t interface)384 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
385 {
386 struct mt7530_priv *priv = ds->priv;
387 u32 ncpo1, ssc_delta, trgint, i, xtal;
388
389 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
390
391 if (xtal == HWTRAP_XTAL_20MHZ) {
392 dev_err(priv->dev,
393 "%s: MT7530 with a 20MHz XTAL is not supported!\n",
394 __func__);
395 return -EINVAL;
396 }
397
398 switch (interface) {
399 case PHY_INTERFACE_MODE_RGMII:
400 trgint = 0;
401 /* PLL frequency: 125MHz */
402 ncpo1 = 0x0c80;
403 break;
404 case PHY_INTERFACE_MODE_TRGMII:
405 trgint = 1;
406 if (priv->id == ID_MT7621) {
407 /* PLL frequency: 150MHz: 1.2GBit */
408 if (xtal == HWTRAP_XTAL_40MHZ)
409 ncpo1 = 0x0780;
410 if (xtal == HWTRAP_XTAL_25MHZ)
411 ncpo1 = 0x0a00;
412 } else { /* PLL frequency: 250MHz: 2.0Gbit */
413 if (xtal == HWTRAP_XTAL_40MHZ)
414 ncpo1 = 0x0c80;
415 if (xtal == HWTRAP_XTAL_25MHZ)
416 ncpo1 = 0x1400;
417 }
418 break;
419 default:
420 dev_err(priv->dev, "xMII interface %d not supported\n",
421 interface);
422 return -EINVAL;
423 }
424
425 if (xtal == HWTRAP_XTAL_25MHZ)
426 ssc_delta = 0x57;
427 else
428 ssc_delta = 0x87;
429
430 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
431 P6_INTF_MODE(trgint));
432
433 /* Lower Tx Driving for TRGMII path */
434 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
435 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
436 TD_DM_DRVP(8) | TD_DM_DRVN(8));
437
438 /* Setup core clock for MT7530 */
439 if (!trgint) {
440 /* Disable MT7530 core clock */
441 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
442
443 /* Disable PLL, since phy_device has not yet been created
444 * provided for phy_[read,write]_mmd_indirect is called, we
445 * provide our own core_write_mmd_indirect to complete this
446 * function.
447 */
448 core_write_mmd_indirect(priv,
449 CORE_GSWPLL_GRP1,
450 MDIO_MMD_VEND2,
451 0);
452
453 /* Set core clock into 500Mhz */
454 core_write(priv, CORE_GSWPLL_GRP2,
455 RG_GSWPLL_POSDIV_500M(1) |
456 RG_GSWPLL_FBKDIV_500M(25));
457
458 /* Enable PLL */
459 core_write(priv, CORE_GSWPLL_GRP1,
460 RG_GSWPLL_EN_PRE |
461 RG_GSWPLL_POSDIV_200M(2) |
462 RG_GSWPLL_FBKDIV_200M(32));
463
464 /* Enable MT7530 core clock */
465 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
466 }
467
468 /* Setup the MT7530 TRGMII Tx Clock */
469 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
470 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
471 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
472 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
473 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
474 core_write(priv, CORE_PLL_GROUP4,
475 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
476 RG_SYSPLL_BIAS_LPF_EN);
477 core_write(priv, CORE_PLL_GROUP2,
478 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
479 RG_SYSPLL_POSDIV(1));
480 core_write(priv, CORE_PLL_GROUP7,
481 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
482 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
483 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
484 REG_GSWCK_EN | REG_TRGMIICK_EN);
485
486 if (!trgint)
487 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
488 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
489 RD_TAP_MASK, RD_TAP(16));
490 return 0;
491 }
492
mt7531_dual_sgmii_supported(struct mt7530_priv * priv)493 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
494 {
495 u32 val;
496
497 val = mt7530_read(priv, MT7531_TOP_SIG_SR);
498
499 return (val & PAD_DUAL_SGMII_EN) != 0;
500 }
501
502 static int
mt7531_pad_setup(struct dsa_switch * ds,phy_interface_t interface)503 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
504 {
505 struct mt7530_priv *priv = ds->priv;
506 u32 top_sig;
507 u32 hwstrap;
508 u32 xtal;
509 u32 val;
510
511 if (mt7531_dual_sgmii_supported(priv))
512 return 0;
513
514 val = mt7530_read(priv, MT7531_CREV);
515 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
516 hwstrap = mt7530_read(priv, MT7531_HWTRAP);
517 if ((val & CHIP_REV_M) > 0)
518 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
519 HWTRAP_XTAL_FSEL_25MHZ;
520 else
521 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
522
523 /* Step 1 : Disable MT7531 COREPLL */
524 val = mt7530_read(priv, MT7531_PLLGP_EN);
525 val &= ~EN_COREPLL;
526 mt7530_write(priv, MT7531_PLLGP_EN, val);
527
528 /* Step 2: switch to XTAL output */
529 val = mt7530_read(priv, MT7531_PLLGP_EN);
530 val |= SW_CLKSW;
531 mt7530_write(priv, MT7531_PLLGP_EN, val);
532
533 val = mt7530_read(priv, MT7531_PLLGP_CR0);
534 val &= ~RG_COREPLL_EN;
535 mt7530_write(priv, MT7531_PLLGP_CR0, val);
536
537 /* Step 3: disable PLLGP and enable program PLLGP */
538 val = mt7530_read(priv, MT7531_PLLGP_EN);
539 val |= SW_PLLGP;
540 mt7530_write(priv, MT7531_PLLGP_EN, val);
541
542 /* Step 4: program COREPLL output frequency to 500MHz */
543 val = mt7530_read(priv, MT7531_PLLGP_CR0);
544 val &= ~RG_COREPLL_POSDIV_M;
545 val |= 2 << RG_COREPLL_POSDIV_S;
546 mt7530_write(priv, MT7531_PLLGP_CR0, val);
547 usleep_range(25, 35);
548
549 switch (xtal) {
550 case HWTRAP_XTAL_FSEL_25MHZ:
551 val = mt7530_read(priv, MT7531_PLLGP_CR0);
552 val &= ~RG_COREPLL_SDM_PCW_M;
553 val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
554 mt7530_write(priv, MT7531_PLLGP_CR0, val);
555 break;
556 case HWTRAP_XTAL_FSEL_40MHZ:
557 val = mt7530_read(priv, MT7531_PLLGP_CR0);
558 val &= ~RG_COREPLL_SDM_PCW_M;
559 val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
560 mt7530_write(priv, MT7531_PLLGP_CR0, val);
561 break;
562 };
563
564 /* Set feedback divide ratio update signal to high */
565 val = mt7530_read(priv, MT7531_PLLGP_CR0);
566 val |= RG_COREPLL_SDM_PCW_CHG;
567 mt7530_write(priv, MT7531_PLLGP_CR0, val);
568 /* Wait for at least 16 XTAL clocks */
569 usleep_range(10, 20);
570
571 /* Step 5: set feedback divide ratio update signal to low */
572 val = mt7530_read(priv, MT7531_PLLGP_CR0);
573 val &= ~RG_COREPLL_SDM_PCW_CHG;
574 mt7530_write(priv, MT7531_PLLGP_CR0, val);
575
576 /* Enable 325M clock for SGMII */
577 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
578
579 /* Enable 250SSC clock for RGMII */
580 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
581
582 /* Step 6: Enable MT7531 PLL */
583 val = mt7530_read(priv, MT7531_PLLGP_CR0);
584 val |= RG_COREPLL_EN;
585 mt7530_write(priv, MT7531_PLLGP_CR0, val);
586
587 val = mt7530_read(priv, MT7531_PLLGP_EN);
588 val |= EN_COREPLL;
589 mt7530_write(priv, MT7531_PLLGP_EN, val);
590 usleep_range(25, 35);
591
592 return 0;
593 }
594
595 static void
mt7530_mib_reset(struct dsa_switch * ds)596 mt7530_mib_reset(struct dsa_switch *ds)
597 {
598 struct mt7530_priv *priv = ds->priv;
599
600 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
601 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
602 }
603
mt7530_phy_read(struct dsa_switch * ds,int port,int regnum)604 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
605 {
606 struct mt7530_priv *priv = ds->priv;
607
608 return mdiobus_read_nested(priv->bus, port, regnum);
609 }
610
mt7530_phy_write(struct dsa_switch * ds,int port,int regnum,u16 val)611 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum,
612 u16 val)
613 {
614 struct mt7530_priv *priv = ds->priv;
615
616 return mdiobus_write_nested(priv->bus, port, regnum, val);
617 }
618
619 static int
mt7531_ind_c45_phy_read(struct mt7530_priv * priv,int port,int devad,int regnum)620 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
621 int regnum)
622 {
623 struct mii_bus *bus = priv->bus;
624 struct mt7530_dummy_poll p;
625 u32 reg, val;
626 int ret;
627
628 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
629
630 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
631
632 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
633 !(val & MT7531_PHY_ACS_ST), 20, 100000);
634 if (ret < 0) {
635 dev_err(priv->dev, "poll timeout\n");
636 goto out;
637 }
638
639 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
640 MT7531_MDIO_DEV_ADDR(devad) | regnum;
641 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
642
643 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
644 !(val & MT7531_PHY_ACS_ST), 20, 100000);
645 if (ret < 0) {
646 dev_err(priv->dev, "poll timeout\n");
647 goto out;
648 }
649
650 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) |
651 MT7531_MDIO_DEV_ADDR(devad);
652 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
653
654 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
655 !(val & MT7531_PHY_ACS_ST), 20, 100000);
656 if (ret < 0) {
657 dev_err(priv->dev, "poll timeout\n");
658 goto out;
659 }
660
661 ret = val & MT7531_MDIO_RW_DATA_MASK;
662 out:
663 mutex_unlock(&bus->mdio_lock);
664
665 return ret;
666 }
667
668 static int
mt7531_ind_c45_phy_write(struct mt7530_priv * priv,int port,int devad,int regnum,u32 data)669 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
670 int regnum, u32 data)
671 {
672 struct mii_bus *bus = priv->bus;
673 struct mt7530_dummy_poll p;
674 u32 val, reg;
675 int ret;
676
677 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
678
679 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
680
681 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
682 !(val & MT7531_PHY_ACS_ST), 20, 100000);
683 if (ret < 0) {
684 dev_err(priv->dev, "poll timeout\n");
685 goto out;
686 }
687
688 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
689 MT7531_MDIO_DEV_ADDR(devad) | regnum;
690 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
691
692 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
693 !(val & MT7531_PHY_ACS_ST), 20, 100000);
694 if (ret < 0) {
695 dev_err(priv->dev, "poll timeout\n");
696 goto out;
697 }
698
699 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) |
700 MT7531_MDIO_DEV_ADDR(devad) | data;
701 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
702
703 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
704 !(val & MT7531_PHY_ACS_ST), 20, 100000);
705 if (ret < 0) {
706 dev_err(priv->dev, "poll timeout\n");
707 goto out;
708 }
709
710 out:
711 mutex_unlock(&bus->mdio_lock);
712
713 return ret;
714 }
715
716 static int
mt7531_ind_c22_phy_read(struct mt7530_priv * priv,int port,int regnum)717 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
718 {
719 struct mii_bus *bus = priv->bus;
720 struct mt7530_dummy_poll p;
721 int ret;
722 u32 val;
723
724 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
725
726 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
727
728 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
729 !(val & MT7531_PHY_ACS_ST), 20, 100000);
730 if (ret < 0) {
731 dev_err(priv->dev, "poll timeout\n");
732 goto out;
733 }
734
735 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
736 MT7531_MDIO_REG_ADDR(regnum);
737
738 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
739
740 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
741 !(val & MT7531_PHY_ACS_ST), 20, 100000);
742 if (ret < 0) {
743 dev_err(priv->dev, "poll timeout\n");
744 goto out;
745 }
746
747 ret = val & MT7531_MDIO_RW_DATA_MASK;
748 out:
749 mutex_unlock(&bus->mdio_lock);
750
751 return ret;
752 }
753
754 static int
mt7531_ind_c22_phy_write(struct mt7530_priv * priv,int port,int regnum,u16 data)755 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
756 u16 data)
757 {
758 struct mii_bus *bus = priv->bus;
759 struct mt7530_dummy_poll p;
760 int ret;
761 u32 reg;
762
763 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
764
765 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
766
767 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
768 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
769 if (ret < 0) {
770 dev_err(priv->dev, "poll timeout\n");
771 goto out;
772 }
773
774 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) |
775 MT7531_MDIO_REG_ADDR(regnum) | data;
776
777 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
778
779 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
780 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
781 if (ret < 0) {
782 dev_err(priv->dev, "poll timeout\n");
783 goto out;
784 }
785
786 out:
787 mutex_unlock(&bus->mdio_lock);
788
789 return ret;
790 }
791
792 static int
mt7531_ind_phy_read(struct dsa_switch * ds,int port,int regnum)793 mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum)
794 {
795 struct mt7530_priv *priv = ds->priv;
796 int devad;
797 int ret;
798
799 if (regnum & MII_ADDR_C45) {
800 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
801 ret = mt7531_ind_c45_phy_read(priv, port, devad,
802 regnum & MII_REGADDR_C45_MASK);
803 } else {
804 ret = mt7531_ind_c22_phy_read(priv, port, regnum);
805 }
806
807 return ret;
808 }
809
810 static int
mt7531_ind_phy_write(struct dsa_switch * ds,int port,int regnum,u16 data)811 mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum,
812 u16 data)
813 {
814 struct mt7530_priv *priv = ds->priv;
815 int devad;
816 int ret;
817
818 if (regnum & MII_ADDR_C45) {
819 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
820 ret = mt7531_ind_c45_phy_write(priv, port, devad,
821 regnum & MII_REGADDR_C45_MASK,
822 data);
823 } else {
824 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data);
825 }
826
827 return ret;
828 }
829
830 static void
mt7530_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)831 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
832 uint8_t *data)
833 {
834 int i;
835
836 if (stringset != ETH_SS_STATS)
837 return;
838
839 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
840 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
841 ETH_GSTRING_LEN);
842 }
843
844 static void
mt7530_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)845 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
846 uint64_t *data)
847 {
848 struct mt7530_priv *priv = ds->priv;
849 const struct mt7530_mib_desc *mib;
850 u32 reg, i;
851 u64 hi;
852
853 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
854 mib = &mt7530_mib[i];
855 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
856
857 data[i] = mt7530_read(priv, reg);
858 if (mib->size == 2) {
859 hi = mt7530_read(priv, reg + 4);
860 data[i] |= hi << 32;
861 }
862 }
863 }
864
865 static int
mt7530_get_sset_count(struct dsa_switch * ds,int port,int sset)866 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
867 {
868 if (sset != ETH_SS_STATS)
869 return 0;
870
871 return ARRAY_SIZE(mt7530_mib);
872 }
873
mt7530_setup_port5(struct dsa_switch * ds,phy_interface_t interface)874 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
875 {
876 struct mt7530_priv *priv = ds->priv;
877 u8 tx_delay = 0;
878 int val;
879
880 mutex_lock(&priv->reg_mutex);
881
882 val = mt7530_read(priv, MT7530_MHWTRAP);
883
884 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
885 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
886
887 switch (priv->p5_intf_sel) {
888 case P5_INTF_SEL_PHY_P0:
889 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
890 val |= MHWTRAP_PHY0_SEL;
891 fallthrough;
892 case P5_INTF_SEL_PHY_P4:
893 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
894 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
895
896 /* Setup the MAC by default for the cpu port */
897 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
898 break;
899 case P5_INTF_SEL_GMAC5:
900 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
901 val &= ~MHWTRAP_P5_DIS;
902 break;
903 case P5_DISABLED:
904 interface = PHY_INTERFACE_MODE_NA;
905 break;
906 default:
907 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
908 priv->p5_intf_sel);
909 goto unlock_exit;
910 }
911
912 /* Setup RGMII settings */
913 if (phy_interface_mode_is_rgmii(interface)) {
914 val |= MHWTRAP_P5_RGMII_MODE;
915
916 /* P5 RGMII RX Clock Control: delay setting for 1000M */
917 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
918
919 /* Don't set delay in DSA mode */
920 if (!dsa_is_dsa_port(priv->ds, 5) &&
921 (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
922 interface == PHY_INTERFACE_MODE_RGMII_ID))
923 tx_delay = 4; /* n * 0.5 ns */
924
925 /* P5 RGMII TX Clock Control: delay x */
926 mt7530_write(priv, MT7530_P5RGMIITXCR,
927 CSR_RGMII_TXC_CFG(0x10 + tx_delay));
928
929 /* reduce P5 RGMII Tx driving, 8mA */
930 mt7530_write(priv, MT7530_IO_DRV_CR,
931 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
932 }
933
934 mt7530_write(priv, MT7530_MHWTRAP, val);
935
936 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
937 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
938
939 priv->p5_interface = interface;
940
941 unlock_exit:
942 mutex_unlock(&priv->reg_mutex);
943 }
944
945 static int
mt753x_cpu_port_enable(struct dsa_switch * ds,int port)946 mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
947 {
948 struct mt7530_priv *priv = ds->priv;
949 int ret;
950
951 /* Setup max capability of CPU port at first */
952 if (priv->info->cpu_port_config) {
953 ret = priv->info->cpu_port_config(ds, port);
954 if (ret)
955 return ret;
956 }
957
958 /* Enable Mediatek header mode on the cpu port */
959 mt7530_write(priv, MT7530_PVC_P(port),
960 PORT_SPEC_TAG);
961
962 /* Unknown multicast frame forwarding to the cpu port */
963 mt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port)));
964
965 /* Set CPU port number */
966 if (priv->id == ID_MT7621)
967 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
968
969 /* CPU port gets connected to all user ports of
970 * the switch.
971 */
972 mt7530_write(priv, MT7530_PCR_P(port),
973 PCR_MATRIX(dsa_user_ports(priv->ds)));
974
975 return 0;
976 }
977
978 static int
mt7530_port_enable(struct dsa_switch * ds,int port,struct phy_device * phy)979 mt7530_port_enable(struct dsa_switch *ds, int port,
980 struct phy_device *phy)
981 {
982 struct mt7530_priv *priv = ds->priv;
983
984 mutex_lock(&priv->reg_mutex);
985
986 /* Allow the user port gets connected to the cpu port and also
987 * restore the port matrix if the port is the member of a certain
988 * bridge.
989 */
990 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
991 priv->ports[port].enable = true;
992 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
993 priv->ports[port].pm);
994 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
995
996 mutex_unlock(&priv->reg_mutex);
997
998 return 0;
999 }
1000
1001 static void
mt7530_port_disable(struct dsa_switch * ds,int port)1002 mt7530_port_disable(struct dsa_switch *ds, int port)
1003 {
1004 struct mt7530_priv *priv = ds->priv;
1005
1006 mutex_lock(&priv->reg_mutex);
1007
1008 /* Clear up all port matrix which could be restored in the next
1009 * enablement for the port.
1010 */
1011 priv->ports[port].enable = false;
1012 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1013 PCR_MATRIX_CLR);
1014 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
1015
1016 mutex_unlock(&priv->reg_mutex);
1017 }
1018
1019 static void
mt7530_stp_state_set(struct dsa_switch * ds,int port,u8 state)1020 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1021 {
1022 struct mt7530_priv *priv = ds->priv;
1023 u32 stp_state;
1024
1025 switch (state) {
1026 case BR_STATE_DISABLED:
1027 stp_state = MT7530_STP_DISABLED;
1028 break;
1029 case BR_STATE_BLOCKING:
1030 stp_state = MT7530_STP_BLOCKING;
1031 break;
1032 case BR_STATE_LISTENING:
1033 stp_state = MT7530_STP_LISTENING;
1034 break;
1035 case BR_STATE_LEARNING:
1036 stp_state = MT7530_STP_LEARNING;
1037 break;
1038 case BR_STATE_FORWARDING:
1039 default:
1040 stp_state = MT7530_STP_FORWARDING;
1041 break;
1042 }
1043
1044 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
1045 }
1046
1047 static int
mt7530_port_bridge_join(struct dsa_switch * ds,int port,struct net_device * bridge)1048 mt7530_port_bridge_join(struct dsa_switch *ds, int port,
1049 struct net_device *bridge)
1050 {
1051 struct mt7530_priv *priv = ds->priv;
1052 u32 port_bitmap = BIT(MT7530_CPU_PORT);
1053 int i;
1054
1055 mutex_lock(&priv->reg_mutex);
1056
1057 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1058 /* Add this port to the port matrix of the other ports in the
1059 * same bridge. If the port is disabled, port matrix is kept
1060 * and not being setup until the port becomes enabled.
1061 */
1062 if (dsa_is_user_port(ds, i) && i != port) {
1063 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1064 continue;
1065 if (priv->ports[i].enable)
1066 mt7530_set(priv, MT7530_PCR_P(i),
1067 PCR_MATRIX(BIT(port)));
1068 priv->ports[i].pm |= PCR_MATRIX(BIT(port));
1069
1070 port_bitmap |= BIT(i);
1071 }
1072 }
1073
1074 /* Add the all other ports to this port matrix. */
1075 if (priv->ports[port].enable)
1076 mt7530_rmw(priv, MT7530_PCR_P(port),
1077 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
1078 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
1079
1080 mutex_unlock(&priv->reg_mutex);
1081
1082 return 0;
1083 }
1084
1085 static void
mt7530_port_set_vlan_unaware(struct dsa_switch * ds,int port)1086 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
1087 {
1088 struct mt7530_priv *priv = ds->priv;
1089 bool all_user_ports_removed = true;
1090 int i;
1091
1092 /* When a port is removed from the bridge, the port would be set up
1093 * back to the default as is at initial boot which is a VLAN-unaware
1094 * port.
1095 */
1096 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1097 MT7530_PORT_MATRIX_MODE);
1098 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1099 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
1100 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1101
1102 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1103 if (dsa_is_user_port(ds, i) &&
1104 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
1105 all_user_ports_removed = false;
1106 break;
1107 }
1108 }
1109
1110 /* CPU port also does the same thing until all user ports belonging to
1111 * the CPU port get out of VLAN filtering mode.
1112 */
1113 if (all_user_ports_removed) {
1114 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
1115 PCR_MATRIX(dsa_user_ports(priv->ds)));
1116 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG
1117 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1118 }
1119 }
1120
1121 static void
mt7530_port_set_vlan_aware(struct dsa_switch * ds,int port)1122 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
1123 {
1124 struct mt7530_priv *priv = ds->priv;
1125
1126 /* Trapped into security mode allows packet forwarding through VLAN
1127 * table lookup. CPU port is set to fallback mode to let untagged
1128 * frames pass through.
1129 */
1130 if (dsa_is_cpu_port(ds, port))
1131 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1132 MT7530_PORT_FALLBACK_MODE);
1133 else
1134 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1135 MT7530_PORT_SECURITY_MODE);
1136
1137 /* Set the port as a user port which is to be able to recognize VID
1138 * from incoming packets before fetching entry within the VLAN table.
1139 */
1140 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1141 VLAN_ATTR(MT7530_VLAN_USER) |
1142 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
1143 }
1144
1145 static void
mt7530_port_bridge_leave(struct dsa_switch * ds,int port,struct net_device * bridge)1146 mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
1147 struct net_device *bridge)
1148 {
1149 struct mt7530_priv *priv = ds->priv;
1150 int i;
1151
1152 mutex_lock(&priv->reg_mutex);
1153
1154 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1155 /* Remove this port from the port matrix of the other ports
1156 * in the same bridge. If the port is disabled, port matrix
1157 * is kept and not being setup until the port becomes enabled.
1158 */
1159 if (dsa_is_user_port(ds, i) && i != port) {
1160 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1161 continue;
1162 if (priv->ports[i].enable)
1163 mt7530_clear(priv, MT7530_PCR_P(i),
1164 PCR_MATRIX(BIT(port)));
1165 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
1166 }
1167 }
1168
1169 /* Set the cpu port to be the only one in the port matrix of
1170 * this port.
1171 */
1172 if (priv->ports[port].enable)
1173 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1174 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
1175 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
1176
1177 mutex_unlock(&priv->reg_mutex);
1178 }
1179
1180 static int
mt7530_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid)1181 mt7530_port_fdb_add(struct dsa_switch *ds, int port,
1182 const unsigned char *addr, u16 vid)
1183 {
1184 struct mt7530_priv *priv = ds->priv;
1185 int ret;
1186 u8 port_mask = BIT(port);
1187
1188 mutex_lock(&priv->reg_mutex);
1189 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
1190 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1191 mutex_unlock(&priv->reg_mutex);
1192
1193 return ret;
1194 }
1195
1196 static int
mt7530_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid)1197 mt7530_port_fdb_del(struct dsa_switch *ds, int port,
1198 const unsigned char *addr, u16 vid)
1199 {
1200 struct mt7530_priv *priv = ds->priv;
1201 int ret;
1202 u8 port_mask = BIT(port);
1203
1204 mutex_lock(&priv->reg_mutex);
1205 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
1206 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1207 mutex_unlock(&priv->reg_mutex);
1208
1209 return ret;
1210 }
1211
1212 static int
mt7530_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)1213 mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
1214 dsa_fdb_dump_cb_t *cb, void *data)
1215 {
1216 struct mt7530_priv *priv = ds->priv;
1217 struct mt7530_fdb _fdb = { 0 };
1218 int cnt = MT7530_NUM_FDB_RECORDS;
1219 int ret = 0;
1220 u32 rsp = 0;
1221
1222 mutex_lock(&priv->reg_mutex);
1223
1224 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
1225 if (ret < 0)
1226 goto err;
1227
1228 do {
1229 if (rsp & ATC_SRCH_HIT) {
1230 mt7530_fdb_read(priv, &_fdb);
1231 if (_fdb.port_mask & BIT(port)) {
1232 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
1233 data);
1234 if (ret < 0)
1235 break;
1236 }
1237 }
1238 } while (--cnt &&
1239 !(rsp & ATC_SRCH_END) &&
1240 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
1241 err:
1242 mutex_unlock(&priv->reg_mutex);
1243
1244 return 0;
1245 }
1246
1247 static int
mt7530_vlan_cmd(struct mt7530_priv * priv,enum mt7530_vlan_cmd cmd,u16 vid)1248 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
1249 {
1250 struct mt7530_dummy_poll p;
1251 u32 val;
1252 int ret;
1253
1254 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
1255 mt7530_write(priv, MT7530_VTCR, val);
1256
1257 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
1258 ret = readx_poll_timeout(_mt7530_read, &p, val,
1259 !(val & VTCR_BUSY), 20, 20000);
1260 if (ret < 0) {
1261 dev_err(priv->dev, "poll timeout\n");
1262 return ret;
1263 }
1264
1265 val = mt7530_read(priv, MT7530_VTCR);
1266 if (val & VTCR_INVALID) {
1267 dev_err(priv->dev, "read VTCR invalid\n");
1268 return -EINVAL;
1269 }
1270
1271 return 0;
1272 }
1273
1274 static int
mt7530_port_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct switchdev_trans * trans)1275 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port,
1276 bool vlan_filtering,
1277 struct switchdev_trans *trans)
1278 {
1279 if (switchdev_trans_ph_prepare(trans))
1280 return 0;
1281
1282 if (vlan_filtering) {
1283 /* The port is being kept as VLAN-unaware port when bridge is
1284 * set up with vlan_filtering not being set, Otherwise, the
1285 * port and the corresponding CPU port is required the setup
1286 * for becoming a VLAN-aware port.
1287 */
1288 mt7530_port_set_vlan_aware(ds, port);
1289 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
1290 } else {
1291 mt7530_port_set_vlan_unaware(ds, port);
1292 }
1293
1294 return 0;
1295 }
1296
1297 static int
mt7530_port_vlan_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1298 mt7530_port_vlan_prepare(struct dsa_switch *ds, int port,
1299 const struct switchdev_obj_port_vlan *vlan)
1300 {
1301 /* nothing needed */
1302
1303 return 0;
1304 }
1305
1306 static void
mt7530_hw_vlan_add(struct mt7530_priv * priv,struct mt7530_hw_vlan_entry * entry)1307 mt7530_hw_vlan_add(struct mt7530_priv *priv,
1308 struct mt7530_hw_vlan_entry *entry)
1309 {
1310 u8 new_members;
1311 u32 val;
1312
1313 new_members = entry->old_members | BIT(entry->port) |
1314 BIT(MT7530_CPU_PORT);
1315
1316 /* Validate the entry with independent learning, create egress tag per
1317 * VLAN and joining the port as one of the port members.
1318 */
1319 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
1320 mt7530_write(priv, MT7530_VAWD1, val);
1321
1322 /* Decide whether adding tag or not for those outgoing packets from the
1323 * port inside the VLAN.
1324 */
1325 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1326 MT7530_VLAN_EGRESS_TAG;
1327 mt7530_rmw(priv, MT7530_VAWD2,
1328 ETAG_CTRL_P_MASK(entry->port),
1329 ETAG_CTRL_P(entry->port, val));
1330
1331 /* CPU port is always taken as a tagged port for serving more than one
1332 * VLANs across and also being applied with egress type stack mode for
1333 * that VLAN tags would be appended after hardware special tag used as
1334 * DSA tag.
1335 */
1336 mt7530_rmw(priv, MT7530_VAWD2,
1337 ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
1338 ETAG_CTRL_P(MT7530_CPU_PORT,
1339 MT7530_VLAN_EGRESS_STACK));
1340 }
1341
1342 static void
mt7530_hw_vlan_del(struct mt7530_priv * priv,struct mt7530_hw_vlan_entry * entry)1343 mt7530_hw_vlan_del(struct mt7530_priv *priv,
1344 struct mt7530_hw_vlan_entry *entry)
1345 {
1346 u8 new_members;
1347 u32 val;
1348
1349 new_members = entry->old_members & ~BIT(entry->port);
1350
1351 val = mt7530_read(priv, MT7530_VAWD1);
1352 if (!(val & VLAN_VALID)) {
1353 dev_err(priv->dev,
1354 "Cannot be deleted due to invalid entry\n");
1355 return;
1356 }
1357
1358 /* If certain member apart from CPU port is still alive in the VLAN,
1359 * the entry would be kept valid. Otherwise, the entry is got to be
1360 * disabled.
1361 */
1362 if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
1363 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1364 VLAN_VALID;
1365 mt7530_write(priv, MT7530_VAWD1, val);
1366 } else {
1367 mt7530_write(priv, MT7530_VAWD1, 0);
1368 mt7530_write(priv, MT7530_VAWD2, 0);
1369 }
1370 }
1371
1372 static void
mt7530_hw_vlan_update(struct mt7530_priv * priv,u16 vid,struct mt7530_hw_vlan_entry * entry,mt7530_vlan_op vlan_op)1373 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1374 struct mt7530_hw_vlan_entry *entry,
1375 mt7530_vlan_op vlan_op)
1376 {
1377 u32 val;
1378
1379 /* Fetch entry */
1380 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1381
1382 val = mt7530_read(priv, MT7530_VAWD1);
1383
1384 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1385
1386 /* Manipulate entry */
1387 vlan_op(priv, entry);
1388
1389 /* Flush result to hardware */
1390 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1391 }
1392
1393 static void
mt7530_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1394 mt7530_port_vlan_add(struct dsa_switch *ds, int port,
1395 const struct switchdev_obj_port_vlan *vlan)
1396 {
1397 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1398 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1399 struct mt7530_hw_vlan_entry new_entry;
1400 struct mt7530_priv *priv = ds->priv;
1401 u16 vid;
1402
1403 mutex_lock(&priv->reg_mutex);
1404
1405 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1406 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1407 mt7530_hw_vlan_update(priv, vid, &new_entry,
1408 mt7530_hw_vlan_add);
1409 }
1410
1411 if (pvid) {
1412 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1413 G0_PORT_VID(vlan->vid_end));
1414 priv->ports[port].pvid = vlan->vid_end;
1415 }
1416
1417 mutex_unlock(&priv->reg_mutex);
1418 }
1419
1420 static int
mt7530_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1421 mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1422 const struct switchdev_obj_port_vlan *vlan)
1423 {
1424 struct mt7530_hw_vlan_entry target_entry;
1425 struct mt7530_priv *priv = ds->priv;
1426 u16 vid, pvid;
1427
1428 mutex_lock(&priv->reg_mutex);
1429
1430 pvid = priv->ports[port].pvid;
1431 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1432 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1433 mt7530_hw_vlan_update(priv, vid, &target_entry,
1434 mt7530_hw_vlan_del);
1435
1436 /* PVID is being restored to the default whenever the PVID port
1437 * is being removed from the VLAN.
1438 */
1439 if (pvid == vid)
1440 pvid = G0_PORT_VID_DEF;
1441 }
1442
1443 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
1444 priv->ports[port].pvid = pvid;
1445
1446 mutex_unlock(&priv->reg_mutex);
1447
1448 return 0;
1449 }
1450
mt753x_mirror_port_get(unsigned int id,u32 val)1451 static int mt753x_mirror_port_get(unsigned int id, u32 val)
1452 {
1453 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
1454 MIRROR_PORT(val);
1455 }
1456
mt753x_mirror_port_set(unsigned int id,u32 val)1457 static int mt753x_mirror_port_set(unsigned int id, u32 val)
1458 {
1459 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
1460 MIRROR_PORT(val);
1461 }
1462
mt753x_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress)1463 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
1464 struct dsa_mall_mirror_tc_entry *mirror,
1465 bool ingress)
1466 {
1467 struct mt7530_priv *priv = ds->priv;
1468 int monitor_port;
1469 u32 val;
1470
1471 /* Check for existent entry */
1472 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
1473 return -EEXIST;
1474
1475 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1476
1477 /* MT7530 only supports one monitor port */
1478 monitor_port = mt753x_mirror_port_get(priv->id, val);
1479 if (val & MT753X_MIRROR_EN(priv->id) &&
1480 monitor_port != mirror->to_local_port)
1481 return -EEXIST;
1482
1483 val |= MT753X_MIRROR_EN(priv->id);
1484 val &= ~MT753X_MIRROR_MASK(priv->id);
1485 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
1486 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
1487
1488 val = mt7530_read(priv, MT7530_PCR_P(port));
1489 if (ingress) {
1490 val |= PORT_RX_MIR;
1491 priv->mirror_rx |= BIT(port);
1492 } else {
1493 val |= PORT_TX_MIR;
1494 priv->mirror_tx |= BIT(port);
1495 }
1496 mt7530_write(priv, MT7530_PCR_P(port), val);
1497
1498 return 0;
1499 }
1500
mt753x_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)1501 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
1502 struct dsa_mall_mirror_tc_entry *mirror)
1503 {
1504 struct mt7530_priv *priv = ds->priv;
1505 u32 val;
1506
1507 val = mt7530_read(priv, MT7530_PCR_P(port));
1508 if (mirror->ingress) {
1509 val &= ~PORT_RX_MIR;
1510 priv->mirror_rx &= ~BIT(port);
1511 } else {
1512 val &= ~PORT_TX_MIR;
1513 priv->mirror_tx &= ~BIT(port);
1514 }
1515 mt7530_write(priv, MT7530_PCR_P(port), val);
1516
1517 if (!priv->mirror_rx && !priv->mirror_tx) {
1518 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1519 val &= ~MT753X_MIRROR_EN(priv->id);
1520 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
1521 }
1522 }
1523
1524 static enum dsa_tag_protocol
mtk_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)1525 mtk_get_tag_protocol(struct dsa_switch *ds, int port,
1526 enum dsa_tag_protocol mp)
1527 {
1528 struct mt7530_priv *priv = ds->priv;
1529
1530 if (port != MT7530_CPU_PORT) {
1531 dev_warn(priv->dev,
1532 "port not matched with tagging CPU port\n");
1533 return DSA_TAG_PROTO_NONE;
1534 } else {
1535 return DSA_TAG_PROTO_MTK;
1536 }
1537 }
1538
1539 static int
mt7530_setup(struct dsa_switch * ds)1540 mt7530_setup(struct dsa_switch *ds)
1541 {
1542 struct mt7530_priv *priv = ds->priv;
1543 struct device_node *phy_node;
1544 struct device_node *mac_np;
1545 struct mt7530_dummy_poll p;
1546 phy_interface_t interface;
1547 struct device_node *dn;
1548 u32 id, val;
1549 int ret, i;
1550
1551 /* The parent node of master netdev which holds the common system
1552 * controller also is the container for two GMACs nodes representing
1553 * as two netdev instances.
1554 */
1555 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
1556 ds->configure_vlan_while_not_filtering = true;
1557
1558 if (priv->id == ID_MT7530) {
1559 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
1560 ret = regulator_enable(priv->core_pwr);
1561 if (ret < 0) {
1562 dev_err(priv->dev,
1563 "Failed to enable core power: %d\n", ret);
1564 return ret;
1565 }
1566
1567 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
1568 ret = regulator_enable(priv->io_pwr);
1569 if (ret < 0) {
1570 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
1571 ret);
1572 return ret;
1573 }
1574 }
1575
1576 /* Reset whole chip through gpio pin or memory-mapped registers for
1577 * different type of hardware
1578 */
1579 if (priv->mcm) {
1580 reset_control_assert(priv->rstc);
1581 usleep_range(1000, 1100);
1582 reset_control_deassert(priv->rstc);
1583 } else {
1584 gpiod_set_value_cansleep(priv->reset, 0);
1585 usleep_range(1000, 1100);
1586 gpiod_set_value_cansleep(priv->reset, 1);
1587 }
1588
1589 /* Waiting for MT7530 got to stable */
1590 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1591 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1592 20, 1000000);
1593 if (ret < 0) {
1594 dev_err(priv->dev, "reset timeout\n");
1595 return ret;
1596 }
1597
1598 id = mt7530_read(priv, MT7530_CREV);
1599 id >>= CHIP_NAME_SHIFT;
1600 if (id != MT7530_ID) {
1601 dev_err(priv->dev, "chip %x can't be supported\n", id);
1602 return -ENODEV;
1603 }
1604
1605 /* Reset the switch through internal reset */
1606 mt7530_write(priv, MT7530_SYS_CTRL,
1607 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1608 SYS_CTRL_REG_RST);
1609
1610 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
1611 val = mt7530_read(priv, MT7530_MHWTRAP);
1612 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
1613 val |= MHWTRAP_MANUAL;
1614 mt7530_write(priv, MT7530_MHWTRAP, val);
1615
1616 priv->p6_interface = PHY_INTERFACE_MODE_NA;
1617
1618 /* Enable and reset MIB counters */
1619 mt7530_mib_reset(ds);
1620
1621 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1622 /* Disable forwarding by default on all ports */
1623 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1624 PCR_MATRIX_CLR);
1625
1626 if (dsa_is_cpu_port(ds, i)) {
1627 ret = mt753x_cpu_port_enable(ds, i);
1628 if (ret)
1629 return ret;
1630 } else
1631 mt7530_port_disable(ds, i);
1632
1633 /* Enable consistent egress tag */
1634 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
1635 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1636 }
1637
1638 /* Setup port 5 */
1639 priv->p5_intf_sel = P5_DISABLED;
1640 interface = PHY_INTERFACE_MODE_NA;
1641
1642 if (!dsa_is_unused_port(ds, 5)) {
1643 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
1644 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
1645 if (ret && ret != -ENODEV)
1646 return ret;
1647 } else {
1648 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
1649 for_each_child_of_node(dn, mac_np) {
1650 if (!of_device_is_compatible(mac_np,
1651 "mediatek,eth-mac"))
1652 continue;
1653
1654 ret = of_property_read_u32(mac_np, "reg", &id);
1655 if (ret < 0 || id != 1)
1656 continue;
1657
1658 phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
1659 if (!phy_node)
1660 continue;
1661
1662 if (phy_node->parent == priv->dev->of_node->parent) {
1663 ret = of_get_phy_mode(mac_np, &interface);
1664 if (ret && ret != -ENODEV) {
1665 of_node_put(mac_np);
1666 return ret;
1667 }
1668 id = of_mdio_parse_addr(ds->dev, phy_node);
1669 if (id == 0)
1670 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
1671 if (id == 4)
1672 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
1673 }
1674 of_node_put(mac_np);
1675 of_node_put(phy_node);
1676 break;
1677 }
1678 }
1679
1680 mt7530_setup_port5(ds, interface);
1681
1682 /* Flush the FDB table */
1683 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
1684 if (ret < 0)
1685 return ret;
1686
1687 return 0;
1688 }
1689
1690 static int
mt7531_setup(struct dsa_switch * ds)1691 mt7531_setup(struct dsa_switch *ds)
1692 {
1693 struct mt7530_priv *priv = ds->priv;
1694 struct mt7530_dummy_poll p;
1695 u32 val, id;
1696 int ret, i;
1697
1698 /* Reset whole chip through gpio pin or memory-mapped registers for
1699 * different type of hardware
1700 */
1701 if (priv->mcm) {
1702 reset_control_assert(priv->rstc);
1703 usleep_range(1000, 1100);
1704 reset_control_deassert(priv->rstc);
1705 } else {
1706 gpiod_set_value_cansleep(priv->reset, 0);
1707 usleep_range(1000, 1100);
1708 gpiod_set_value_cansleep(priv->reset, 1);
1709 }
1710
1711 /* Waiting for MT7530 got to stable */
1712 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1713 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1714 20, 1000000);
1715 if (ret < 0) {
1716 dev_err(priv->dev, "reset timeout\n");
1717 return ret;
1718 }
1719
1720 id = mt7530_read(priv, MT7531_CREV);
1721 id >>= CHIP_NAME_SHIFT;
1722
1723 if (id != MT7531_ID) {
1724 dev_err(priv->dev, "chip %x can't be supported\n", id);
1725 return -ENODEV;
1726 }
1727
1728 /* Reset the switch through internal reset */
1729 mt7530_write(priv, MT7530_SYS_CTRL,
1730 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1731 SYS_CTRL_REG_RST);
1732
1733 if (mt7531_dual_sgmii_supported(priv)) {
1734 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
1735
1736 /* Let ds->slave_mii_bus be able to access external phy. */
1737 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
1738 MT7531_EXT_P_MDC_11);
1739 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
1740 MT7531_EXT_P_MDIO_12);
1741 } else {
1742 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
1743 }
1744 dev_dbg(ds->dev, "P5 support %s interface\n",
1745 p5_intf_modes(priv->p5_intf_sel));
1746
1747 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
1748 MT7531_GPIO0_INTERRUPT);
1749
1750 /* Let phylink decide the interface later. */
1751 priv->p5_interface = PHY_INTERFACE_MODE_NA;
1752 priv->p6_interface = PHY_INTERFACE_MODE_NA;
1753
1754 /* Enable PHY core PLL, since phy_device has not yet been created
1755 * provided for phy_[read,write]_mmd_indirect is called, we provide
1756 * our own mt7531_ind_mmd_phy_[read,write] to complete this
1757 * function.
1758 */
1759 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
1760 MDIO_MMD_VEND2, CORE_PLL_GROUP4);
1761 val |= MT7531_PHY_PLL_BYPASS_MODE;
1762 val &= ~MT7531_PHY_PLL_OFF;
1763 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
1764 CORE_PLL_GROUP4, val);
1765
1766 /* BPDU to CPU port */
1767 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
1768 BIT(MT7530_CPU_PORT));
1769 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
1770 MT753X_BPDU_CPU_ONLY);
1771
1772 /* Enable and reset MIB counters */
1773 mt7530_mib_reset(ds);
1774
1775 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1776 /* Disable forwarding by default on all ports */
1777 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1778 PCR_MATRIX_CLR);
1779
1780 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
1781
1782 if (dsa_is_cpu_port(ds, i)) {
1783 ret = mt753x_cpu_port_enable(ds, i);
1784 if (ret)
1785 return ret;
1786 } else
1787 mt7530_port_disable(ds, i);
1788
1789 /* Enable consistent egress tag */
1790 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
1791 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1792 }
1793
1794 ds->configure_vlan_while_not_filtering = true;
1795
1796 /* Flush the FDB table */
1797 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
1798 if (ret < 0)
1799 return ret;
1800
1801 return 0;
1802 }
1803
1804 static bool
mt7530_phy_mode_supported(struct dsa_switch * ds,int port,const struct phylink_link_state * state)1805 mt7530_phy_mode_supported(struct dsa_switch *ds, int port,
1806 const struct phylink_link_state *state)
1807 {
1808 struct mt7530_priv *priv = ds->priv;
1809
1810 switch (port) {
1811 case 0 ... 4: /* Internal phy */
1812 if (state->interface != PHY_INTERFACE_MODE_GMII)
1813 return false;
1814 break;
1815 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
1816 if (!phy_interface_mode_is_rgmii(state->interface) &&
1817 state->interface != PHY_INTERFACE_MODE_MII &&
1818 state->interface != PHY_INTERFACE_MODE_GMII)
1819 return false;
1820 break;
1821 case 6: /* 1st cpu port */
1822 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1823 state->interface != PHY_INTERFACE_MODE_TRGMII)
1824 return false;
1825 break;
1826 default:
1827 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
1828 port);
1829 return false;
1830 }
1831
1832 return true;
1833 }
1834
mt7531_is_rgmii_port(struct mt7530_priv * priv,u32 port)1835 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
1836 {
1837 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
1838 }
1839
1840 static bool
mt7531_phy_mode_supported(struct dsa_switch * ds,int port,const struct phylink_link_state * state)1841 mt7531_phy_mode_supported(struct dsa_switch *ds, int port,
1842 const struct phylink_link_state *state)
1843 {
1844 struct mt7530_priv *priv = ds->priv;
1845
1846 switch (port) {
1847 case 0 ... 4: /* Internal phy */
1848 if (state->interface != PHY_INTERFACE_MODE_GMII)
1849 return false;
1850 break;
1851 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
1852 if (mt7531_is_rgmii_port(priv, port))
1853 return phy_interface_mode_is_rgmii(state->interface);
1854 fallthrough;
1855 case 6: /* 1st cpu port supports sgmii/8023z only */
1856 if (state->interface != PHY_INTERFACE_MODE_SGMII &&
1857 !phy_interface_mode_is_8023z(state->interface))
1858 return false;
1859 break;
1860 default:
1861 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
1862 port);
1863 return false;
1864 }
1865
1866 return true;
1867 }
1868
1869 static bool
mt753x_phy_mode_supported(struct dsa_switch * ds,int port,const struct phylink_link_state * state)1870 mt753x_phy_mode_supported(struct dsa_switch *ds, int port,
1871 const struct phylink_link_state *state)
1872 {
1873 struct mt7530_priv *priv = ds->priv;
1874
1875 return priv->info->phy_mode_supported(ds, port, state);
1876 }
1877
1878 static int
mt753x_pad_setup(struct dsa_switch * ds,const struct phylink_link_state * state)1879 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
1880 {
1881 struct mt7530_priv *priv = ds->priv;
1882
1883 return priv->info->pad_setup(ds, state->interface);
1884 }
1885
1886 static int
mt7530_mac_config(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)1887 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
1888 phy_interface_t interface)
1889 {
1890 struct mt7530_priv *priv = ds->priv;
1891
1892 /* Only need to setup port5. */
1893 if (port != 5)
1894 return 0;
1895
1896 mt7530_setup_port5(priv->ds, interface);
1897
1898 return 0;
1899 }
1900
mt7531_rgmii_setup(struct mt7530_priv * priv,u32 port,phy_interface_t interface,struct phy_device * phydev)1901 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
1902 phy_interface_t interface,
1903 struct phy_device *phydev)
1904 {
1905 u32 val;
1906
1907 if (!mt7531_is_rgmii_port(priv, port)) {
1908 dev_err(priv->dev, "RGMII mode is not available for port %d\n",
1909 port);
1910 return -EINVAL;
1911 }
1912
1913 val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
1914 val |= GP_CLK_EN;
1915 val &= ~GP_MODE_MASK;
1916 val |= GP_MODE(MT7531_GP_MODE_RGMII);
1917 val &= ~CLK_SKEW_IN_MASK;
1918 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
1919 val &= ~CLK_SKEW_OUT_MASK;
1920 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
1921 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY;
1922
1923 /* Do not adjust rgmii delay when vendor phy driver presents. */
1924 if (!phydev || phy_driver_is_genphy(phydev)) {
1925 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY);
1926 switch (interface) {
1927 case PHY_INTERFACE_MODE_RGMII:
1928 val |= TXCLK_NO_REVERSE;
1929 val |= RXCLK_NO_DELAY;
1930 break;
1931 case PHY_INTERFACE_MODE_RGMII_RXID:
1932 val |= TXCLK_NO_REVERSE;
1933 break;
1934 case PHY_INTERFACE_MODE_RGMII_TXID:
1935 val |= RXCLK_NO_DELAY;
1936 break;
1937 case PHY_INTERFACE_MODE_RGMII_ID:
1938 break;
1939 default:
1940 return -EINVAL;
1941 }
1942 }
1943 mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
1944
1945 return 0;
1946 }
1947
mt7531_sgmii_validate(struct mt7530_priv * priv,int port,unsigned long * supported)1948 static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port,
1949 unsigned long *supported)
1950 {
1951 /* Port5 supports ethier RGMII or SGMII.
1952 * Port6 supports SGMII only.
1953 */
1954 switch (port) {
1955 case 5:
1956 if (mt7531_is_rgmii_port(priv, port))
1957 break;
1958 fallthrough;
1959 case 6:
1960 phylink_set(supported, 1000baseX_Full);
1961 phylink_set(supported, 2500baseX_Full);
1962 phylink_set(supported, 2500baseT_Full);
1963 }
1964 }
1965
1966 static void
mt7531_sgmii_link_up_force(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,int speed,int duplex)1967 mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port,
1968 unsigned int mode, phy_interface_t interface,
1969 int speed, int duplex)
1970 {
1971 struct mt7530_priv *priv = ds->priv;
1972 unsigned int val;
1973
1974 /* For adjusting speed and duplex of SGMII force mode. */
1975 if (interface != PHY_INTERFACE_MODE_SGMII ||
1976 phylink_autoneg_inband(mode))
1977 return;
1978
1979 /* SGMII force mode setting */
1980 val = mt7530_read(priv, MT7531_SGMII_MODE(port));
1981 val &= ~MT7531_SGMII_IF_MODE_MASK;
1982
1983 switch (speed) {
1984 case SPEED_10:
1985 val |= MT7531_SGMII_FORCE_SPEED_10;
1986 break;
1987 case SPEED_100:
1988 val |= MT7531_SGMII_FORCE_SPEED_100;
1989 break;
1990 case SPEED_1000:
1991 val |= MT7531_SGMII_FORCE_SPEED_1000;
1992 break;
1993 }
1994
1995 /* MT7531 SGMII 1G force mode can only work in full duplex mode,
1996 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
1997 */
1998 if ((speed == SPEED_10 || speed == SPEED_100) &&
1999 duplex != DUPLEX_FULL)
2000 val |= MT7531_SGMII_FORCE_HALF_DUPLEX;
2001
2002 mt7530_write(priv, MT7531_SGMII_MODE(port), val);
2003 }
2004
mt753x_is_mac_port(u32 port)2005 static bool mt753x_is_mac_port(u32 port)
2006 {
2007 return (port == 5 || port == 6);
2008 }
2009
mt7531_sgmii_setup_mode_force(struct mt7530_priv * priv,u32 port,phy_interface_t interface)2010 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
2011 phy_interface_t interface)
2012 {
2013 u32 val;
2014
2015 if (!mt753x_is_mac_port(port))
2016 return -EINVAL;
2017
2018 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2019 MT7531_SGMII_PHYA_PWD);
2020
2021 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
2022 val &= ~MT7531_RG_TPHY_SPEED_MASK;
2023 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B
2024 * encoding.
2025 */
2026 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ?
2027 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G;
2028 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
2029
2030 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2031
2032 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex
2033 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2034 */
2035 mt7530_rmw(priv, MT7531_SGMII_MODE(port),
2036 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS,
2037 MT7531_SGMII_FORCE_SPEED_1000);
2038
2039 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2040
2041 return 0;
2042 }
2043
mt7531_sgmii_setup_mode_an(struct mt7530_priv * priv,int port,phy_interface_t interface)2044 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
2045 phy_interface_t interface)
2046 {
2047 if (!mt753x_is_mac_port(port))
2048 return -EINVAL;
2049
2050 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2051 MT7531_SGMII_PHYA_PWD);
2052
2053 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
2054 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G);
2055
2056 mt7530_set(priv, MT7531_SGMII_MODE(port),
2057 MT7531_SGMII_REMOTE_FAULT_DIS |
2058 MT7531_SGMII_SPEED_DUPLEX_AN);
2059
2060 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port),
2061 MT7531_SGMII_TX_CONFIG_MASK, 1);
2062
2063 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2064
2065 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART);
2066
2067 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2068
2069 return 0;
2070 }
2071
mt7531_sgmii_restart_an(struct dsa_switch * ds,int port)2072 static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port)
2073 {
2074 struct mt7530_priv *priv = ds->priv;
2075 u32 val;
2076
2077 /* Only restart AN when AN is enabled */
2078 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2079 if (val & MT7531_SGMII_AN_ENABLE) {
2080 val |= MT7531_SGMII_AN_RESTART;
2081 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
2082 }
2083 }
2084
2085 static int
mt7531_mac_config(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)2086 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2087 phy_interface_t interface)
2088 {
2089 struct mt7530_priv *priv = ds->priv;
2090 struct phy_device *phydev;
2091 struct dsa_port *dp;
2092
2093 if (!mt753x_is_mac_port(port)) {
2094 dev_err(priv->dev, "port %d is not a MAC port\n", port);
2095 return -EINVAL;
2096 }
2097
2098 switch (interface) {
2099 case PHY_INTERFACE_MODE_RGMII:
2100 case PHY_INTERFACE_MODE_RGMII_ID:
2101 case PHY_INTERFACE_MODE_RGMII_RXID:
2102 case PHY_INTERFACE_MODE_RGMII_TXID:
2103 dp = dsa_to_port(ds, port);
2104 phydev = dp->slave->phydev;
2105 return mt7531_rgmii_setup(priv, port, interface, phydev);
2106 case PHY_INTERFACE_MODE_SGMII:
2107 return mt7531_sgmii_setup_mode_an(priv, port, interface);
2108 case PHY_INTERFACE_MODE_NA:
2109 case PHY_INTERFACE_MODE_1000BASEX:
2110 case PHY_INTERFACE_MODE_2500BASEX:
2111 if (phylink_autoneg_inband(mode))
2112 return -EINVAL;
2113
2114 return mt7531_sgmii_setup_mode_force(priv, port, interface);
2115 default:
2116 return -EINVAL;
2117 }
2118
2119 return -EINVAL;
2120 }
2121
2122 static int
mt753x_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)2123 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2124 const struct phylink_link_state *state)
2125 {
2126 struct mt7530_priv *priv = ds->priv;
2127
2128 return priv->info->mac_port_config(ds, port, mode, state->interface);
2129 }
2130
2131 static void
mt753x_phylink_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)2132 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2133 const struct phylink_link_state *state)
2134 {
2135 struct mt7530_priv *priv = ds->priv;
2136 u32 mcr_cur, mcr_new;
2137
2138 if (!mt753x_phy_mode_supported(ds, port, state))
2139 goto unsupported;
2140
2141 switch (port) {
2142 case 0 ... 4: /* Internal phy */
2143 if (state->interface != PHY_INTERFACE_MODE_GMII)
2144 goto unsupported;
2145 break;
2146 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2147 if (priv->p5_interface == state->interface)
2148 break;
2149
2150 if (mt753x_mac_config(ds, port, mode, state) < 0)
2151 goto unsupported;
2152
2153 if (priv->p5_intf_sel != P5_DISABLED)
2154 priv->p5_interface = state->interface;
2155 break;
2156 case 6: /* 1st cpu port */
2157 if (priv->p6_interface == state->interface)
2158 break;
2159
2160 mt753x_pad_setup(ds, state);
2161
2162 if (mt753x_mac_config(ds, port, mode, state) < 0)
2163 goto unsupported;
2164
2165 priv->p6_interface = state->interface;
2166 break;
2167 default:
2168 unsupported:
2169 dev_err(ds->dev, "%s: unsupported %s port: %i\n",
2170 __func__, phy_modes(state->interface), port);
2171 return;
2172 }
2173
2174 if (phylink_autoneg_inband(mode) &&
2175 state->interface != PHY_INTERFACE_MODE_SGMII) {
2176 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
2177 __func__);
2178 return;
2179 }
2180
2181 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
2182 mcr_new = mcr_cur;
2183 mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
2184 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
2185 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id);
2186
2187 /* Are we connected to external phy */
2188 if (port == 5 && dsa_is_user_port(ds, 5))
2189 mcr_new |= PMCR_EXT_PHY;
2190
2191 if (mcr_new != mcr_cur)
2192 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
2193 }
2194
2195 static void
mt753x_phylink_mac_an_restart(struct dsa_switch * ds,int port)2196 mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port)
2197 {
2198 struct mt7530_priv *priv = ds->priv;
2199
2200 if (!priv->info->mac_pcs_an_restart)
2201 return;
2202
2203 priv->info->mac_pcs_an_restart(ds, port);
2204 }
2205
mt753x_phylink_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)2206 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
2207 unsigned int mode,
2208 phy_interface_t interface)
2209 {
2210 struct mt7530_priv *priv = ds->priv;
2211
2212 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
2213 }
2214
mt753x_mac_pcs_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,int speed,int duplex)2215 static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port,
2216 unsigned int mode, phy_interface_t interface,
2217 int speed, int duplex)
2218 {
2219 struct mt7530_priv *priv = ds->priv;
2220
2221 if (!priv->info->mac_pcs_link_up)
2222 return;
2223
2224 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2225 }
2226
mt753x_phylink_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)2227 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
2228 unsigned int mode,
2229 phy_interface_t interface,
2230 struct phy_device *phydev,
2231 int speed, int duplex,
2232 bool tx_pause, bool rx_pause)
2233 {
2234 struct mt7530_priv *priv = ds->priv;
2235 u32 mcr;
2236
2237 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2238
2239 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
2240
2241 /* MT753x MAC works in 1G full duplex mode for all up-clocked
2242 * variants.
2243 */
2244 if (interface == PHY_INTERFACE_MODE_TRGMII ||
2245 (phy_interface_mode_is_8023z(interface))) {
2246 speed = SPEED_1000;
2247 duplex = DUPLEX_FULL;
2248 }
2249
2250 switch (speed) {
2251 case SPEED_1000:
2252 mcr |= PMCR_FORCE_SPEED_1000;
2253 break;
2254 case SPEED_100:
2255 mcr |= PMCR_FORCE_SPEED_100;
2256 break;
2257 }
2258 if (duplex == DUPLEX_FULL) {
2259 mcr |= PMCR_FORCE_FDX;
2260 if (tx_pause)
2261 mcr |= PMCR_TX_FC_EN;
2262 if (rx_pause)
2263 mcr |= PMCR_RX_FC_EN;
2264 }
2265
2266 mt7530_set(priv, MT7530_PMCR_P(port), mcr);
2267 }
2268
2269 static int
mt7531_cpu_port_config(struct dsa_switch * ds,int port)2270 mt7531_cpu_port_config(struct dsa_switch *ds, int port)
2271 {
2272 struct mt7530_priv *priv = ds->priv;
2273 phy_interface_t interface;
2274 int speed;
2275 int ret;
2276
2277 switch (port) {
2278 case 5:
2279 if (mt7531_is_rgmii_port(priv, port))
2280 interface = PHY_INTERFACE_MODE_RGMII;
2281 else
2282 interface = PHY_INTERFACE_MODE_2500BASEX;
2283
2284 priv->p5_interface = interface;
2285 break;
2286 case 6:
2287 interface = PHY_INTERFACE_MODE_2500BASEX;
2288
2289 mt7531_pad_setup(ds, interface);
2290
2291 priv->p6_interface = interface;
2292 break;
2293 default:
2294 return -EINVAL;
2295 }
2296
2297 if (interface == PHY_INTERFACE_MODE_2500BASEX)
2298 speed = SPEED_2500;
2299 else
2300 speed = SPEED_1000;
2301
2302 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
2303 if (ret)
2304 return ret;
2305 mt7530_write(priv, MT7530_PMCR_P(port),
2306 PMCR_CPU_PORT_SETTING(priv->id));
2307 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
2308 speed, DUPLEX_FULL, true, true);
2309
2310 return 0;
2311 }
2312
2313 static void
mt7530_mac_port_validate(struct dsa_switch * ds,int port,unsigned long * supported)2314 mt7530_mac_port_validate(struct dsa_switch *ds, int port,
2315 unsigned long *supported)
2316 {
2317 if (port == 5)
2318 phylink_set(supported, 1000baseX_Full);
2319 }
2320
mt7531_mac_port_validate(struct dsa_switch * ds,int port,unsigned long * supported)2321 static void mt7531_mac_port_validate(struct dsa_switch *ds, int port,
2322 unsigned long *supported)
2323 {
2324 struct mt7530_priv *priv = ds->priv;
2325
2326 mt7531_sgmii_validate(priv, port, supported);
2327 }
2328
2329 static void
mt753x_phylink_validate(struct dsa_switch * ds,int port,unsigned long * supported,struct phylink_link_state * state)2330 mt753x_phylink_validate(struct dsa_switch *ds, int port,
2331 unsigned long *supported,
2332 struct phylink_link_state *state)
2333 {
2334 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
2335 struct mt7530_priv *priv = ds->priv;
2336
2337 if (state->interface != PHY_INTERFACE_MODE_NA &&
2338 !mt753x_phy_mode_supported(ds, port, state)) {
2339 linkmode_zero(supported);
2340 return;
2341 }
2342
2343 phylink_set_port_modes(mask);
2344
2345 if (state->interface != PHY_INTERFACE_MODE_TRGMII ||
2346 !phy_interface_mode_is_8023z(state->interface)) {
2347 phylink_set(mask, 10baseT_Half);
2348 phylink_set(mask, 10baseT_Full);
2349 phylink_set(mask, 100baseT_Half);
2350 phylink_set(mask, 100baseT_Full);
2351 phylink_set(mask, Autoneg);
2352 }
2353
2354 /* This switch only supports 1G full-duplex. */
2355 if (state->interface != PHY_INTERFACE_MODE_MII)
2356 phylink_set(mask, 1000baseT_Full);
2357
2358 priv->info->mac_port_validate(ds, port, mask);
2359
2360 phylink_set(mask, Pause);
2361 phylink_set(mask, Asym_Pause);
2362
2363 linkmode_and(supported, supported, mask);
2364 linkmode_and(state->advertising, state->advertising, mask);
2365
2366 /* We can only operate at 2500BaseX or 1000BaseX. If requested
2367 * to advertise both, only report advertising at 2500BaseX.
2368 */
2369 phylink_helper_basex_speed(state);
2370 }
2371
2372 static int
mt7530_phylink_mac_link_state(struct dsa_switch * ds,int port,struct phylink_link_state * state)2373 mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port,
2374 struct phylink_link_state *state)
2375 {
2376 struct mt7530_priv *priv = ds->priv;
2377 u32 pmsr;
2378
2379 if (port < 0 || port >= MT7530_NUM_PORTS)
2380 return -EINVAL;
2381
2382 pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
2383
2384 state->link = (pmsr & PMSR_LINK);
2385 state->an_complete = state->link;
2386 state->duplex = !!(pmsr & PMSR_DPX);
2387
2388 switch (pmsr & PMSR_SPEED_MASK) {
2389 case PMSR_SPEED_10:
2390 state->speed = SPEED_10;
2391 break;
2392 case PMSR_SPEED_100:
2393 state->speed = SPEED_100;
2394 break;
2395 case PMSR_SPEED_1000:
2396 state->speed = SPEED_1000;
2397 break;
2398 default:
2399 state->speed = SPEED_UNKNOWN;
2400 break;
2401 }
2402
2403 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
2404 if (pmsr & PMSR_RX_FC)
2405 state->pause |= MLO_PAUSE_RX;
2406 if (pmsr & PMSR_TX_FC)
2407 state->pause |= MLO_PAUSE_TX;
2408
2409 return 1;
2410 }
2411
2412 static int
mt7531_sgmii_pcs_get_state_an(struct mt7530_priv * priv,int port,struct phylink_link_state * state)2413 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port,
2414 struct phylink_link_state *state)
2415 {
2416 u32 status, val;
2417 u16 config_reg;
2418
2419 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2420 state->link = !!(status & MT7531_SGMII_LINK_STATUS);
2421 if (state->interface == PHY_INTERFACE_MODE_SGMII &&
2422 (status & MT7531_SGMII_AN_ENABLE)) {
2423 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
2424 config_reg = val >> 16;
2425
2426 switch (config_reg & LPA_SGMII_SPD_MASK) {
2427 case LPA_SGMII_1000:
2428 state->speed = SPEED_1000;
2429 break;
2430 case LPA_SGMII_100:
2431 state->speed = SPEED_100;
2432 break;
2433 case LPA_SGMII_10:
2434 state->speed = SPEED_10;
2435 break;
2436 default:
2437 dev_err(priv->dev, "invalid sgmii PHY speed\n");
2438 state->link = false;
2439 return -EINVAL;
2440 }
2441
2442 if (config_reg & LPA_SGMII_FULL_DUPLEX)
2443 state->duplex = DUPLEX_FULL;
2444 else
2445 state->duplex = DUPLEX_HALF;
2446 }
2447
2448 return 0;
2449 }
2450
2451 static int
mt7531_phylink_mac_link_state(struct dsa_switch * ds,int port,struct phylink_link_state * state)2452 mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port,
2453 struct phylink_link_state *state)
2454 {
2455 struct mt7530_priv *priv = ds->priv;
2456
2457 if (state->interface == PHY_INTERFACE_MODE_SGMII)
2458 return mt7531_sgmii_pcs_get_state_an(priv, port, state);
2459
2460 return -EOPNOTSUPP;
2461 }
2462
2463 static int
mt753x_phylink_mac_link_state(struct dsa_switch * ds,int port,struct phylink_link_state * state)2464 mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port,
2465 struct phylink_link_state *state)
2466 {
2467 struct mt7530_priv *priv = ds->priv;
2468
2469 return priv->info->mac_port_get_state(ds, port, state);
2470 }
2471
2472 static int
mt753x_setup(struct dsa_switch * ds)2473 mt753x_setup(struct dsa_switch *ds)
2474 {
2475 struct mt7530_priv *priv = ds->priv;
2476
2477 return priv->info->sw_setup(ds);
2478 }
2479
2480 static int
mt753x_phy_read(struct dsa_switch * ds,int port,int regnum)2481 mt753x_phy_read(struct dsa_switch *ds, int port, int regnum)
2482 {
2483 struct mt7530_priv *priv = ds->priv;
2484
2485 return priv->info->phy_read(ds, port, regnum);
2486 }
2487
2488 static int
mt753x_phy_write(struct dsa_switch * ds,int port,int regnum,u16 val)2489 mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2490 {
2491 struct mt7530_priv *priv = ds->priv;
2492
2493 return priv->info->phy_write(ds, port, regnum, val);
2494 }
2495
2496 static const struct dsa_switch_ops mt7530_switch_ops = {
2497 .get_tag_protocol = mtk_get_tag_protocol,
2498 .setup = mt753x_setup,
2499 .get_strings = mt7530_get_strings,
2500 .phy_read = mt753x_phy_read,
2501 .phy_write = mt753x_phy_write,
2502 .get_ethtool_stats = mt7530_get_ethtool_stats,
2503 .get_sset_count = mt7530_get_sset_count,
2504 .port_enable = mt7530_port_enable,
2505 .port_disable = mt7530_port_disable,
2506 .port_stp_state_set = mt7530_stp_state_set,
2507 .port_bridge_join = mt7530_port_bridge_join,
2508 .port_bridge_leave = mt7530_port_bridge_leave,
2509 .port_fdb_add = mt7530_port_fdb_add,
2510 .port_fdb_del = mt7530_port_fdb_del,
2511 .port_fdb_dump = mt7530_port_fdb_dump,
2512 .port_vlan_filtering = mt7530_port_vlan_filtering,
2513 .port_vlan_prepare = mt7530_port_vlan_prepare,
2514 .port_vlan_add = mt7530_port_vlan_add,
2515 .port_vlan_del = mt7530_port_vlan_del,
2516 .port_mirror_add = mt753x_port_mirror_add,
2517 .port_mirror_del = mt753x_port_mirror_del,
2518 .phylink_validate = mt753x_phylink_validate,
2519 .phylink_mac_link_state = mt753x_phylink_mac_link_state,
2520 .phylink_mac_config = mt753x_phylink_mac_config,
2521 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart,
2522 .phylink_mac_link_down = mt753x_phylink_mac_link_down,
2523 .phylink_mac_link_up = mt753x_phylink_mac_link_up,
2524 };
2525
2526 static const struct mt753x_info mt753x_table[] = {
2527 [ID_MT7621] = {
2528 .id = ID_MT7621,
2529 .sw_setup = mt7530_setup,
2530 .phy_read = mt7530_phy_read,
2531 .phy_write = mt7530_phy_write,
2532 .pad_setup = mt7530_pad_clk_setup,
2533 .phy_mode_supported = mt7530_phy_mode_supported,
2534 .mac_port_validate = mt7530_mac_port_validate,
2535 .mac_port_get_state = mt7530_phylink_mac_link_state,
2536 .mac_port_config = mt7530_mac_config,
2537 },
2538 [ID_MT7530] = {
2539 .id = ID_MT7530,
2540 .sw_setup = mt7530_setup,
2541 .phy_read = mt7530_phy_read,
2542 .phy_write = mt7530_phy_write,
2543 .pad_setup = mt7530_pad_clk_setup,
2544 .phy_mode_supported = mt7530_phy_mode_supported,
2545 .mac_port_validate = mt7530_mac_port_validate,
2546 .mac_port_get_state = mt7530_phylink_mac_link_state,
2547 .mac_port_config = mt7530_mac_config,
2548 },
2549 [ID_MT7531] = {
2550 .id = ID_MT7531,
2551 .sw_setup = mt7531_setup,
2552 .phy_read = mt7531_ind_phy_read,
2553 .phy_write = mt7531_ind_phy_write,
2554 .pad_setup = mt7531_pad_setup,
2555 .cpu_port_config = mt7531_cpu_port_config,
2556 .phy_mode_supported = mt7531_phy_mode_supported,
2557 .mac_port_validate = mt7531_mac_port_validate,
2558 .mac_port_get_state = mt7531_phylink_mac_link_state,
2559 .mac_port_config = mt7531_mac_config,
2560 .mac_pcs_an_restart = mt7531_sgmii_restart_an,
2561 .mac_pcs_link_up = mt7531_sgmii_link_up_force,
2562 },
2563 };
2564
2565 static const struct of_device_id mt7530_of_match[] = {
2566 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
2567 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
2568 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
2569 { /* sentinel */ },
2570 };
2571 MODULE_DEVICE_TABLE(of, mt7530_of_match);
2572
2573 static int
mt7530_probe(struct mdio_device * mdiodev)2574 mt7530_probe(struct mdio_device *mdiodev)
2575 {
2576 struct mt7530_priv *priv;
2577 struct device_node *dn;
2578
2579 dn = mdiodev->dev.of_node;
2580
2581 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
2582 if (!priv)
2583 return -ENOMEM;
2584
2585 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
2586 if (!priv->ds)
2587 return -ENOMEM;
2588
2589 priv->ds->dev = &mdiodev->dev;
2590 priv->ds->num_ports = MT7530_NUM_PORTS;
2591
2592 /* Use medatek,mcm property to distinguish hardware type that would
2593 * casues a little bit differences on power-on sequence.
2594 */
2595 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
2596 if (priv->mcm) {
2597 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
2598
2599 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
2600 if (IS_ERR(priv->rstc)) {
2601 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
2602 return PTR_ERR(priv->rstc);
2603 }
2604 }
2605
2606 /* Get the hardware identifier from the devicetree node.
2607 * We will need it for some of the clock and regulator setup.
2608 */
2609 priv->info = of_device_get_match_data(&mdiodev->dev);
2610 if (!priv->info)
2611 return -EINVAL;
2612
2613 /* Sanity check if these required device operations are filled
2614 * properly.
2615 */
2616 if (!priv->info->sw_setup || !priv->info->pad_setup ||
2617 !priv->info->phy_read || !priv->info->phy_write ||
2618 !priv->info->phy_mode_supported ||
2619 !priv->info->mac_port_validate ||
2620 !priv->info->mac_port_get_state || !priv->info->mac_port_config)
2621 return -EINVAL;
2622
2623 priv->id = priv->info->id;
2624
2625 if (priv->id == ID_MT7530) {
2626 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
2627 if (IS_ERR(priv->core_pwr))
2628 return PTR_ERR(priv->core_pwr);
2629
2630 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
2631 if (IS_ERR(priv->io_pwr))
2632 return PTR_ERR(priv->io_pwr);
2633 }
2634
2635 /* Not MCM that indicates switch works as the remote standalone
2636 * integrated circuit so the GPIO pin would be used to complete
2637 * the reset, otherwise memory-mapped register accessing used
2638 * through syscon provides in the case of MCM.
2639 */
2640 if (!priv->mcm) {
2641 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
2642 GPIOD_OUT_LOW);
2643 if (IS_ERR(priv->reset)) {
2644 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
2645 return PTR_ERR(priv->reset);
2646 }
2647 }
2648
2649 priv->bus = mdiodev->bus;
2650 priv->dev = &mdiodev->dev;
2651 priv->ds->priv = priv;
2652 priv->ds->ops = &mt7530_switch_ops;
2653 mutex_init(&priv->reg_mutex);
2654 dev_set_drvdata(&mdiodev->dev, priv);
2655
2656 return dsa_register_switch(priv->ds);
2657 }
2658
2659 static void
mt7530_remove(struct mdio_device * mdiodev)2660 mt7530_remove(struct mdio_device *mdiodev)
2661 {
2662 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
2663 int ret = 0;
2664
2665 ret = regulator_disable(priv->core_pwr);
2666 if (ret < 0)
2667 dev_err(priv->dev,
2668 "Failed to disable core power: %d\n", ret);
2669
2670 ret = regulator_disable(priv->io_pwr);
2671 if (ret < 0)
2672 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
2673 ret);
2674
2675 dsa_unregister_switch(priv->ds);
2676 mutex_destroy(&priv->reg_mutex);
2677 }
2678
2679 static struct mdio_driver mt7530_mdio_driver = {
2680 .probe = mt7530_probe,
2681 .remove = mt7530_remove,
2682 .mdiodrv.driver = {
2683 .name = "mt7530",
2684 .of_match_table = mt7530_of_match,
2685 },
2686 };
2687
2688 mdio_module_driver(mt7530_mdio_driver);
2689
2690 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
2691 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
2692 MODULE_LICENSE("GPL");
2693