1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Atmel AT91 Serial ports
4 * Copyright (C) 2003 Rick Bronson
5 *
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 *
9 * DMA support added by Chip Coldwell.
10 */
11 #include <linux/tty.h>
12 #include <linux/ioport.h>
13 #include <linux/slab.h>
14 #include <linux/init.h>
15 #include <linux/serial.h>
16 #include <linux/clk.h>
17 #include <linux/console.h>
18 #include <linux/sysrq.h>
19 #include <linux/tty_flip.h>
20 #include <linux/platform_device.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmaengine.h>
25 #include <linux/atmel_pdc.h>
26 #include <linux/uaccess.h>
27 #include <linux/platform_data/atmel.h>
28 #include <linux/timer.h>
29 #include <linux/err.h>
30 #include <linux/irq.h>
31 #include <linux/suspend.h>
32 #include <linux/mm.h>
33
34 #include <asm/div64.h>
35 #include <asm/io.h>
36 #include <asm/ioctls.h>
37
38 #define PDC_BUFFER_SIZE 512
39 /* Revisit: We should calculate this based on the actual port settings */
40 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
41
42 /* The minium number of data FIFOs should be able to contain */
43 #define ATMEL_MIN_FIFO_SIZE 8
44 /*
45 * These two offsets are substracted from the RX FIFO size to define the RTS
46 * high and low thresholds
47 */
48 #define ATMEL_RTS_HIGH_OFFSET 16
49 #define ATMEL_RTS_LOW_OFFSET 20
50
51 #include <linux/serial_core.h>
52
53 #include "serial_mctrl_gpio.h"
54 #include "atmel_serial.h"
55
56 static void atmel_start_rx(struct uart_port *port);
57 static void atmel_stop_rx(struct uart_port *port);
58
59 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
60
61 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
62 * should coexist with the 8250 driver, such as if we have an external 16C550
63 * UART. */
64 #define SERIAL_ATMEL_MAJOR 204
65 #define MINOR_START 154
66 #define ATMEL_DEVICENAME "ttyAT"
67
68 #else
69
70 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
71 * name, but it is legally reserved for the 8250 driver. */
72 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
73 #define MINOR_START 64
74 #define ATMEL_DEVICENAME "ttyS"
75
76 #endif
77
78 #define ATMEL_ISR_PASS_LIMIT 256
79
80 struct atmel_dma_buffer {
81 unsigned char *buf;
82 dma_addr_t dma_addr;
83 unsigned int dma_size;
84 unsigned int ofs;
85 };
86
87 struct atmel_uart_char {
88 u16 status;
89 u16 ch;
90 };
91
92 /*
93 * Be careful, the real size of the ring buffer is
94 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
95 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
96 * DMA mode.
97 */
98 #define ATMEL_SERIAL_RINGSIZE 1024
99
100 /*
101 * at91: 6 USARTs and one DBGU port (SAM9260)
102 * samx7: 3 USARTs and 5 UARTs
103 */
104 #define ATMEL_MAX_UART 8
105
106 /*
107 * We wrap our port structure around the generic uart_port.
108 */
109 struct atmel_uart_port {
110 struct uart_port uart; /* uart */
111 struct clk *clk; /* uart clock */
112 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
113 u32 backup_imr; /* IMR saved during suspend */
114 int break_active; /* break being received */
115
116 bool use_dma_rx; /* enable DMA receiver */
117 bool use_pdc_rx; /* enable PDC receiver */
118 short pdc_rx_idx; /* current PDC RX buffer */
119 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
120
121 bool use_dma_tx; /* enable DMA transmitter */
122 bool use_pdc_tx; /* enable PDC transmitter */
123 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
124
125 spinlock_t lock_tx; /* port lock */
126 spinlock_t lock_rx; /* port lock */
127 struct dma_chan *chan_tx;
128 struct dma_chan *chan_rx;
129 struct dma_async_tx_descriptor *desc_tx;
130 struct dma_async_tx_descriptor *desc_rx;
131 dma_cookie_t cookie_tx;
132 dma_cookie_t cookie_rx;
133 struct scatterlist sg_tx;
134 struct scatterlist sg_rx;
135 struct tasklet_struct tasklet_rx;
136 struct tasklet_struct tasklet_tx;
137 atomic_t tasklet_shutdown;
138 unsigned int irq_status_prev;
139 unsigned int tx_len;
140
141 struct circ_buf rx_ring;
142
143 struct mctrl_gpios *gpios;
144 u32 backup_mode; /* MR saved during iso7816 operations */
145 u32 backup_brgr; /* BRGR saved during iso7816 operations */
146 unsigned int tx_done_mask;
147 u32 fifo_size;
148 u32 rts_high;
149 u32 rts_low;
150 bool ms_irq_enabled;
151 u32 rtor; /* address of receiver timeout register if it exists */
152 bool has_frac_baudrate;
153 bool has_hw_timer;
154 struct timer_list uart_timer;
155
156 bool tx_stopped;
157 bool suspended;
158 unsigned int pending;
159 unsigned int pending_status;
160 spinlock_t lock_suspended;
161
162 bool hd_start_rx; /* can start RX during half-duplex operation */
163
164 /* ISO7816 */
165 unsigned int fidi_min;
166 unsigned int fidi_max;
167
168 #ifdef CONFIG_PM
169 struct {
170 u32 cr;
171 u32 mr;
172 u32 imr;
173 u32 brgr;
174 u32 rtor;
175 u32 ttgr;
176 u32 fmr;
177 u32 fimr;
178 } cache;
179 #endif
180
181 int (*prepare_rx)(struct uart_port *port);
182 int (*prepare_tx)(struct uart_port *port);
183 void (*schedule_rx)(struct uart_port *port);
184 void (*schedule_tx)(struct uart_port *port);
185 void (*release_rx)(struct uart_port *port);
186 void (*release_tx)(struct uart_port *port);
187 };
188
189 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
190 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
191
192 #if defined(CONFIG_OF)
193 static const struct of_device_id atmel_serial_dt_ids[] = {
194 { .compatible = "atmel,at91rm9200-usart-serial" },
195 { /* sentinel */ }
196 };
197 #endif
198
199 static inline struct atmel_uart_port *
to_atmel_uart_port(struct uart_port * uart)200 to_atmel_uart_port(struct uart_port *uart)
201 {
202 return container_of(uart, struct atmel_uart_port, uart);
203 }
204
atmel_uart_readl(struct uart_port * port,u32 reg)205 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
206 {
207 return __raw_readl(port->membase + reg);
208 }
209
atmel_uart_writel(struct uart_port * port,u32 reg,u32 value)210 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
211 {
212 __raw_writel(value, port->membase + reg);
213 }
214
atmel_uart_read_char(struct uart_port * port)215 static inline u8 atmel_uart_read_char(struct uart_port *port)
216 {
217 return __raw_readb(port->membase + ATMEL_US_RHR);
218 }
219
atmel_uart_write_char(struct uart_port * port,u8 value)220 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
221 {
222 __raw_writeb(value, port->membase + ATMEL_US_THR);
223 }
224
atmel_uart_is_half_duplex(struct uart_port * port)225 static inline int atmel_uart_is_half_duplex(struct uart_port *port)
226 {
227 return ((port->rs485.flags & SER_RS485_ENABLED) &&
228 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
229 (port->iso7816.flags & SER_ISO7816_ENABLED);
230 }
231
232 #ifdef CONFIG_SERIAL_ATMEL_PDC
atmel_use_pdc_rx(struct uart_port * port)233 static bool atmel_use_pdc_rx(struct uart_port *port)
234 {
235 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
236
237 return atmel_port->use_pdc_rx;
238 }
239
atmel_use_pdc_tx(struct uart_port * port)240 static bool atmel_use_pdc_tx(struct uart_port *port)
241 {
242 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
243
244 return atmel_port->use_pdc_tx;
245 }
246 #else
atmel_use_pdc_rx(struct uart_port * port)247 static bool atmel_use_pdc_rx(struct uart_port *port)
248 {
249 return false;
250 }
251
atmel_use_pdc_tx(struct uart_port * port)252 static bool atmel_use_pdc_tx(struct uart_port *port)
253 {
254 return false;
255 }
256 #endif
257
atmel_use_dma_tx(struct uart_port * port)258 static bool atmel_use_dma_tx(struct uart_port *port)
259 {
260 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
261
262 return atmel_port->use_dma_tx;
263 }
264
atmel_use_dma_rx(struct uart_port * port)265 static bool atmel_use_dma_rx(struct uart_port *port)
266 {
267 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
268
269 return atmel_port->use_dma_rx;
270 }
271
atmel_use_fifo(struct uart_port * port)272 static bool atmel_use_fifo(struct uart_port *port)
273 {
274 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
275
276 return atmel_port->fifo_size;
277 }
278
atmel_tasklet_schedule(struct atmel_uart_port * atmel_port,struct tasklet_struct * t)279 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
280 struct tasklet_struct *t)
281 {
282 if (!atomic_read(&atmel_port->tasklet_shutdown))
283 tasklet_schedule(t);
284 }
285
286 /* Enable or disable the rs485 support */
atmel_config_rs485(struct uart_port * port,struct serial_rs485 * rs485conf)287 static int atmel_config_rs485(struct uart_port *port,
288 struct serial_rs485 *rs485conf)
289 {
290 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
291 unsigned int mode;
292
293 /* Disable interrupts */
294 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
295
296 mode = atmel_uart_readl(port, ATMEL_US_MR);
297
298 /* Resetting serial mode to RS232 (0x0) */
299 mode &= ~ATMEL_US_USMODE;
300
301 port->rs485 = *rs485conf;
302
303 if (rs485conf->flags & SER_RS485_ENABLED) {
304 dev_dbg(port->dev, "Setting UART to RS485\n");
305 if (port->rs485.flags & SER_RS485_RX_DURING_TX)
306 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
307 else
308 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
309
310 atmel_uart_writel(port, ATMEL_US_TTGR,
311 rs485conf->delay_rts_after_send);
312 mode |= ATMEL_US_USMODE_RS485;
313 } else {
314 dev_dbg(port->dev, "Setting UART to RS232\n");
315 if (atmel_use_pdc_tx(port))
316 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
317 ATMEL_US_TXBUFE;
318 else
319 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
320 }
321 atmel_uart_writel(port, ATMEL_US_MR, mode);
322
323 /* Enable interrupts */
324 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
325
326 return 0;
327 }
328
atmel_calc_cd(struct uart_port * port,struct serial_iso7816 * iso7816conf)329 static unsigned int atmel_calc_cd(struct uart_port *port,
330 struct serial_iso7816 *iso7816conf)
331 {
332 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
333 unsigned int cd;
334 u64 mck_rate;
335
336 mck_rate = (u64)clk_get_rate(atmel_port->clk);
337 do_div(mck_rate, iso7816conf->clk);
338 cd = mck_rate;
339 return cd;
340 }
341
atmel_calc_fidi(struct uart_port * port,struct serial_iso7816 * iso7816conf)342 static unsigned int atmel_calc_fidi(struct uart_port *port,
343 struct serial_iso7816 *iso7816conf)
344 {
345 u64 fidi = 0;
346
347 if (iso7816conf->sc_fi && iso7816conf->sc_di) {
348 fidi = (u64)iso7816conf->sc_fi;
349 do_div(fidi, iso7816conf->sc_di);
350 }
351 return (u32)fidi;
352 }
353
354 /* Enable or disable the iso7816 support */
355 /* Called with interrupts disabled */
atmel_config_iso7816(struct uart_port * port,struct serial_iso7816 * iso7816conf)356 static int atmel_config_iso7816(struct uart_port *port,
357 struct serial_iso7816 *iso7816conf)
358 {
359 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
360 unsigned int mode;
361 unsigned int cd, fidi;
362 int ret = 0;
363
364 /* Disable interrupts */
365 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
366
367 mode = atmel_uart_readl(port, ATMEL_US_MR);
368
369 if (iso7816conf->flags & SER_ISO7816_ENABLED) {
370 mode &= ~ATMEL_US_USMODE;
371
372 if (iso7816conf->tg > 255) {
373 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
374 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
375 ret = -EINVAL;
376 goto err_out;
377 }
378
379 if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
380 == SER_ISO7816_T(0)) {
381 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
382 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
383 == SER_ISO7816_T(1)) {
384 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
385 } else {
386 dev_err(port->dev, "ISO7816: Type not supported\n");
387 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
388 ret = -EINVAL;
389 goto err_out;
390 }
391
392 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
393
394 /* select mck clock, and output */
395 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
396 /* set parity for normal/inverse mode + max iterations */
397 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
398
399 cd = atmel_calc_cd(port, iso7816conf);
400 fidi = atmel_calc_fidi(port, iso7816conf);
401 if (fidi == 0) {
402 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
403 } else if (fidi < atmel_port->fidi_min
404 || fidi > atmel_port->fidi_max) {
405 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
406 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
407 ret = -EINVAL;
408 goto err_out;
409 }
410
411 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
412 /* port not yet in iso7816 mode: store configuration */
413 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
414 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
415 }
416
417 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
418 atmel_uart_writel(port, ATMEL_US_BRGR, cd);
419 atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
420
421 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
422 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
423 } else {
424 dev_dbg(port->dev, "Setting UART back to RS232\n");
425 /* back to last RS232 settings */
426 mode = atmel_port->backup_mode;
427 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
428 atmel_uart_writel(port, ATMEL_US_TTGR, 0);
429 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
430 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
431
432 if (atmel_use_pdc_tx(port))
433 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
434 ATMEL_US_TXBUFE;
435 else
436 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
437 }
438
439 port->iso7816 = *iso7816conf;
440
441 atmel_uart_writel(port, ATMEL_US_MR, mode);
442
443 err_out:
444 /* Enable interrupts */
445 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
446
447 return ret;
448 }
449
450 /*
451 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
452 */
atmel_tx_empty(struct uart_port * port)453 static u_int atmel_tx_empty(struct uart_port *port)
454 {
455 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
456
457 if (atmel_port->tx_stopped)
458 return TIOCSER_TEMT;
459 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
460 TIOCSER_TEMT :
461 0;
462 }
463
464 /*
465 * Set state of the modem control output lines
466 */
atmel_set_mctrl(struct uart_port * port,u_int mctrl)467 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
468 {
469 unsigned int control = 0;
470 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
471 unsigned int rts_paused, rts_ready;
472 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
473
474 /* override mode to RS485 if needed, otherwise keep the current mode */
475 if (port->rs485.flags & SER_RS485_ENABLED) {
476 atmel_uart_writel(port, ATMEL_US_TTGR,
477 port->rs485.delay_rts_after_send);
478 mode &= ~ATMEL_US_USMODE;
479 mode |= ATMEL_US_USMODE_RS485;
480 }
481
482 /* set the RTS line state according to the mode */
483 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
484 /* force RTS line to high level */
485 rts_paused = ATMEL_US_RTSEN;
486
487 /* give the control of the RTS line back to the hardware */
488 rts_ready = ATMEL_US_RTSDIS;
489 } else {
490 /* force RTS line to high level */
491 rts_paused = ATMEL_US_RTSDIS;
492
493 /* force RTS line to low level */
494 rts_ready = ATMEL_US_RTSEN;
495 }
496
497 if (mctrl & TIOCM_RTS)
498 control |= rts_ready;
499 else
500 control |= rts_paused;
501
502 if (mctrl & TIOCM_DTR)
503 control |= ATMEL_US_DTREN;
504 else
505 control |= ATMEL_US_DTRDIS;
506
507 atmel_uart_writel(port, ATMEL_US_CR, control);
508
509 mctrl_gpio_set(atmel_port->gpios, mctrl);
510
511 /* Local loopback mode? */
512 mode &= ~ATMEL_US_CHMODE;
513 if (mctrl & TIOCM_LOOP)
514 mode |= ATMEL_US_CHMODE_LOC_LOOP;
515 else
516 mode |= ATMEL_US_CHMODE_NORMAL;
517
518 atmel_uart_writel(port, ATMEL_US_MR, mode);
519 }
520
521 /*
522 * Get state of the modem control input lines
523 */
atmel_get_mctrl(struct uart_port * port)524 static u_int atmel_get_mctrl(struct uart_port *port)
525 {
526 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
527 unsigned int ret = 0, status;
528
529 status = atmel_uart_readl(port, ATMEL_US_CSR);
530
531 /*
532 * The control signals are active low.
533 */
534 if (!(status & ATMEL_US_DCD))
535 ret |= TIOCM_CD;
536 if (!(status & ATMEL_US_CTS))
537 ret |= TIOCM_CTS;
538 if (!(status & ATMEL_US_DSR))
539 ret |= TIOCM_DSR;
540 if (!(status & ATMEL_US_RI))
541 ret |= TIOCM_RI;
542
543 return mctrl_gpio_get(atmel_port->gpios, &ret);
544 }
545
546 /*
547 * Stop transmitting.
548 */
atmel_stop_tx(struct uart_port * port)549 static void atmel_stop_tx(struct uart_port *port)
550 {
551 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
552
553 if (atmel_use_pdc_tx(port)) {
554 /* disable PDC transmit */
555 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
556 }
557
558 /*
559 * Disable the transmitter.
560 * This is mandatory when DMA is used, otherwise the DMA buffer
561 * is fully transmitted.
562 */
563 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
564 atmel_port->tx_stopped = true;
565
566 /* Disable interrupts */
567 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
568
569 if (atmel_uart_is_half_duplex(port))
570 if (!atomic_read(&atmel_port->tasklet_shutdown))
571 atmel_start_rx(port);
572
573 }
574
575 /*
576 * Start transmitting.
577 */
atmel_start_tx(struct uart_port * port)578 static void atmel_start_tx(struct uart_port *port)
579 {
580 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
581
582 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
583 & ATMEL_PDC_TXTEN))
584 /* The transmitter is already running. Yes, we
585 really need this.*/
586 return;
587
588 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
589 if (atmel_uart_is_half_duplex(port))
590 atmel_stop_rx(port);
591
592 if (atmel_use_pdc_tx(port))
593 /* re-enable PDC transmit */
594 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
595
596 /* Enable interrupts */
597 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
598
599 /* re-enable the transmitter */
600 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
601 atmel_port->tx_stopped = false;
602 }
603
604 /*
605 * start receiving - port is in process of being opened.
606 */
atmel_start_rx(struct uart_port * port)607 static void atmel_start_rx(struct uart_port *port)
608 {
609 /* reset status and receiver */
610 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
611
612 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
613
614 if (atmel_use_pdc_rx(port)) {
615 /* enable PDC controller */
616 atmel_uart_writel(port, ATMEL_US_IER,
617 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
618 port->read_status_mask);
619 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
620 } else {
621 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
622 }
623 }
624
625 /*
626 * Stop receiving - port is in process of being closed.
627 */
atmel_stop_rx(struct uart_port * port)628 static void atmel_stop_rx(struct uart_port *port)
629 {
630 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
631
632 if (atmel_use_pdc_rx(port)) {
633 /* disable PDC receive */
634 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
635 atmel_uart_writel(port, ATMEL_US_IDR,
636 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
637 port->read_status_mask);
638 } else {
639 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
640 }
641 }
642
643 /*
644 * Enable modem status interrupts
645 */
atmel_enable_ms(struct uart_port * port)646 static void atmel_enable_ms(struct uart_port *port)
647 {
648 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
649 uint32_t ier = 0;
650
651 /*
652 * Interrupt should not be enabled twice
653 */
654 if (atmel_port->ms_irq_enabled)
655 return;
656
657 atmel_port->ms_irq_enabled = true;
658
659 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
660 ier |= ATMEL_US_CTSIC;
661
662 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
663 ier |= ATMEL_US_DSRIC;
664
665 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
666 ier |= ATMEL_US_RIIC;
667
668 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
669 ier |= ATMEL_US_DCDIC;
670
671 atmel_uart_writel(port, ATMEL_US_IER, ier);
672
673 mctrl_gpio_enable_ms(atmel_port->gpios);
674 }
675
676 /*
677 * Disable modem status interrupts
678 */
atmel_disable_ms(struct uart_port * port)679 static void atmel_disable_ms(struct uart_port *port)
680 {
681 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
682 uint32_t idr = 0;
683
684 /*
685 * Interrupt should not be disabled twice
686 */
687 if (!atmel_port->ms_irq_enabled)
688 return;
689
690 atmel_port->ms_irq_enabled = false;
691
692 mctrl_gpio_disable_ms(atmel_port->gpios);
693
694 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
695 idr |= ATMEL_US_CTSIC;
696
697 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
698 idr |= ATMEL_US_DSRIC;
699
700 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
701 idr |= ATMEL_US_RIIC;
702
703 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
704 idr |= ATMEL_US_DCDIC;
705
706 atmel_uart_writel(port, ATMEL_US_IDR, idr);
707 }
708
709 /*
710 * Control the transmission of a break signal
711 */
atmel_break_ctl(struct uart_port * port,int break_state)712 static void atmel_break_ctl(struct uart_port *port, int break_state)
713 {
714 if (break_state != 0)
715 /* start break */
716 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
717 else
718 /* stop break */
719 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
720 }
721
722 /*
723 * Stores the incoming character in the ring buffer
724 */
725 static void
atmel_buffer_rx_char(struct uart_port * port,unsigned int status,unsigned int ch)726 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
727 unsigned int ch)
728 {
729 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
730 struct circ_buf *ring = &atmel_port->rx_ring;
731 struct atmel_uart_char *c;
732
733 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
734 /* Buffer overflow, ignore char */
735 return;
736
737 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
738 c->status = status;
739 c->ch = ch;
740
741 /* Make sure the character is stored before we update head. */
742 smp_wmb();
743
744 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
745 }
746
747 /*
748 * Deal with parity, framing and overrun errors.
749 */
atmel_pdc_rxerr(struct uart_port * port,unsigned int status)750 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
751 {
752 /* clear error */
753 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
754
755 if (status & ATMEL_US_RXBRK) {
756 /* ignore side-effect */
757 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
758 port->icount.brk++;
759 }
760 if (status & ATMEL_US_PARE)
761 port->icount.parity++;
762 if (status & ATMEL_US_FRAME)
763 port->icount.frame++;
764 if (status & ATMEL_US_OVRE)
765 port->icount.overrun++;
766 }
767
768 /*
769 * Characters received (called from interrupt handler)
770 */
atmel_rx_chars(struct uart_port * port)771 static void atmel_rx_chars(struct uart_port *port)
772 {
773 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
774 unsigned int status, ch;
775
776 status = atmel_uart_readl(port, ATMEL_US_CSR);
777 while (status & ATMEL_US_RXRDY) {
778 ch = atmel_uart_read_char(port);
779
780 /*
781 * note that the error handling code is
782 * out of the main execution path
783 */
784 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
785 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
786 || atmel_port->break_active)) {
787
788 /* clear error */
789 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
790
791 if (status & ATMEL_US_RXBRK
792 && !atmel_port->break_active) {
793 atmel_port->break_active = 1;
794 atmel_uart_writel(port, ATMEL_US_IER,
795 ATMEL_US_RXBRK);
796 } else {
797 /*
798 * This is either the end-of-break
799 * condition or we've received at
800 * least one character without RXBRK
801 * being set. In both cases, the next
802 * RXBRK will indicate start-of-break.
803 */
804 atmel_uart_writel(port, ATMEL_US_IDR,
805 ATMEL_US_RXBRK);
806 status &= ~ATMEL_US_RXBRK;
807 atmel_port->break_active = 0;
808 }
809 }
810
811 atmel_buffer_rx_char(port, status, ch);
812 status = atmel_uart_readl(port, ATMEL_US_CSR);
813 }
814
815 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
816 }
817
818 /*
819 * Transmit characters (called from tasklet with TXRDY interrupt
820 * disabled)
821 */
atmel_tx_chars(struct uart_port * port)822 static void atmel_tx_chars(struct uart_port *port)
823 {
824 struct circ_buf *xmit = &port->state->xmit;
825 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
826
827 if (port->x_char &&
828 (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) {
829 atmel_uart_write_char(port, port->x_char);
830 port->icount.tx++;
831 port->x_char = 0;
832 }
833 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
834 return;
835
836 while (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY) {
837 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
838 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
839 port->icount.tx++;
840 if (uart_circ_empty(xmit))
841 break;
842 }
843
844 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
845 uart_write_wakeup(port);
846
847 if (!uart_circ_empty(xmit)) {
848 /* we still have characters to transmit, so we should continue
849 * transmitting them when TX is ready, regardless of
850 * mode or duplexity
851 */
852 atmel_port->tx_done_mask |= ATMEL_US_TXRDY;
853
854 /* Enable interrupts */
855 atmel_uart_writel(port, ATMEL_US_IER,
856 atmel_port->tx_done_mask);
857 } else {
858 if (atmel_uart_is_half_duplex(port))
859 atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY;
860 }
861 }
862
atmel_complete_tx_dma(void * arg)863 static void atmel_complete_tx_dma(void *arg)
864 {
865 struct atmel_uart_port *atmel_port = arg;
866 struct uart_port *port = &atmel_port->uart;
867 struct circ_buf *xmit = &port->state->xmit;
868 struct dma_chan *chan = atmel_port->chan_tx;
869 unsigned long flags;
870
871 spin_lock_irqsave(&port->lock, flags);
872
873 if (chan)
874 dmaengine_terminate_all(chan);
875 xmit->tail += atmel_port->tx_len;
876 xmit->tail &= UART_XMIT_SIZE - 1;
877
878 port->icount.tx += atmel_port->tx_len;
879
880 spin_lock_irq(&atmel_port->lock_tx);
881 async_tx_ack(atmel_port->desc_tx);
882 atmel_port->cookie_tx = -EINVAL;
883 atmel_port->desc_tx = NULL;
884 spin_unlock_irq(&atmel_port->lock_tx);
885
886 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
887 uart_write_wakeup(port);
888
889 /*
890 * xmit is a circular buffer so, if we have just send data from
891 * xmit->tail to the end of xmit->buf, now we have to transmit the
892 * remaining data from the beginning of xmit->buf to xmit->head.
893 */
894 if (!uart_circ_empty(xmit))
895 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
896 else if (atmel_uart_is_half_duplex(port)) {
897 /*
898 * DMA done, re-enable TXEMPTY and signal that we can stop
899 * TX and start RX for RS485
900 */
901 atmel_port->hd_start_rx = true;
902 atmel_uart_writel(port, ATMEL_US_IER,
903 atmel_port->tx_done_mask);
904 }
905
906 spin_unlock_irqrestore(&port->lock, flags);
907 }
908
atmel_release_tx_dma(struct uart_port * port)909 static void atmel_release_tx_dma(struct uart_port *port)
910 {
911 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
912 struct dma_chan *chan = atmel_port->chan_tx;
913
914 if (chan) {
915 dmaengine_terminate_all(chan);
916 dma_release_channel(chan);
917 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
918 DMA_TO_DEVICE);
919 }
920
921 atmel_port->desc_tx = NULL;
922 atmel_port->chan_tx = NULL;
923 atmel_port->cookie_tx = -EINVAL;
924 }
925
926 /*
927 * Called from tasklet with TXRDY interrupt is disabled.
928 */
atmel_tx_dma(struct uart_port * port)929 static void atmel_tx_dma(struct uart_port *port)
930 {
931 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
932 struct circ_buf *xmit = &port->state->xmit;
933 struct dma_chan *chan = atmel_port->chan_tx;
934 struct dma_async_tx_descriptor *desc;
935 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
936 unsigned int tx_len, part1_len, part2_len, sg_len;
937 dma_addr_t phys_addr;
938
939 /* Make sure we have an idle channel */
940 if (atmel_port->desc_tx != NULL)
941 return;
942
943 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
944 /*
945 * DMA is idle now.
946 * Port xmit buffer is already mapped,
947 * and it is one page... Just adjust
948 * offsets and lengths. Since it is a circular buffer,
949 * we have to transmit till the end, and then the rest.
950 * Take the port lock to get a
951 * consistent xmit buffer state.
952 */
953 tx_len = CIRC_CNT_TO_END(xmit->head,
954 xmit->tail,
955 UART_XMIT_SIZE);
956
957 if (atmel_port->fifo_size) {
958 /* multi data mode */
959 part1_len = (tx_len & ~0x3); /* DWORD access */
960 part2_len = (tx_len & 0x3); /* BYTE access */
961 } else {
962 /* single data (legacy) mode */
963 part1_len = 0;
964 part2_len = tx_len; /* BYTE access only */
965 }
966
967 sg_init_table(sgl, 2);
968 sg_len = 0;
969 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
970 if (part1_len) {
971 sg = &sgl[sg_len++];
972 sg_dma_address(sg) = phys_addr;
973 sg_dma_len(sg) = part1_len;
974
975 phys_addr += part1_len;
976 }
977
978 if (part2_len) {
979 sg = &sgl[sg_len++];
980 sg_dma_address(sg) = phys_addr;
981 sg_dma_len(sg) = part2_len;
982 }
983
984 /*
985 * save tx_len so atmel_complete_tx_dma() will increase
986 * xmit->tail correctly
987 */
988 atmel_port->tx_len = tx_len;
989
990 desc = dmaengine_prep_slave_sg(chan,
991 sgl,
992 sg_len,
993 DMA_MEM_TO_DEV,
994 DMA_PREP_INTERRUPT |
995 DMA_CTRL_ACK);
996 if (!desc) {
997 dev_err(port->dev, "Failed to send via dma!\n");
998 return;
999 }
1000
1001 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
1002
1003 atmel_port->desc_tx = desc;
1004 desc->callback = atmel_complete_tx_dma;
1005 desc->callback_param = atmel_port;
1006 atmel_port->cookie_tx = dmaengine_submit(desc);
1007 if (dma_submit_error(atmel_port->cookie_tx)) {
1008 dev_err(port->dev, "dma_submit_error %d\n",
1009 atmel_port->cookie_tx);
1010 return;
1011 }
1012
1013 dma_async_issue_pending(chan);
1014 }
1015
1016 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1017 uart_write_wakeup(port);
1018 }
1019
atmel_prepare_tx_dma(struct uart_port * port)1020 static int atmel_prepare_tx_dma(struct uart_port *port)
1021 {
1022 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1023 struct device *mfd_dev = port->dev->parent;
1024 dma_cap_mask_t mask;
1025 struct dma_slave_config config;
1026 int ret, nent;
1027
1028 dma_cap_zero(mask);
1029 dma_cap_set(DMA_SLAVE, mask);
1030
1031 atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx");
1032 if (atmel_port->chan_tx == NULL)
1033 goto chan_err;
1034 dev_info(port->dev, "using %s for tx DMA transfers\n",
1035 dma_chan_name(atmel_port->chan_tx));
1036
1037 spin_lock_init(&atmel_port->lock_tx);
1038 sg_init_table(&atmel_port->sg_tx, 1);
1039 /* UART circular tx buffer is an aligned page. */
1040 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
1041 sg_set_page(&atmel_port->sg_tx,
1042 virt_to_page(port->state->xmit.buf),
1043 UART_XMIT_SIZE,
1044 offset_in_page(port->state->xmit.buf));
1045 nent = dma_map_sg(port->dev,
1046 &atmel_port->sg_tx,
1047 1,
1048 DMA_TO_DEVICE);
1049
1050 if (!nent) {
1051 dev_dbg(port->dev, "need to release resource of dma\n");
1052 goto chan_err;
1053 } else {
1054 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1055 sg_dma_len(&atmel_port->sg_tx),
1056 port->state->xmit.buf,
1057 &sg_dma_address(&atmel_port->sg_tx));
1058 }
1059
1060 /* Configure the slave DMA */
1061 memset(&config, 0, sizeof(config));
1062 config.direction = DMA_MEM_TO_DEV;
1063 config.dst_addr_width = (atmel_port->fifo_size) ?
1064 DMA_SLAVE_BUSWIDTH_4_BYTES :
1065 DMA_SLAVE_BUSWIDTH_1_BYTE;
1066 config.dst_addr = port->mapbase + ATMEL_US_THR;
1067 config.dst_maxburst = 1;
1068
1069 ret = dmaengine_slave_config(atmel_port->chan_tx,
1070 &config);
1071 if (ret) {
1072 dev_err(port->dev, "DMA tx slave configuration failed\n");
1073 goto chan_err;
1074 }
1075
1076 return 0;
1077
1078 chan_err:
1079 dev_err(port->dev, "TX channel not available, switch to pio\n");
1080 atmel_port->use_dma_tx = false;
1081 if (atmel_port->chan_tx)
1082 atmel_release_tx_dma(port);
1083 return -EINVAL;
1084 }
1085
atmel_complete_rx_dma(void * arg)1086 static void atmel_complete_rx_dma(void *arg)
1087 {
1088 struct uart_port *port = arg;
1089 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1090
1091 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1092 }
1093
atmel_release_rx_dma(struct uart_port * port)1094 static void atmel_release_rx_dma(struct uart_port *port)
1095 {
1096 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1097 struct dma_chan *chan = atmel_port->chan_rx;
1098
1099 if (chan) {
1100 dmaengine_terminate_all(chan);
1101 dma_release_channel(chan);
1102 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1103 DMA_FROM_DEVICE);
1104 }
1105
1106 atmel_port->desc_rx = NULL;
1107 atmel_port->chan_rx = NULL;
1108 atmel_port->cookie_rx = -EINVAL;
1109 }
1110
atmel_rx_from_dma(struct uart_port * port)1111 static void atmel_rx_from_dma(struct uart_port *port)
1112 {
1113 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1114 struct tty_port *tport = &port->state->port;
1115 struct circ_buf *ring = &atmel_port->rx_ring;
1116 struct dma_chan *chan = atmel_port->chan_rx;
1117 struct dma_tx_state state;
1118 enum dma_status dmastat;
1119 size_t count;
1120
1121
1122 /* Reset the UART timeout early so that we don't miss one */
1123 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1124 dmastat = dmaengine_tx_status(chan,
1125 atmel_port->cookie_rx,
1126 &state);
1127 /* Restart a new tasklet if DMA status is error */
1128 if (dmastat == DMA_ERROR) {
1129 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1130 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1131 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1132 return;
1133 }
1134
1135 /* CPU claims ownership of RX DMA buffer */
1136 dma_sync_sg_for_cpu(port->dev,
1137 &atmel_port->sg_rx,
1138 1,
1139 DMA_FROM_DEVICE);
1140
1141 /*
1142 * ring->head points to the end of data already written by the DMA.
1143 * ring->tail points to the beginning of data to be read by the
1144 * framework.
1145 * The current transfer size should not be larger than the dma buffer
1146 * length.
1147 */
1148 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1149 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1150 /*
1151 * At this point ring->head may point to the first byte right after the
1152 * last byte of the dma buffer:
1153 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1154 *
1155 * However ring->tail must always points inside the dma buffer:
1156 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1157 *
1158 * Since we use a ring buffer, we have to handle the case
1159 * where head is lower than tail. In such a case, we first read from
1160 * tail to the end of the buffer then reset tail.
1161 */
1162 if (ring->head < ring->tail) {
1163 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1164
1165 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1166 ring->tail = 0;
1167 port->icount.rx += count;
1168 }
1169
1170 /* Finally we read data from tail to head */
1171 if (ring->tail < ring->head) {
1172 count = ring->head - ring->tail;
1173
1174 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1175 /* Wrap ring->head if needed */
1176 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1177 ring->head = 0;
1178 ring->tail = ring->head;
1179 port->icount.rx += count;
1180 }
1181
1182 /* USART retreives ownership of RX DMA buffer */
1183 dma_sync_sg_for_device(port->dev,
1184 &atmel_port->sg_rx,
1185 1,
1186 DMA_FROM_DEVICE);
1187
1188 /*
1189 * Drop the lock here since it might end up calling
1190 * uart_start(), which takes the lock.
1191 */
1192 spin_unlock(&port->lock);
1193 tty_flip_buffer_push(tport);
1194 spin_lock(&port->lock);
1195
1196 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1197 }
1198
atmel_prepare_rx_dma(struct uart_port * port)1199 static int atmel_prepare_rx_dma(struct uart_port *port)
1200 {
1201 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1202 struct device *mfd_dev = port->dev->parent;
1203 struct dma_async_tx_descriptor *desc;
1204 dma_cap_mask_t mask;
1205 struct dma_slave_config config;
1206 struct circ_buf *ring;
1207 int ret, nent;
1208
1209 ring = &atmel_port->rx_ring;
1210
1211 dma_cap_zero(mask);
1212 dma_cap_set(DMA_CYCLIC, mask);
1213
1214 atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx");
1215 if (atmel_port->chan_rx == NULL)
1216 goto chan_err;
1217 dev_info(port->dev, "using %s for rx DMA transfers\n",
1218 dma_chan_name(atmel_port->chan_rx));
1219
1220 spin_lock_init(&atmel_port->lock_rx);
1221 sg_init_table(&atmel_port->sg_rx, 1);
1222 /* UART circular rx buffer is an aligned page. */
1223 BUG_ON(!PAGE_ALIGNED(ring->buf));
1224 sg_set_page(&atmel_port->sg_rx,
1225 virt_to_page(ring->buf),
1226 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1227 offset_in_page(ring->buf));
1228 nent = dma_map_sg(port->dev,
1229 &atmel_port->sg_rx,
1230 1,
1231 DMA_FROM_DEVICE);
1232
1233 if (!nent) {
1234 dev_dbg(port->dev, "need to release resource of dma\n");
1235 goto chan_err;
1236 } else {
1237 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1238 sg_dma_len(&atmel_port->sg_rx),
1239 ring->buf,
1240 &sg_dma_address(&atmel_port->sg_rx));
1241 }
1242
1243 /* Configure the slave DMA */
1244 memset(&config, 0, sizeof(config));
1245 config.direction = DMA_DEV_TO_MEM;
1246 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1247 config.src_addr = port->mapbase + ATMEL_US_RHR;
1248 config.src_maxburst = 1;
1249
1250 ret = dmaengine_slave_config(atmel_port->chan_rx,
1251 &config);
1252 if (ret) {
1253 dev_err(port->dev, "DMA rx slave configuration failed\n");
1254 goto chan_err;
1255 }
1256 /*
1257 * Prepare a cyclic dma transfer, assign 2 descriptors,
1258 * each one is half ring buffer size
1259 */
1260 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1261 sg_dma_address(&atmel_port->sg_rx),
1262 sg_dma_len(&atmel_port->sg_rx),
1263 sg_dma_len(&atmel_port->sg_rx)/2,
1264 DMA_DEV_TO_MEM,
1265 DMA_PREP_INTERRUPT);
1266 if (!desc) {
1267 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1268 goto chan_err;
1269 }
1270 desc->callback = atmel_complete_rx_dma;
1271 desc->callback_param = port;
1272 atmel_port->desc_rx = desc;
1273 atmel_port->cookie_rx = dmaengine_submit(desc);
1274 if (dma_submit_error(atmel_port->cookie_rx)) {
1275 dev_err(port->dev, "dma_submit_error %d\n",
1276 atmel_port->cookie_rx);
1277 goto chan_err;
1278 }
1279
1280 dma_async_issue_pending(atmel_port->chan_rx);
1281
1282 return 0;
1283
1284 chan_err:
1285 dev_err(port->dev, "RX channel not available, switch to pio\n");
1286 atmel_port->use_dma_rx = false;
1287 if (atmel_port->chan_rx)
1288 atmel_release_rx_dma(port);
1289 return -EINVAL;
1290 }
1291
atmel_uart_timer_callback(struct timer_list * t)1292 static void atmel_uart_timer_callback(struct timer_list *t)
1293 {
1294 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1295 uart_timer);
1296 struct uart_port *port = &atmel_port->uart;
1297
1298 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1299 tasklet_schedule(&atmel_port->tasklet_rx);
1300 mod_timer(&atmel_port->uart_timer,
1301 jiffies + uart_poll_timeout(port));
1302 }
1303 }
1304
1305 /*
1306 * receive interrupt handler.
1307 */
1308 static void
atmel_handle_receive(struct uart_port * port,unsigned int pending)1309 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1310 {
1311 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1312
1313 if (atmel_use_pdc_rx(port)) {
1314 /*
1315 * PDC receive. Just schedule the tasklet and let it
1316 * figure out the details.
1317 *
1318 * TODO: We're not handling error flags correctly at
1319 * the moment.
1320 */
1321 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1322 atmel_uart_writel(port, ATMEL_US_IDR,
1323 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1324 atmel_tasklet_schedule(atmel_port,
1325 &atmel_port->tasklet_rx);
1326 }
1327
1328 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1329 ATMEL_US_FRAME | ATMEL_US_PARE))
1330 atmel_pdc_rxerr(port, pending);
1331 }
1332
1333 if (atmel_use_dma_rx(port)) {
1334 if (pending & ATMEL_US_TIMEOUT) {
1335 atmel_uart_writel(port, ATMEL_US_IDR,
1336 ATMEL_US_TIMEOUT);
1337 atmel_tasklet_schedule(atmel_port,
1338 &atmel_port->tasklet_rx);
1339 }
1340 }
1341
1342 /* Interrupt receive */
1343 if (pending & ATMEL_US_RXRDY)
1344 atmel_rx_chars(port);
1345 else if (pending & ATMEL_US_RXBRK) {
1346 /*
1347 * End of break detected. If it came along with a
1348 * character, atmel_rx_chars will handle it.
1349 */
1350 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1351 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1352 atmel_port->break_active = 0;
1353 }
1354 }
1355
1356 /*
1357 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1358 */
1359 static void
atmel_handle_transmit(struct uart_port * port,unsigned int pending)1360 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1361 {
1362 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1363
1364 if (pending & atmel_port->tx_done_mask) {
1365 atmel_uart_writel(port, ATMEL_US_IDR,
1366 atmel_port->tx_done_mask);
1367
1368 /* Start RX if flag was set and FIFO is empty */
1369 if (atmel_port->hd_start_rx) {
1370 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1371 & ATMEL_US_TXEMPTY))
1372 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1373
1374 atmel_port->hd_start_rx = false;
1375 atmel_start_rx(port);
1376 }
1377
1378 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1379 }
1380 }
1381
1382 /*
1383 * status flags interrupt handler.
1384 */
1385 static void
atmel_handle_status(struct uart_port * port,unsigned int pending,unsigned int status)1386 atmel_handle_status(struct uart_port *port, unsigned int pending,
1387 unsigned int status)
1388 {
1389 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1390 unsigned int status_change;
1391
1392 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1393 | ATMEL_US_CTSIC)) {
1394 status_change = status ^ atmel_port->irq_status_prev;
1395 atmel_port->irq_status_prev = status;
1396
1397 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1398 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1399 /* TODO: All reads to CSR will clear these interrupts! */
1400 if (status_change & ATMEL_US_RI)
1401 port->icount.rng++;
1402 if (status_change & ATMEL_US_DSR)
1403 port->icount.dsr++;
1404 if (status_change & ATMEL_US_DCD)
1405 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1406 if (status_change & ATMEL_US_CTS)
1407 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1408
1409 wake_up_interruptible(&port->state->port.delta_msr_wait);
1410 }
1411 }
1412
1413 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
1414 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
1415 }
1416
1417 /*
1418 * Interrupt handler
1419 */
atmel_interrupt(int irq,void * dev_id)1420 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1421 {
1422 struct uart_port *port = dev_id;
1423 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1424 unsigned int status, pending, mask, pass_counter = 0;
1425
1426 spin_lock(&atmel_port->lock_suspended);
1427
1428 do {
1429 status = atmel_uart_readl(port, ATMEL_US_CSR);
1430 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1431 pending = status & mask;
1432 if (!pending)
1433 break;
1434
1435 if (atmel_port->suspended) {
1436 atmel_port->pending |= pending;
1437 atmel_port->pending_status = status;
1438 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1439 pm_system_wakeup();
1440 break;
1441 }
1442
1443 atmel_handle_receive(port, pending);
1444 atmel_handle_status(port, pending, status);
1445 atmel_handle_transmit(port, pending);
1446 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1447
1448 spin_unlock(&atmel_port->lock_suspended);
1449
1450 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1451 }
1452
atmel_release_tx_pdc(struct uart_port * port)1453 static void atmel_release_tx_pdc(struct uart_port *port)
1454 {
1455 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1456 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1457
1458 dma_unmap_single(port->dev,
1459 pdc->dma_addr,
1460 pdc->dma_size,
1461 DMA_TO_DEVICE);
1462 }
1463
1464 /*
1465 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1466 */
atmel_tx_pdc(struct uart_port * port)1467 static void atmel_tx_pdc(struct uart_port *port)
1468 {
1469 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1470 struct circ_buf *xmit = &port->state->xmit;
1471 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1472 int count;
1473
1474 /* nothing left to transmit? */
1475 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1476 return;
1477
1478 xmit->tail += pdc->ofs;
1479 xmit->tail &= UART_XMIT_SIZE - 1;
1480
1481 port->icount.tx += pdc->ofs;
1482 pdc->ofs = 0;
1483
1484 /* more to transmit - setup next transfer */
1485
1486 /* disable PDC transmit */
1487 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1488
1489 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1490 dma_sync_single_for_device(port->dev,
1491 pdc->dma_addr,
1492 pdc->dma_size,
1493 DMA_TO_DEVICE);
1494
1495 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1496 pdc->ofs = count;
1497
1498 atmel_uart_writel(port, ATMEL_PDC_TPR,
1499 pdc->dma_addr + xmit->tail);
1500 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1501 /* re-enable PDC transmit */
1502 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1503 /* Enable interrupts */
1504 atmel_uart_writel(port, ATMEL_US_IER,
1505 atmel_port->tx_done_mask);
1506 } else {
1507 if (atmel_uart_is_half_duplex(port)) {
1508 /* DMA done, stop TX, start RX for RS485 */
1509 atmel_start_rx(port);
1510 }
1511 }
1512
1513 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1514 uart_write_wakeup(port);
1515 }
1516
atmel_prepare_tx_pdc(struct uart_port * port)1517 static int atmel_prepare_tx_pdc(struct uart_port *port)
1518 {
1519 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1520 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1521 struct circ_buf *xmit = &port->state->xmit;
1522
1523 pdc->buf = xmit->buf;
1524 pdc->dma_addr = dma_map_single(port->dev,
1525 pdc->buf,
1526 UART_XMIT_SIZE,
1527 DMA_TO_DEVICE);
1528 pdc->dma_size = UART_XMIT_SIZE;
1529 pdc->ofs = 0;
1530
1531 return 0;
1532 }
1533
atmel_rx_from_ring(struct uart_port * port)1534 static void atmel_rx_from_ring(struct uart_port *port)
1535 {
1536 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1537 struct circ_buf *ring = &atmel_port->rx_ring;
1538 unsigned int flg;
1539 unsigned int status;
1540
1541 while (ring->head != ring->tail) {
1542 struct atmel_uart_char c;
1543
1544 /* Make sure c is loaded after head. */
1545 smp_rmb();
1546
1547 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1548
1549 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1550
1551 port->icount.rx++;
1552 status = c.status;
1553 flg = TTY_NORMAL;
1554
1555 /*
1556 * note that the error handling code is
1557 * out of the main execution path
1558 */
1559 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1560 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1561 if (status & ATMEL_US_RXBRK) {
1562 /* ignore side-effect */
1563 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1564
1565 port->icount.brk++;
1566 if (uart_handle_break(port))
1567 continue;
1568 }
1569 if (status & ATMEL_US_PARE)
1570 port->icount.parity++;
1571 if (status & ATMEL_US_FRAME)
1572 port->icount.frame++;
1573 if (status & ATMEL_US_OVRE)
1574 port->icount.overrun++;
1575
1576 status &= port->read_status_mask;
1577
1578 if (status & ATMEL_US_RXBRK)
1579 flg = TTY_BREAK;
1580 else if (status & ATMEL_US_PARE)
1581 flg = TTY_PARITY;
1582 else if (status & ATMEL_US_FRAME)
1583 flg = TTY_FRAME;
1584 }
1585
1586
1587 if (uart_handle_sysrq_char(port, c.ch))
1588 continue;
1589
1590 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1591 }
1592
1593 /*
1594 * Drop the lock here since it might end up calling
1595 * uart_start(), which takes the lock.
1596 */
1597 spin_unlock(&port->lock);
1598 tty_flip_buffer_push(&port->state->port);
1599 spin_lock(&port->lock);
1600 }
1601
atmel_release_rx_pdc(struct uart_port * port)1602 static void atmel_release_rx_pdc(struct uart_port *port)
1603 {
1604 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1605 int i;
1606
1607 for (i = 0; i < 2; i++) {
1608 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1609
1610 dma_unmap_single(port->dev,
1611 pdc->dma_addr,
1612 pdc->dma_size,
1613 DMA_FROM_DEVICE);
1614 kfree(pdc->buf);
1615 }
1616 }
1617
atmel_rx_from_pdc(struct uart_port * port)1618 static void atmel_rx_from_pdc(struct uart_port *port)
1619 {
1620 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1621 struct tty_port *tport = &port->state->port;
1622 struct atmel_dma_buffer *pdc;
1623 int rx_idx = atmel_port->pdc_rx_idx;
1624 unsigned int head;
1625 unsigned int tail;
1626 unsigned int count;
1627
1628 do {
1629 /* Reset the UART timeout early so that we don't miss one */
1630 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1631
1632 pdc = &atmel_port->pdc_rx[rx_idx];
1633 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1634 tail = pdc->ofs;
1635
1636 /* If the PDC has switched buffers, RPR won't contain
1637 * any address within the current buffer. Since head
1638 * is unsigned, we just need a one-way comparison to
1639 * find out.
1640 *
1641 * In this case, we just need to consume the entire
1642 * buffer and resubmit it for DMA. This will clear the
1643 * ENDRX bit as well, so that we can safely re-enable
1644 * all interrupts below.
1645 */
1646 head = min(head, pdc->dma_size);
1647
1648 if (likely(head != tail)) {
1649 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1650 pdc->dma_size, DMA_FROM_DEVICE);
1651
1652 /*
1653 * head will only wrap around when we recycle
1654 * the DMA buffer, and when that happens, we
1655 * explicitly set tail to 0. So head will
1656 * always be greater than tail.
1657 */
1658 count = head - tail;
1659
1660 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1661 count);
1662
1663 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1664 pdc->dma_size, DMA_FROM_DEVICE);
1665
1666 port->icount.rx += count;
1667 pdc->ofs = head;
1668 }
1669
1670 /*
1671 * If the current buffer is full, we need to check if
1672 * the next one contains any additional data.
1673 */
1674 if (head >= pdc->dma_size) {
1675 pdc->ofs = 0;
1676 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1677 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1678
1679 rx_idx = !rx_idx;
1680 atmel_port->pdc_rx_idx = rx_idx;
1681 }
1682 } while (head >= pdc->dma_size);
1683
1684 /*
1685 * Drop the lock here since it might end up calling
1686 * uart_start(), which takes the lock.
1687 */
1688 spin_unlock(&port->lock);
1689 tty_flip_buffer_push(tport);
1690 spin_lock(&port->lock);
1691
1692 atmel_uart_writel(port, ATMEL_US_IER,
1693 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1694 }
1695
atmel_prepare_rx_pdc(struct uart_port * port)1696 static int atmel_prepare_rx_pdc(struct uart_port *port)
1697 {
1698 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1699 int i;
1700
1701 for (i = 0; i < 2; i++) {
1702 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1703
1704 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1705 if (pdc->buf == NULL) {
1706 if (i != 0) {
1707 dma_unmap_single(port->dev,
1708 atmel_port->pdc_rx[0].dma_addr,
1709 PDC_BUFFER_SIZE,
1710 DMA_FROM_DEVICE);
1711 kfree(atmel_port->pdc_rx[0].buf);
1712 }
1713 atmel_port->use_pdc_rx = false;
1714 return -ENOMEM;
1715 }
1716 pdc->dma_addr = dma_map_single(port->dev,
1717 pdc->buf,
1718 PDC_BUFFER_SIZE,
1719 DMA_FROM_DEVICE);
1720 pdc->dma_size = PDC_BUFFER_SIZE;
1721 pdc->ofs = 0;
1722 }
1723
1724 atmel_port->pdc_rx_idx = 0;
1725
1726 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1727 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1728
1729 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1730 atmel_port->pdc_rx[1].dma_addr);
1731 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1732
1733 return 0;
1734 }
1735
1736 /*
1737 * tasklet handling tty stuff outside the interrupt handler.
1738 */
atmel_tasklet_rx_func(struct tasklet_struct * t)1739 static void atmel_tasklet_rx_func(struct tasklet_struct *t)
1740 {
1741 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1742 tasklet_rx);
1743 struct uart_port *port = &atmel_port->uart;
1744
1745 /* The interrupt handler does not take the lock */
1746 spin_lock(&port->lock);
1747 atmel_port->schedule_rx(port);
1748 spin_unlock(&port->lock);
1749 }
1750
atmel_tasklet_tx_func(struct tasklet_struct * t)1751 static void atmel_tasklet_tx_func(struct tasklet_struct *t)
1752 {
1753 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1754 tasklet_tx);
1755 struct uart_port *port = &atmel_port->uart;
1756
1757 /* The interrupt handler does not take the lock */
1758 spin_lock(&port->lock);
1759 atmel_port->schedule_tx(port);
1760 spin_unlock(&port->lock);
1761 }
1762
atmel_init_property(struct atmel_uart_port * atmel_port,struct platform_device * pdev)1763 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1764 struct platform_device *pdev)
1765 {
1766 struct device_node *np = pdev->dev.of_node;
1767
1768 /* DMA/PDC usage specification */
1769 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1770 if (of_property_read_bool(np, "dmas")) {
1771 atmel_port->use_dma_rx = true;
1772 atmel_port->use_pdc_rx = false;
1773 } else {
1774 atmel_port->use_dma_rx = false;
1775 atmel_port->use_pdc_rx = true;
1776 }
1777 } else {
1778 atmel_port->use_dma_rx = false;
1779 atmel_port->use_pdc_rx = false;
1780 }
1781
1782 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1783 if (of_property_read_bool(np, "dmas")) {
1784 atmel_port->use_dma_tx = true;
1785 atmel_port->use_pdc_tx = false;
1786 } else {
1787 atmel_port->use_dma_tx = false;
1788 atmel_port->use_pdc_tx = true;
1789 }
1790 } else {
1791 atmel_port->use_dma_tx = false;
1792 atmel_port->use_pdc_tx = false;
1793 }
1794 }
1795
atmel_set_ops(struct uart_port * port)1796 static void atmel_set_ops(struct uart_port *port)
1797 {
1798 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1799
1800 if (atmel_use_dma_rx(port)) {
1801 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1802 atmel_port->schedule_rx = &atmel_rx_from_dma;
1803 atmel_port->release_rx = &atmel_release_rx_dma;
1804 } else if (atmel_use_pdc_rx(port)) {
1805 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1806 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1807 atmel_port->release_rx = &atmel_release_rx_pdc;
1808 } else {
1809 atmel_port->prepare_rx = NULL;
1810 atmel_port->schedule_rx = &atmel_rx_from_ring;
1811 atmel_port->release_rx = NULL;
1812 }
1813
1814 if (atmel_use_dma_tx(port)) {
1815 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1816 atmel_port->schedule_tx = &atmel_tx_dma;
1817 atmel_port->release_tx = &atmel_release_tx_dma;
1818 } else if (atmel_use_pdc_tx(port)) {
1819 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1820 atmel_port->schedule_tx = &atmel_tx_pdc;
1821 atmel_port->release_tx = &atmel_release_tx_pdc;
1822 } else {
1823 atmel_port->prepare_tx = NULL;
1824 atmel_port->schedule_tx = &atmel_tx_chars;
1825 atmel_port->release_tx = NULL;
1826 }
1827 }
1828
1829 /*
1830 * Get ip name usart or uart
1831 */
atmel_get_ip_name(struct uart_port * port)1832 static void atmel_get_ip_name(struct uart_port *port)
1833 {
1834 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1835 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1836 u32 version;
1837 u32 usart, dbgu_uart, new_uart;
1838 /* ASCII decoding for IP version */
1839 usart = 0x55534152; /* USAR(T) */
1840 dbgu_uart = 0x44424755; /* DBGU */
1841 new_uart = 0x55415254; /* UART */
1842
1843 /*
1844 * Only USART devices from at91sam9260 SOC implement fractional
1845 * baudrate. It is available for all asynchronous modes, with the
1846 * following restriction: the sampling clock's duty cycle is not
1847 * constant.
1848 */
1849 atmel_port->has_frac_baudrate = false;
1850 atmel_port->has_hw_timer = false;
1851
1852 if (name == new_uart) {
1853 dev_dbg(port->dev, "Uart with hw timer");
1854 atmel_port->has_hw_timer = true;
1855 atmel_port->rtor = ATMEL_UA_RTOR;
1856 } else if (name == usart) {
1857 dev_dbg(port->dev, "Usart\n");
1858 atmel_port->has_frac_baudrate = true;
1859 atmel_port->has_hw_timer = true;
1860 atmel_port->rtor = ATMEL_US_RTOR;
1861 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1862 switch (version) {
1863 case 0x814: /* sama5d2 */
1864 fallthrough;
1865 case 0x701: /* sama5d4 */
1866 atmel_port->fidi_min = 3;
1867 atmel_port->fidi_max = 65535;
1868 break;
1869 case 0x502: /* sam9x5, sama5d3 */
1870 atmel_port->fidi_min = 3;
1871 atmel_port->fidi_max = 2047;
1872 break;
1873 default:
1874 atmel_port->fidi_min = 1;
1875 atmel_port->fidi_max = 2047;
1876 }
1877 } else if (name == dbgu_uart) {
1878 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1879 } else {
1880 /* fallback for older SoCs: use version field */
1881 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1882 switch (version) {
1883 case 0x302:
1884 case 0x10213:
1885 case 0x10302:
1886 dev_dbg(port->dev, "This version is usart\n");
1887 atmel_port->has_frac_baudrate = true;
1888 atmel_port->has_hw_timer = true;
1889 atmel_port->rtor = ATMEL_US_RTOR;
1890 break;
1891 case 0x203:
1892 case 0x10202:
1893 dev_dbg(port->dev, "This version is uart\n");
1894 break;
1895 default:
1896 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1897 }
1898 }
1899 }
1900
1901 /*
1902 * Perform initialization and enable port for reception
1903 */
atmel_startup(struct uart_port * port)1904 static int atmel_startup(struct uart_port *port)
1905 {
1906 struct platform_device *pdev = to_platform_device(port->dev);
1907 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1908 int retval;
1909
1910 /*
1911 * Ensure that no interrupts are enabled otherwise when
1912 * request_irq() is called we could get stuck trying to
1913 * handle an unexpected interrupt
1914 */
1915 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1916 atmel_port->ms_irq_enabled = false;
1917
1918 /*
1919 * Allocate the IRQ
1920 */
1921 retval = request_irq(port->irq, atmel_interrupt,
1922 IRQF_SHARED | IRQF_COND_SUSPEND,
1923 dev_name(&pdev->dev), port);
1924 if (retval) {
1925 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1926 return retval;
1927 }
1928
1929 atomic_set(&atmel_port->tasklet_shutdown, 0);
1930 tasklet_setup(&atmel_port->tasklet_rx, atmel_tasklet_rx_func);
1931 tasklet_setup(&atmel_port->tasklet_tx, atmel_tasklet_tx_func);
1932
1933 /*
1934 * Initialize DMA (if necessary)
1935 */
1936 atmel_init_property(atmel_port, pdev);
1937 atmel_set_ops(port);
1938
1939 if (atmel_port->prepare_rx) {
1940 retval = atmel_port->prepare_rx(port);
1941 if (retval < 0)
1942 atmel_set_ops(port);
1943 }
1944
1945 if (atmel_port->prepare_tx) {
1946 retval = atmel_port->prepare_tx(port);
1947 if (retval < 0)
1948 atmel_set_ops(port);
1949 }
1950
1951 /*
1952 * Enable FIFO when available
1953 */
1954 if (atmel_port->fifo_size) {
1955 unsigned int txrdym = ATMEL_US_ONE_DATA;
1956 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1957 unsigned int fmr;
1958
1959 atmel_uart_writel(port, ATMEL_US_CR,
1960 ATMEL_US_FIFOEN |
1961 ATMEL_US_RXFCLR |
1962 ATMEL_US_TXFLCLR);
1963
1964 if (atmel_use_dma_tx(port))
1965 txrdym = ATMEL_US_FOUR_DATA;
1966
1967 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1968 if (atmel_port->rts_high &&
1969 atmel_port->rts_low)
1970 fmr |= ATMEL_US_FRTSC |
1971 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1972 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1973
1974 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1975 }
1976
1977 /* Save current CSR for comparison in atmel_tasklet_func() */
1978 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
1979
1980 /*
1981 * Finally, enable the serial port
1982 */
1983 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1984 /* enable xmit & rcvr */
1985 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1986 atmel_port->tx_stopped = false;
1987
1988 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
1989
1990 if (atmel_use_pdc_rx(port)) {
1991 /* set UART timeout */
1992 if (!atmel_port->has_hw_timer) {
1993 mod_timer(&atmel_port->uart_timer,
1994 jiffies + uart_poll_timeout(port));
1995 /* set USART timeout */
1996 } else {
1997 atmel_uart_writel(port, atmel_port->rtor,
1998 PDC_RX_TIMEOUT);
1999 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
2000
2001 atmel_uart_writel(port, ATMEL_US_IER,
2002 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
2003 }
2004 /* enable PDC controller */
2005 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
2006 } else if (atmel_use_dma_rx(port)) {
2007 /* set UART timeout */
2008 if (!atmel_port->has_hw_timer) {
2009 mod_timer(&atmel_port->uart_timer,
2010 jiffies + uart_poll_timeout(port));
2011 /* set USART timeout */
2012 } else {
2013 atmel_uart_writel(port, atmel_port->rtor,
2014 PDC_RX_TIMEOUT);
2015 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
2016
2017 atmel_uart_writel(port, ATMEL_US_IER,
2018 ATMEL_US_TIMEOUT);
2019 }
2020 } else {
2021 /* enable receive only */
2022 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
2023 }
2024
2025 return 0;
2026 }
2027
2028 /*
2029 * Flush any TX data submitted for DMA. Called when the TX circular
2030 * buffer is reset.
2031 */
atmel_flush_buffer(struct uart_port * port)2032 static void atmel_flush_buffer(struct uart_port *port)
2033 {
2034 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2035
2036 if (atmel_use_pdc_tx(port)) {
2037 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
2038 atmel_port->pdc_tx.ofs = 0;
2039 }
2040 /*
2041 * in uart_flush_buffer(), the xmit circular buffer has just
2042 * been cleared, so we have to reset tx_len accordingly.
2043 */
2044 atmel_port->tx_len = 0;
2045 }
2046
2047 /*
2048 * Disable the port
2049 */
atmel_shutdown(struct uart_port * port)2050 static void atmel_shutdown(struct uart_port *port)
2051 {
2052 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2053
2054 /* Disable modem control lines interrupts */
2055 atmel_disable_ms(port);
2056
2057 /* Disable interrupts at device level */
2058 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2059
2060 /* Prevent spurious interrupts from scheduling the tasklet */
2061 atomic_inc(&atmel_port->tasklet_shutdown);
2062
2063 /*
2064 * Prevent any tasklets being scheduled during
2065 * cleanup
2066 */
2067 del_timer_sync(&atmel_port->uart_timer);
2068
2069 /* Make sure that no interrupt is on the fly */
2070 synchronize_irq(port->irq);
2071
2072 /*
2073 * Clear out any scheduled tasklets before
2074 * we destroy the buffers
2075 */
2076 tasklet_kill(&atmel_port->tasklet_rx);
2077 tasklet_kill(&atmel_port->tasklet_tx);
2078
2079 /*
2080 * Ensure everything is stopped and
2081 * disable port and break condition.
2082 */
2083 atmel_stop_rx(port);
2084 atmel_stop_tx(port);
2085
2086 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2087
2088 /*
2089 * Shut-down the DMA.
2090 */
2091 if (atmel_port->release_rx)
2092 atmel_port->release_rx(port);
2093 if (atmel_port->release_tx)
2094 atmel_port->release_tx(port);
2095
2096 /*
2097 * Reset ring buffer pointers
2098 */
2099 atmel_port->rx_ring.head = 0;
2100 atmel_port->rx_ring.tail = 0;
2101
2102 /*
2103 * Free the interrupts
2104 */
2105 free_irq(port->irq, port);
2106
2107 atmel_flush_buffer(port);
2108 }
2109
2110 /*
2111 * Power / Clock management.
2112 */
atmel_serial_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)2113 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2114 unsigned int oldstate)
2115 {
2116 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2117
2118 switch (state) {
2119 case 0:
2120 /*
2121 * Enable the peripheral clock for this serial port.
2122 * This is called on uart_open() or a resume event.
2123 */
2124 clk_prepare_enable(atmel_port->clk);
2125
2126 /* re-enable interrupts if we disabled some on suspend */
2127 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2128 break;
2129 case 3:
2130 /* Back up the interrupt mask and disable all interrupts */
2131 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2132 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2133
2134 /*
2135 * Disable the peripheral clock for this serial port.
2136 * This is called on uart_close() or a suspend event.
2137 */
2138 clk_disable_unprepare(atmel_port->clk);
2139 break;
2140 default:
2141 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2142 }
2143 }
2144
2145 /*
2146 * Change the port parameters
2147 */
atmel_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)2148 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2149 struct ktermios *old)
2150 {
2151 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2152 unsigned long flags;
2153 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2154
2155 /* save the current mode register */
2156 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2157
2158 /* reset the mode, clock divisor, parity, stop bits and data size */
2159 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2160 ATMEL_US_PAR | ATMEL_US_USMODE);
2161
2162 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2163
2164 /* byte size */
2165 switch (termios->c_cflag & CSIZE) {
2166 case CS5:
2167 mode |= ATMEL_US_CHRL_5;
2168 break;
2169 case CS6:
2170 mode |= ATMEL_US_CHRL_6;
2171 break;
2172 case CS7:
2173 mode |= ATMEL_US_CHRL_7;
2174 break;
2175 default:
2176 mode |= ATMEL_US_CHRL_8;
2177 break;
2178 }
2179
2180 /* stop bits */
2181 if (termios->c_cflag & CSTOPB)
2182 mode |= ATMEL_US_NBSTOP_2;
2183
2184 /* parity */
2185 if (termios->c_cflag & PARENB) {
2186 /* Mark or Space parity */
2187 if (termios->c_cflag & CMSPAR) {
2188 if (termios->c_cflag & PARODD)
2189 mode |= ATMEL_US_PAR_MARK;
2190 else
2191 mode |= ATMEL_US_PAR_SPACE;
2192 } else if (termios->c_cflag & PARODD)
2193 mode |= ATMEL_US_PAR_ODD;
2194 else
2195 mode |= ATMEL_US_PAR_EVEN;
2196 } else
2197 mode |= ATMEL_US_PAR_NONE;
2198
2199 spin_lock_irqsave(&port->lock, flags);
2200
2201 port->read_status_mask = ATMEL_US_OVRE;
2202 if (termios->c_iflag & INPCK)
2203 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2204 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2205 port->read_status_mask |= ATMEL_US_RXBRK;
2206
2207 if (atmel_use_pdc_rx(port))
2208 /* need to enable error interrupts */
2209 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2210
2211 /*
2212 * Characters to ignore
2213 */
2214 port->ignore_status_mask = 0;
2215 if (termios->c_iflag & IGNPAR)
2216 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2217 if (termios->c_iflag & IGNBRK) {
2218 port->ignore_status_mask |= ATMEL_US_RXBRK;
2219 /*
2220 * If we're ignoring parity and break indicators,
2221 * ignore overruns too (for real raw support).
2222 */
2223 if (termios->c_iflag & IGNPAR)
2224 port->ignore_status_mask |= ATMEL_US_OVRE;
2225 }
2226 /* TODO: Ignore all characters if CREAD is set.*/
2227
2228 /* update the per-port timeout */
2229 uart_update_timeout(port, termios->c_cflag, baud);
2230
2231 /*
2232 * save/disable interrupts. The tty layer will ensure that the
2233 * transmitter is empty if requested by the caller, so there's
2234 * no need to wait for it here.
2235 */
2236 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2237 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2238
2239 /* disable receiver and transmitter */
2240 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2241 atmel_port->tx_stopped = true;
2242
2243 /* mode */
2244 if (port->rs485.flags & SER_RS485_ENABLED) {
2245 atmel_uart_writel(port, ATMEL_US_TTGR,
2246 port->rs485.delay_rts_after_send);
2247 mode |= ATMEL_US_USMODE_RS485;
2248 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2249 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2250 /* select mck clock, and output */
2251 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
2252 /* set max iterations */
2253 mode |= ATMEL_US_MAX_ITER(3);
2254 if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2255 == SER_ISO7816_T(0))
2256 mode |= ATMEL_US_USMODE_ISO7816_T0;
2257 else
2258 mode |= ATMEL_US_USMODE_ISO7816_T1;
2259 } else if (termios->c_cflag & CRTSCTS) {
2260 /* RS232 with hardware handshake (RTS/CTS) */
2261 if (atmel_use_fifo(port) &&
2262 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2263 /*
2264 * with ATMEL_US_USMODE_HWHS set, the controller will
2265 * be able to drive the RTS pin high/low when the RX
2266 * FIFO is above RXFTHRES/below RXFTHRES2.
2267 * It will also disable the transmitter when the CTS
2268 * pin is high.
2269 * This mode is not activated if CTS pin is a GPIO
2270 * because in this case, the transmitter is always
2271 * disabled (there must be an internal pull-up
2272 * responsible for this behaviour).
2273 * If the RTS pin is a GPIO, the controller won't be
2274 * able to drive it according to the FIFO thresholds,
2275 * but it will be handled by the driver.
2276 */
2277 mode |= ATMEL_US_USMODE_HWHS;
2278 } else {
2279 /*
2280 * For platforms without FIFO, the flow control is
2281 * handled by the driver.
2282 */
2283 mode |= ATMEL_US_USMODE_NORMAL;
2284 }
2285 } else {
2286 /* RS232 without hadware handshake */
2287 mode |= ATMEL_US_USMODE_NORMAL;
2288 }
2289
2290 /*
2291 * Set the baud rate:
2292 * Fractional baudrate allows to setup output frequency more
2293 * accurately. This feature is enabled only when using normal mode.
2294 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2295 * Currently, OVER is always set to 0 so we get
2296 * baudrate = selected clock / (16 * (CD + FP / 8))
2297 * then
2298 * 8 CD + FP = selected clock / (2 * baudrate)
2299 */
2300 if (atmel_port->has_frac_baudrate) {
2301 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2302 cd = div >> 3;
2303 fp = div & ATMEL_US_FP_MASK;
2304 } else {
2305 cd = uart_get_divisor(port, baud);
2306 }
2307
2308 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2309 cd /= 8;
2310 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2311 }
2312 quot = cd | fp << ATMEL_US_FP_OFFSET;
2313
2314 if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2315 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2316
2317 /* set the mode, clock divisor, parity, stop bits and data size */
2318 atmel_uart_writel(port, ATMEL_US_MR, mode);
2319
2320 /*
2321 * when switching the mode, set the RTS line state according to the
2322 * new mode, otherwise keep the former state
2323 */
2324 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2325 unsigned int rts_state;
2326
2327 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2328 /* let the hardware control the RTS line */
2329 rts_state = ATMEL_US_RTSDIS;
2330 } else {
2331 /* force RTS line to low level */
2332 rts_state = ATMEL_US_RTSEN;
2333 }
2334
2335 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2336 }
2337
2338 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2339 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2340 atmel_port->tx_stopped = false;
2341
2342 /* restore interrupts */
2343 atmel_uart_writel(port, ATMEL_US_IER, imr);
2344
2345 /* CTS flow-control and modem-status interrupts */
2346 if (UART_ENABLE_MS(port, termios->c_cflag))
2347 atmel_enable_ms(port);
2348 else
2349 atmel_disable_ms(port);
2350
2351 spin_unlock_irqrestore(&port->lock, flags);
2352 }
2353
atmel_set_ldisc(struct uart_port * port,struct ktermios * termios)2354 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2355 {
2356 if (termios->c_line == N_PPS) {
2357 port->flags |= UPF_HARDPPS_CD;
2358 spin_lock_irq(&port->lock);
2359 atmel_enable_ms(port);
2360 spin_unlock_irq(&port->lock);
2361 } else {
2362 port->flags &= ~UPF_HARDPPS_CD;
2363 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2364 spin_lock_irq(&port->lock);
2365 atmel_disable_ms(port);
2366 spin_unlock_irq(&port->lock);
2367 }
2368 }
2369 }
2370
2371 /*
2372 * Return string describing the specified port
2373 */
atmel_type(struct uart_port * port)2374 static const char *atmel_type(struct uart_port *port)
2375 {
2376 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2377 }
2378
2379 /*
2380 * Release the memory region(s) being used by 'port'.
2381 */
atmel_release_port(struct uart_port * port)2382 static void atmel_release_port(struct uart_port *port)
2383 {
2384 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2385 int size = resource_size(mpdev->resource);
2386
2387 release_mem_region(port->mapbase, size);
2388
2389 if (port->flags & UPF_IOREMAP) {
2390 iounmap(port->membase);
2391 port->membase = NULL;
2392 }
2393 }
2394
2395 /*
2396 * Request the memory region(s) being used by 'port'.
2397 */
atmel_request_port(struct uart_port * port)2398 static int atmel_request_port(struct uart_port *port)
2399 {
2400 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2401 int size = resource_size(mpdev->resource);
2402
2403 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2404 return -EBUSY;
2405
2406 if (port->flags & UPF_IOREMAP) {
2407 port->membase = ioremap(port->mapbase, size);
2408 if (port->membase == NULL) {
2409 release_mem_region(port->mapbase, size);
2410 return -ENOMEM;
2411 }
2412 }
2413
2414 return 0;
2415 }
2416
2417 /*
2418 * Configure/autoconfigure the port.
2419 */
atmel_config_port(struct uart_port * port,int flags)2420 static void atmel_config_port(struct uart_port *port, int flags)
2421 {
2422 if (flags & UART_CONFIG_TYPE) {
2423 port->type = PORT_ATMEL;
2424 atmel_request_port(port);
2425 }
2426 }
2427
2428 /*
2429 * Verify the new serial_struct (for TIOCSSERIAL).
2430 */
atmel_verify_port(struct uart_port * port,struct serial_struct * ser)2431 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2432 {
2433 int ret = 0;
2434 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2435 ret = -EINVAL;
2436 if (port->irq != ser->irq)
2437 ret = -EINVAL;
2438 if (ser->io_type != SERIAL_IO_MEM)
2439 ret = -EINVAL;
2440 if (port->uartclk / 16 != ser->baud_base)
2441 ret = -EINVAL;
2442 if (port->mapbase != (unsigned long)ser->iomem_base)
2443 ret = -EINVAL;
2444 if (port->iobase != ser->port)
2445 ret = -EINVAL;
2446 if (ser->hub6 != 0)
2447 ret = -EINVAL;
2448 return ret;
2449 }
2450
2451 #ifdef CONFIG_CONSOLE_POLL
atmel_poll_get_char(struct uart_port * port)2452 static int atmel_poll_get_char(struct uart_port *port)
2453 {
2454 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2455 cpu_relax();
2456
2457 return atmel_uart_read_char(port);
2458 }
2459
atmel_poll_put_char(struct uart_port * port,unsigned char ch)2460 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2461 {
2462 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2463 cpu_relax();
2464
2465 atmel_uart_write_char(port, ch);
2466 }
2467 #endif
2468
2469 static const struct uart_ops atmel_pops = {
2470 .tx_empty = atmel_tx_empty,
2471 .set_mctrl = atmel_set_mctrl,
2472 .get_mctrl = atmel_get_mctrl,
2473 .stop_tx = atmel_stop_tx,
2474 .start_tx = atmel_start_tx,
2475 .stop_rx = atmel_stop_rx,
2476 .enable_ms = atmel_enable_ms,
2477 .break_ctl = atmel_break_ctl,
2478 .startup = atmel_startup,
2479 .shutdown = atmel_shutdown,
2480 .flush_buffer = atmel_flush_buffer,
2481 .set_termios = atmel_set_termios,
2482 .set_ldisc = atmel_set_ldisc,
2483 .type = atmel_type,
2484 .release_port = atmel_release_port,
2485 .request_port = atmel_request_port,
2486 .config_port = atmel_config_port,
2487 .verify_port = atmel_verify_port,
2488 .pm = atmel_serial_pm,
2489 #ifdef CONFIG_CONSOLE_POLL
2490 .poll_get_char = atmel_poll_get_char,
2491 .poll_put_char = atmel_poll_put_char,
2492 #endif
2493 };
2494
2495 /*
2496 * Configure the port from the platform device resource info.
2497 */
atmel_init_port(struct atmel_uart_port * atmel_port,struct platform_device * pdev)2498 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2499 struct platform_device *pdev)
2500 {
2501 int ret;
2502 struct uart_port *port = &atmel_port->uart;
2503 struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
2504
2505 atmel_init_property(atmel_port, pdev);
2506 atmel_set_ops(port);
2507
2508 port->iotype = UPIO_MEM;
2509 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2510 port->ops = &atmel_pops;
2511 port->fifosize = 1;
2512 port->dev = &pdev->dev;
2513 port->mapbase = mpdev->resource[0].start;
2514 port->irq = mpdev->resource[1].start;
2515 port->rs485_config = atmel_config_rs485;
2516 port->iso7816_config = atmel_config_iso7816;
2517 port->membase = NULL;
2518
2519 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2520
2521 ret = uart_get_rs485_mode(port);
2522 if (ret)
2523 return ret;
2524
2525 /* for console, the clock could already be configured */
2526 if (!atmel_port->clk) {
2527 atmel_port->clk = clk_get(&mpdev->dev, "usart");
2528 if (IS_ERR(atmel_port->clk)) {
2529 ret = PTR_ERR(atmel_port->clk);
2530 atmel_port->clk = NULL;
2531 return ret;
2532 }
2533 ret = clk_prepare_enable(atmel_port->clk);
2534 if (ret) {
2535 clk_put(atmel_port->clk);
2536 atmel_port->clk = NULL;
2537 return ret;
2538 }
2539 port->uartclk = clk_get_rate(atmel_port->clk);
2540 clk_disable_unprepare(atmel_port->clk);
2541 /* only enable clock when USART is in use */
2542 }
2543
2544 /*
2545 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
2546 * ENDTX|TXBUFE
2547 */
2548 if (atmel_uart_is_half_duplex(port))
2549 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2550 else if (atmel_use_pdc_tx(port)) {
2551 port->fifosize = PDC_BUFFER_SIZE;
2552 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2553 } else {
2554 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2555 }
2556
2557 return 0;
2558 }
2559
2560 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
atmel_console_putchar(struct uart_port * port,int ch)2561 static void atmel_console_putchar(struct uart_port *port, int ch)
2562 {
2563 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2564 cpu_relax();
2565 atmel_uart_write_char(port, ch);
2566 }
2567
2568 /*
2569 * Interrupts are disabled on entering
2570 */
atmel_console_write(struct console * co,const char * s,u_int count)2571 static void atmel_console_write(struct console *co, const char *s, u_int count)
2572 {
2573 struct uart_port *port = &atmel_ports[co->index].uart;
2574 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2575 unsigned int status, imr;
2576 unsigned int pdc_tx;
2577
2578 /*
2579 * First, save IMR and then disable interrupts
2580 */
2581 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2582 atmel_uart_writel(port, ATMEL_US_IDR,
2583 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2584
2585 /* Store PDC transmit status and disable it */
2586 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2587 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2588
2589 /* Make sure that tx path is actually able to send characters */
2590 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2591 atmel_port->tx_stopped = false;
2592
2593 uart_console_write(port, s, count, atmel_console_putchar);
2594
2595 /*
2596 * Finally, wait for transmitter to become empty
2597 * and restore IMR
2598 */
2599 do {
2600 status = atmel_uart_readl(port, ATMEL_US_CSR);
2601 } while (!(status & ATMEL_US_TXRDY));
2602
2603 /* Restore PDC transmit status */
2604 if (pdc_tx)
2605 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2606
2607 /* set interrupts back the way they were */
2608 atmel_uart_writel(port, ATMEL_US_IER, imr);
2609 }
2610
2611 /*
2612 * If the port was already initialised (eg, by a boot loader),
2613 * try to determine the current setup.
2614 */
atmel_console_get_options(struct uart_port * port,int * baud,int * parity,int * bits)2615 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2616 int *parity, int *bits)
2617 {
2618 unsigned int mr, quot;
2619
2620 /*
2621 * If the baud rate generator isn't running, the port wasn't
2622 * initialized by the boot loader.
2623 */
2624 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2625 if (!quot)
2626 return;
2627
2628 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2629 if (mr == ATMEL_US_CHRL_8)
2630 *bits = 8;
2631 else
2632 *bits = 7;
2633
2634 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2635 if (mr == ATMEL_US_PAR_EVEN)
2636 *parity = 'e';
2637 else if (mr == ATMEL_US_PAR_ODD)
2638 *parity = 'o';
2639
2640 /*
2641 * The serial core only rounds down when matching this to a
2642 * supported baud rate. Make sure we don't end up slightly
2643 * lower than one of those, as it would make us fall through
2644 * to a much lower baud rate than we really want.
2645 */
2646 *baud = port->uartclk / (16 * (quot - 1));
2647 }
2648
atmel_console_setup(struct console * co,char * options)2649 static int __init atmel_console_setup(struct console *co, char *options)
2650 {
2651 int ret;
2652 struct uart_port *port = &atmel_ports[co->index].uart;
2653 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2654 int baud = 115200;
2655 int bits = 8;
2656 int parity = 'n';
2657 int flow = 'n';
2658
2659 if (port->membase == NULL) {
2660 /* Port not initialized yet - delay setup */
2661 return -ENODEV;
2662 }
2663
2664 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2665 if (ret)
2666 return ret;
2667
2668 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2669 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2670 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2671 atmel_port->tx_stopped = false;
2672
2673 if (options)
2674 uart_parse_options(options, &baud, &parity, &bits, &flow);
2675 else
2676 atmel_console_get_options(port, &baud, &parity, &bits);
2677
2678 return uart_set_options(port, co, baud, parity, bits, flow);
2679 }
2680
2681 static struct uart_driver atmel_uart;
2682
2683 static struct console atmel_console = {
2684 .name = ATMEL_DEVICENAME,
2685 .write = atmel_console_write,
2686 .device = uart_console_device,
2687 .setup = atmel_console_setup,
2688 .flags = CON_PRINTBUFFER,
2689 .index = -1,
2690 .data = &atmel_uart,
2691 };
2692
2693 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2694
2695 #else
2696 #define ATMEL_CONSOLE_DEVICE NULL
2697 #endif
2698
2699 static struct uart_driver atmel_uart = {
2700 .owner = THIS_MODULE,
2701 .driver_name = "atmel_serial",
2702 .dev_name = ATMEL_DEVICENAME,
2703 .major = SERIAL_ATMEL_MAJOR,
2704 .minor = MINOR_START,
2705 .nr = ATMEL_MAX_UART,
2706 .cons = ATMEL_CONSOLE_DEVICE,
2707 };
2708
2709 #ifdef CONFIG_PM
atmel_serial_clk_will_stop(void)2710 static bool atmel_serial_clk_will_stop(void)
2711 {
2712 #ifdef CONFIG_ARCH_AT91
2713 return at91_suspend_entering_slow_clock();
2714 #else
2715 return false;
2716 #endif
2717 }
2718
atmel_serial_suspend(struct platform_device * pdev,pm_message_t state)2719 static int atmel_serial_suspend(struct platform_device *pdev,
2720 pm_message_t state)
2721 {
2722 struct uart_port *port = platform_get_drvdata(pdev);
2723 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2724
2725 if (uart_console(port) && console_suspend_enabled) {
2726 /* Drain the TX shifter */
2727 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2728 ATMEL_US_TXEMPTY))
2729 cpu_relax();
2730 }
2731
2732 if (uart_console(port) && !console_suspend_enabled) {
2733 /* Cache register values as we won't get a full shutdown/startup
2734 * cycle
2735 */
2736 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2737 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2738 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2739 atmel_port->cache.rtor = atmel_uart_readl(port,
2740 atmel_port->rtor);
2741 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2742 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2743 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2744 }
2745
2746 /* we can not wake up if we're running on slow clock */
2747 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2748 if (atmel_serial_clk_will_stop()) {
2749 unsigned long flags;
2750
2751 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2752 atmel_port->suspended = true;
2753 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2754 device_set_wakeup_enable(&pdev->dev, 0);
2755 }
2756
2757 uart_suspend_port(&atmel_uart, port);
2758
2759 return 0;
2760 }
2761
atmel_serial_resume(struct platform_device * pdev)2762 static int atmel_serial_resume(struct platform_device *pdev)
2763 {
2764 struct uart_port *port = platform_get_drvdata(pdev);
2765 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2766 unsigned long flags;
2767
2768 if (uart_console(port) && !console_suspend_enabled) {
2769 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2770 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2771 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2772 atmel_uart_writel(port, atmel_port->rtor,
2773 atmel_port->cache.rtor);
2774 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2775
2776 if (atmel_port->fifo_size) {
2777 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2778 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2779 atmel_uart_writel(port, ATMEL_US_FMR,
2780 atmel_port->cache.fmr);
2781 atmel_uart_writel(port, ATMEL_US_FIER,
2782 atmel_port->cache.fimr);
2783 }
2784 atmel_start_rx(port);
2785 }
2786
2787 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2788 if (atmel_port->pending) {
2789 atmel_handle_receive(port, atmel_port->pending);
2790 atmel_handle_status(port, atmel_port->pending,
2791 atmel_port->pending_status);
2792 atmel_handle_transmit(port, atmel_port->pending);
2793 atmel_port->pending = 0;
2794 }
2795 atmel_port->suspended = false;
2796 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2797
2798 uart_resume_port(&atmel_uart, port);
2799 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2800
2801 return 0;
2802 }
2803 #else
2804 #define atmel_serial_suspend NULL
2805 #define atmel_serial_resume NULL
2806 #endif
2807
atmel_serial_probe_fifos(struct atmel_uart_port * atmel_port,struct platform_device * pdev)2808 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2809 struct platform_device *pdev)
2810 {
2811 atmel_port->fifo_size = 0;
2812 atmel_port->rts_low = 0;
2813 atmel_port->rts_high = 0;
2814
2815 if (of_property_read_u32(pdev->dev.of_node,
2816 "atmel,fifo-size",
2817 &atmel_port->fifo_size))
2818 return;
2819
2820 if (!atmel_port->fifo_size)
2821 return;
2822
2823 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2824 atmel_port->fifo_size = 0;
2825 dev_err(&pdev->dev, "Invalid FIFO size\n");
2826 return;
2827 }
2828
2829 /*
2830 * 0 <= rts_low <= rts_high <= fifo_size
2831 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2832 * to flush their internal TX FIFO, commonly up to 16 data, before
2833 * actually stopping to send new data. So we try to set the RTS High
2834 * Threshold to a reasonably high value respecting this 16 data
2835 * empirical rule when possible.
2836 */
2837 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2838 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2839 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2840 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2841
2842 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2843 atmel_port->fifo_size);
2844 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2845 atmel_port->rts_high);
2846 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2847 atmel_port->rts_low);
2848 }
2849
atmel_serial_probe(struct platform_device * pdev)2850 static int atmel_serial_probe(struct platform_device *pdev)
2851 {
2852 struct atmel_uart_port *atmel_port;
2853 struct device_node *np = pdev->dev.parent->of_node;
2854 void *data;
2855 int ret;
2856 bool rs485_enabled;
2857
2858 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2859
2860 /*
2861 * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2862 * as compatible string. This driver is probed by at91-usart mfd driver
2863 * which is just a wrapper over the atmel_serial driver and
2864 * spi-at91-usart driver. All attributes needed by this driver are
2865 * found in of_node of parent.
2866 */
2867 pdev->dev.of_node = np;
2868
2869 ret = of_alias_get_id(np, "serial");
2870 if (ret < 0)
2871 /* port id not found in platform data nor device-tree aliases:
2872 * auto-enumerate it */
2873 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2874
2875 if (ret >= ATMEL_MAX_UART) {
2876 ret = -ENODEV;
2877 goto err;
2878 }
2879
2880 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2881 /* port already in use */
2882 ret = -EBUSY;
2883 goto err;
2884 }
2885
2886 atmel_port = &atmel_ports[ret];
2887 atmel_port->backup_imr = 0;
2888 atmel_port->uart.line = ret;
2889 atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE);
2890 atmel_serial_probe_fifos(atmel_port, pdev);
2891
2892 atomic_set(&atmel_port->tasklet_shutdown, 0);
2893 spin_lock_init(&atmel_port->lock_suspended);
2894
2895 ret = atmel_init_port(atmel_port, pdev);
2896 if (ret)
2897 goto err_clear_bit;
2898
2899 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2900 if (IS_ERR(atmel_port->gpios)) {
2901 ret = PTR_ERR(atmel_port->gpios);
2902 goto err_clear_bit;
2903 }
2904
2905 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2906 ret = -ENOMEM;
2907 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2908 sizeof(struct atmel_uart_char),
2909 GFP_KERNEL);
2910 if (!data)
2911 goto err_alloc_ring;
2912 atmel_port->rx_ring.buf = data;
2913 }
2914
2915 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2916
2917 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2918 if (ret)
2919 goto err_add_port;
2920
2921 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2922 if (uart_console(&atmel_port->uart)
2923 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2924 /*
2925 * The serial core enabled the clock for us, so undo
2926 * the clk_prepare_enable() in atmel_console_setup()
2927 */
2928 clk_disable_unprepare(atmel_port->clk);
2929 }
2930 #endif
2931
2932 device_init_wakeup(&pdev->dev, 1);
2933 platform_set_drvdata(pdev, atmel_port);
2934
2935 /*
2936 * The peripheral clock has been disabled by atmel_init_port():
2937 * enable it before accessing I/O registers
2938 */
2939 clk_prepare_enable(atmel_port->clk);
2940
2941 if (rs485_enabled) {
2942 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2943 ATMEL_US_USMODE_NORMAL);
2944 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2945 ATMEL_US_RTSEN);
2946 }
2947
2948 /*
2949 * Get port name of usart or uart
2950 */
2951 atmel_get_ip_name(&atmel_port->uart);
2952
2953 /*
2954 * The peripheral clock can now safely be disabled till the port
2955 * is used
2956 */
2957 clk_disable_unprepare(atmel_port->clk);
2958
2959 return 0;
2960
2961 err_add_port:
2962 kfree(atmel_port->rx_ring.buf);
2963 atmel_port->rx_ring.buf = NULL;
2964 err_alloc_ring:
2965 if (!uart_console(&atmel_port->uart)) {
2966 clk_put(atmel_port->clk);
2967 atmel_port->clk = NULL;
2968 }
2969 err_clear_bit:
2970 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2971 err:
2972 return ret;
2973 }
2974
2975 /*
2976 * Even if the driver is not modular, it makes sense to be able to
2977 * unbind a device: there can be many bound devices, and there are
2978 * situations where dynamic binding and unbinding can be useful.
2979 *
2980 * For example, a connected device can require a specific firmware update
2981 * protocol that needs bitbanging on IO lines, but use the regular serial
2982 * port in the normal case.
2983 */
atmel_serial_remove(struct platform_device * pdev)2984 static int atmel_serial_remove(struct platform_device *pdev)
2985 {
2986 struct uart_port *port = platform_get_drvdata(pdev);
2987 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2988 int ret = 0;
2989
2990 tasklet_kill(&atmel_port->tasklet_rx);
2991 tasklet_kill(&atmel_port->tasklet_tx);
2992
2993 device_init_wakeup(&pdev->dev, 0);
2994
2995 ret = uart_remove_one_port(&atmel_uart, port);
2996
2997 kfree(atmel_port->rx_ring.buf);
2998
2999 /* "port" is allocated statically, so we shouldn't free it */
3000
3001 clear_bit(port->line, atmel_ports_in_use);
3002
3003 clk_put(atmel_port->clk);
3004 atmel_port->clk = NULL;
3005 pdev->dev.of_node = NULL;
3006
3007 return ret;
3008 }
3009
3010 static struct platform_driver atmel_serial_driver = {
3011 .probe = atmel_serial_probe,
3012 .remove = atmel_serial_remove,
3013 .suspend = atmel_serial_suspend,
3014 .resume = atmel_serial_resume,
3015 .driver = {
3016 .name = "atmel_usart_serial",
3017 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
3018 },
3019 };
3020
atmel_serial_init(void)3021 static int __init atmel_serial_init(void)
3022 {
3023 int ret;
3024
3025 ret = uart_register_driver(&atmel_uart);
3026 if (ret)
3027 return ret;
3028
3029 ret = platform_driver_register(&atmel_serial_driver);
3030 if (ret)
3031 uart_unregister_driver(&atmel_uart);
3032
3033 return ret;
3034 }
3035 device_initcall(atmel_serial_init);
3036