1[/ 2 Copyright Oliver Kowalke 2017. 3 Distributed under the Boost Software License, Version 1.0. 4 (See accompanying file LICENSE_1_0.txt or copy at 5 http://www.boost.org/LICENSE_1_0.txt 6] 7 8[#speculation] 9[section:speculation Specualtive execution] 10 11[heading Hardware transactional memory] 12 13With help of hardware transactional memory multiple logical processors 14execute a critical region speculatively, e.g. without explicit 15synchronization.[br] 16If the transactional execution completes successfully, then all memory 17operations performed within the transactional region are commited without any 18inter-thread serialization.[br] 19When the optimistic execution fails, the processor aborts the transaction and 20discards all performed modifications.[br] 21In non-transactional code a single lock serializes the access to a critical 22region. With a transactional memory, multiple logical processor start a 23transaction and update the memory (the data) inside the ciritical region. 24Unless some logical processors try to update the same data, the transactions 25would always succeed. 26 27 28[heading Intel Transactional Synchronisation Extensions (TSX)] 29 30TSX is Intel's implementation of hardware transactional memory in modern Intel 31processors[footnote intel.com: [@https://software.intel.com/en-us/node/695149 32Intel Transactional Synchronization Extensions]].[br] 33In TSX the hardware keeps track of which cachelines have been read from and 34which have been written to in a transaction. The cache-line size (64-byte) and 35the n-way set associative cache determine the maximum size of memory in a 36transaction. For instance if a transaction modifies 9 cache-lines at a 37processor with a 8-way set associative cache, the transaction will always be 38aborted. 39 40[note TXS is enabled if property `htm=tsx` is specified at b2 command-line and 41`BOOST_USE_TSX` is applied to the compiler.] 42 43[note A TSX-transaction will be aborted if the floating point state is modified 44inside a critical region. As a consequence floating point operations, e.g. 45store/load of floating point related registers during a fiber (context) switch 46are disabled.] 47 48[important TSX can not be used together with MSVC at this time!] 49 50Boost.Fiber uses TSX-enabled spinlocks to protect critical regions (see section 51[link tuning Tuning]). 52 53[endsect] 54