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1{
2 "enums": {
3  "COMMAND__SAIC": {
4   "entries": [
5    {"name": "INCREMENT", "value": 0},
6    {"name": "NO_INCREMENT", "value": 1}
7   ]
8  },
9  "COMMAND__SAS": {
10   "entries": [
11    {"name": "MEMORY", "value": 0},
12    {"name": "REGISTER", "value": 1}
13   ]
14  },
15  "COMMAND__SRC_SWAP": {
16   "entries": [
17    {"name": "NONE", "value": 0},
18    {"name": "8_IN_16", "value": 1},
19    {"name": "8_IN_32", "value": 2},
20    {"name": "8_IN_64", "value": 3}
21   ]
22  },
23  "CONTROL__DST_SEL": {
24   "entries": [
25    {"name": "MEM_MAPPED_REGISTER", "value": 0},
26    {"comment": "sync across GRBM", "name": "MEM_GRBM", "value": 1},
27    {"name": "TC_L2", "value": 2},
28    {"name": "GDS", "value": 3},
29    {"name": "RESERVED", "value": 4}
30   ]
31  },
32  "CONTROL__DST_SEL_cik": {
33   "entries": [
34    {"name": "MEM_MAPPED_REGISTER", "value": 0},
35    {"comment": "sync across GRBM", "name": "MEM_GRBM", "value": 1},
36    {"name": "TC_L2", "value": 2},
37    {"name": "GDS", "value": 3},
38    {"name": "RESERVED", "value": 4},
39    {"name": "MEM", "value": 5}
40   ]
41  },
42  "CONTROL__ENGINE_SEL": {
43   "entries": [
44    {"name": "ME", "value": 0},
45    {"name": "PFP", "value": 1},
46    {"name": "CE", "value": 2},
47    {"name": "DE", "value": 3}
48   ]
49  },
50  "CP_DMA_WORD1__DST_SEL": {
51   "entries": [
52    {"name": "DST_ADDR", "value": 0},
53    {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1}
54   ]
55  },
56  "CP_DMA_WORD1__DST_SEL_cik": {
57   "entries": [
58    {"name": "DST_ADDR", "value": 0},
59    {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1},
60    {"name": "DST_ADDR_TC_L2", "value": 3}
61   ]
62  },
63  "CP_DMA_WORD1__DST_SEL_gfx9": {
64   "entries": [
65    {"name": "DST_ADDR", "value": 0},
66    {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1},
67    {"name": "NOWHERE", "value": 2},
68    {"name": "DST_ADDR_TC_L2", "value": 3}
69   ]
70  },
71  "CP_DMA_WORD1__ENGINE": {
72   "entries": [
73    {"name": "ME", "value": 0},
74    {"name": "PFP", "value": 1}
75   ]
76  },
77  "CP_DMA_WORD1__SRC_SEL": {
78   "entries": [
79    {"name": "SRC_ADDR", "value": 0},
80    {"comment": "program SAS to 1 as well", "name": "GDS", "value": 1},
81    {"name": "DATA", "value": 2}
82   ]
83  },
84  "CP_DMA_WORD1__SRC_SEL_cik": {
85   "entries": [
86    {"name": "SRC_ADDR", "value": 0},
87    {"comment": "program SAS to 1 as well", "name": "GDS", "value": 1},
88    {"name": "DATA", "value": 2},
89    {"name": "SRC_ADDR_TC_L2", "value": 3}
90   ]
91  },
92  "GCR_GL1_RANGE": {
93   "entries": [
94    {"name": "GL1_ALL", "value": 0},
95    {"name": "GL1_RANGE", "value": 2},
96    {"name": "GL1_FIRST_LAST", "value": 3}
97   ]
98  },
99  "GCR_GL2_RANGE": {
100   "entries": [
101    {"name": "GL2_ALL", "value": 0},
102    {"name": "GL2_VOL", "value": 1},
103    {"name": "GL2_RANGE", "value": 2},
104    {"name": "GL2_FIRST_LAST", "value": 3}
105   ]
106  },
107  "GCR_GLI_INV": {
108   "entries": [
109    {"name": "GLI_NOP", "value": 0},
110    {"name": "GLI_ALL", "value": 1},
111    {"name": "GLI_RANGE", "value": 2},
112    {"name": "GLI_FIRST_LAST", "value": 3}
113   ]
114  },
115  "GCR_SEQ": {
116   "entries": [
117    {"name": "SEQ_PARALLEL", "value": 0},
118    {"name": "SEQ_FORWARD", "value": 1},
119    {"name": "SEQ_REVERSE", "value": 2}
120   ]
121  }
122 },
123 "register_mappings": [
124  {
125   "comment": "This is at offset 0x415 instead of 0x414 due to a conflict with SQ_WAVE_GPR_ALLOC",
126   "chips": ["gfx6", "gfx7", "gfx8", "gfx81"],
127   "map": {"at": 1045, "to": "pkt3"},
128   "name": "COMMAND",
129   "type_ref": "COMMAND"
130  },
131  {
132   "chips": ["gfx9", "gfx10", "gfx103"],
133   "map": {"at": 1045, "to": "pkt3"},
134   "name": "COMMAND",
135   "type_ref": "COMMAND_gfx9"
136  },
137  {
138   "chips": ["gfx6"],
139   "map": {"at": 880, "to": "pkt3"},
140   "name": "CONTROL",
141   "type_ref": "CONTROL"
142  },
143  {
144   "chips": ["gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
145   "map": {"at": 880, "to": "pkt3"},
146   "name": "CONTROL",
147   "type_ref": "CONTROL_cik"
148  },
149  {
150   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
151   "map": {"at": 1040, "to": "pkt3"},
152   "name": "CP_DMA_WORD0",
153   "type_ref": "CP_DMA_WORD0"
154  },
155  {
156   "chips": ["gfx6"],
157   "map": {"at": 1041, "to": "pkt3"},
158   "name": "CP_DMA_WORD1",
159   "type_ref": "CP_DMA_WORD1"
160  },
161  {
162   "chips": ["gfx7", "gfx8", "gfx81"],
163   "map": {"at": 1041, "to": "pkt3"},
164   "name": "CP_DMA_WORD1",
165   "type_ref": "CP_DMA_WORD1_cik"
166  },
167  {
168   "chips": ["gfx9", "gfx10", "gfx103"],
169   "map": {"at": 1041, "to": "pkt3"},
170   "name": "CP_DMA_WORD1",
171   "type_ref": "CP_DMA_WORD1_gfx9"
172  },
173  {
174   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
175   "map": {"at": 1042, "to": "pkt3"},
176   "name": "CP_DMA_WORD2",
177   "type_ref": "CP_DMA_WORD2"
178  },
179  {
180   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
181   "map": {"at": 1043, "to": "pkt3"},
182   "name": "CP_DMA_WORD3",
183   "type_ref": "CP_DMA_WORD3"
184  },
185  {
186   "chips": ["gfx6"],
187   "map": {"at": 1280, "to": "pkt3"},
188   "name": "DMA_DATA_WORD0",
189   "type_ref": "DMA_DATA_WORD0"
190  },
191  {
192   "chips": ["gfx7", "gfx8", "gfx81"],
193   "map": {"at": 1280, "to": "pkt3"},
194   "name": "DMA_DATA_WORD0",
195   "type_ref": "DMA_DATA_WORD0_cik"
196  },
197  {
198   "chips": ["gfx9", "gfx10", "gfx103"],
199   "map": {"at": 1280, "to": "pkt3"},
200   "name": "DMA_DATA_WORD0",
201   "type_ref": "DMA_DATA_WORD0_gfx9"
202  },
203  {
204   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
205   "map": {"at": 882, "to": "pkt3"},
206   "name": "DST_ADDR_HI"
207  },
208  {
209   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
210   "map": {"at": 1284, "to": "pkt3"},
211   "name": "DST_ADDR_HI"
212  },
213  {
214   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
215   "map": {"at": 881, "to": "pkt3"},
216   "name": "DST_ADDR_LO"
217  },
218  {
219   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
220   "map": {"at": 1283, "to": "pkt3"},
221   "name": "DST_ADDR_LO"
222  },
223  {
224   "chips": ["gfx10", "gfx103"],
225   "map": {"at": 1414, "to": "pkt3"},
226   "name": "GCR_CNTL",
227   "type_ref": "GCR_CNTL"
228  },
229  {
230   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
231   "map": {"at": 1009, "to": "pkt3"},
232   "name": "IB_BASE_HI"
233  },
234  {
235   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
236   "map": {"at": 1008, "to": "pkt3"},
237   "name": "IB_BASE_LO"
238  },
239  {
240   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
241   "map": {"at": 1010, "to": "pkt3"},
242   "name": "IB_CONTROL",
243   "type_ref": "IB_CONTROL"
244  },
245  {
246   "chips": ["gfx10", "gfx103"],
247   "map": {"at": 1168, "to": "pkt3"},
248   "name": "RELEASE_MEM_OP",
249   "type_ref": "RELEASE_MEM_OP"
250  },
251  {
252   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
253   "map": {"at": 1282, "to": "pkt3"},
254   "name": "SRC_ADDR_HI"
255  },
256  {
257   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
258   "map": {"at": 1281, "to": "pkt3"},
259   "name": "SRC_ADDR_LO"
260  }
261 ],
262 "register_types": {
263  "COMMAND": {
264   "fields": [
265    {"bits": [0, 20], "name": "BYTE_COUNT"},
266    {"bits": [21, 21], "name": "DISABLE_WR_CONFIRM"},
267    {"bits": [22, 23], "enum_ref": "COMMAND__SRC_SWAP", "name": "SRC_SWAP"},
268    {"bits": [24, 25], "enum_ref": "COMMAND__SRC_SWAP", "name": "DST_SWAP"},
269    {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"},
270    {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"},
271    {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"},
272    {"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"},
273    {"bits": [30, 30], "name": "RAW_WAIT"}
274   ]
275  },
276  "COMMAND_gfx9": {
277   "fields": [
278    {"bits": [0, 25], "name": "BYTE_COUNT"},
279    {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"},
280    {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"},
281    {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"},
282    {"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"},
283    {"bits": [30, 30], "name": "RAW_WAIT"},
284    {"bits": [31, 31], "name": "DISABLE_WR_CONFIRM"}
285   ]
286  },
287  "CONTROL": {
288   "fields": [
289    {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL", "name": "DST_SEL"},
290    {"bits": [16, 16], "name": "WR_ONE_ADDR"},
291    {"bits": [20, 20], "name": "WR_CONFIRM"},
292    {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"}
293   ]
294  },
295  "CONTROL_cik": {
296   "fields": [
297    {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL_cik", "name": "DST_SEL"},
298    {"bits": [16, 16], "name": "WR_ONE_ADDR"},
299    {"bits": [20, 20], "name": "WR_CONFIRM"},
300    {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"}
301   ]
302  },
303  "CP_DMA_WORD0": {
304   "fields": [
305    {"bits": [0, 31], "name": "SRC_ADDR_LO"}
306   ]
307  },
308  "CP_DMA_WORD1": {
309   "fields": [
310    {"bits": [0, 15], "name": "SRC_ADDR_HI"},
311    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"},
312    {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
313    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"},
314    {"bits": [31, 31], "name": "CP_SYNC"}
315   ]
316  },
317  "CP_DMA_WORD1_cik": {
318   "fields": [
319    {"bits": [0, 15], "name": "SRC_ADDR_HI"},
320    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"},
321    {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
322    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
323    {"bits": [31, 31], "name": "CP_SYNC"}
324   ]
325  },
326  "CP_DMA_WORD1_gfx9": {
327   "fields": [
328    {"bits": [0, 15], "name": "SRC_ADDR_HI"},
329    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"},
330    {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
331    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
332    {"bits": [31, 31], "name": "CP_SYNC"}
333   ]
334  },
335  "CP_DMA_WORD2": {
336   "fields": [
337    {"bits": [0, 31], "name": "DST_ADDR_LO"}
338   ]
339  },
340  "CP_DMA_WORD3": {
341   "fields": [
342    {"bits": [0, 15], "name": "DST_ADDR_HI"}
343   ]
344  },
345  "DMA_DATA_WORD0": {
346   "fields": [
347    {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
348    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"},
349    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"},
350    {"bits": [31, 31], "name": "CP_SYNC"}
351   ]
352  },
353  "DMA_DATA_WORD0_cik": {
354   "fields": [
355    {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
356    {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
357    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"},
358    {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
359    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
360    {"bits": [31, 31], "name": "CP_SYNC"}
361   ]
362  },
363  "DMA_DATA_WORD0_gfx9": {
364   "fields": [
365    {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
366    {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
367    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"},
368    {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
369    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
370    {"bits": [31, 31], "name": "CP_SYNC"}
371   ]
372  },
373  "GCR_CNTL": {
374   "fields": [
375    {"bits": [0, 1], "enum_ref": "GCR_GLI_INV", "name": "GLI_INV"},
376    {"bits": [2, 3], "enum_ref": "GCR_GL1_RANGE", "name": "GL1_RANGE"},
377    {"bits": [4, 4], "name": "GLM_WB"},
378    {"bits": [5, 5], "name": "GLM_INV"},
379    {"bits": [6, 6], "name": "GLK_WB"},
380    {"bits": [7, 7], "name": "GLK_INV"},
381    {"bits": [8, 8], "name": "GLV_INV"},
382    {"bits": [9, 9], "name": "GL1_INV"},
383    {"bits": [10, 10], "name": "GL2_US"},
384    {"bits": [11, 12], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"},
385    {"bits": [13, 13], "name": "GL2_DISCARD"},
386    {"bits": [14, 14], "name": "GL2_INV"},
387    {"bits": [15, 15], "name": "GL2_WB"},
388    {"bits": [16, 17], "enum_ref": "GCR_SEQ", "name": "SEQ"},
389    {"bits": [18, 18], "name": "RANGE_IS_PA"}
390   ]
391  },
392  "IB_CONTROL": {
393   "fields": [
394    {"bits": [0, 19], "name": "IB_SIZE"},
395    {"bits": [20, 20], "name": "CHAIN"},
396    {"bits": [23, 23], "name": "VALID"}
397   ]
398  },
399  "RELEASE_MEM_OP": {
400   "fields": [
401    {"bits": [0, 5], "name": "EVENT_TYPE"},
402    {"bits": [8, 11], "name": "EVENT_INDEX"},
403    {"bits": [12, 12], "name": "GLM_WB"},
404    {"bits": [13, 13], "name": "GLM_INV"},
405    {"bits": [14, 14], "name": "GLV_INV"},
406    {"bits": [15, 15], "name": "GL1_INV"},
407    {"bits": [16, 16], "name": "GL2_US"},
408    {"bits": [17, 18], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"},
409    {"bits": [19, 19], "name": "GL2_DISCARD"},
410    {"bits": [20, 20], "name": "GL2_INV"},
411    {"bits": [21, 21], "name": "GL2_WB"},
412    {"bits": [22, 23], "enum_ref": "GCR_SEQ", "name": "SEQ"}
413   ]
414  }
415 }
416}
417