1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> 5 6<enum name="vgt_event_type"> 7 <value name="VS_DEALLOC" value="0"/> 8 <value name="PS_DEALLOC" value="1"/> 9 <value name="VS_DONE_TS" value="2"/> 10 <value name="PS_DONE_TS" value="3"/> 11 <value name="CACHE_FLUSH_TS" value="4"/> 12 <value name="CONTEXT_DONE" value="5"/> 13 <value name="CACHE_FLUSH" value="6"/> 14 <value name="VIZQUERY_START" value="7" varset="chip" variants="A2XX"/> 15 <value name="HLSQ_FLUSH" value="7" varset="chip" variants="A3XX-A4XX"/> 16 <value name="VIZQUERY_END" value="8" varset="chip" variants="A2XX"/> 17 <value name="SC_WAIT_WC" value="9" varset="chip" variants="A2XX"/> 18 <value name="WRITE_PRIMITIVE_COUNTS" value="9" varset="chip" variants="A6XX"/> 19 <value name="START_PRIMITIVE_CTRS" value="11" varset="chip" variants="A6XX"/> 20 <value name="STOP_PRIMITIVE_CTRS" value="12" varset="chip" variants="A6XX"/> 21 <value name="RST_PIX_CNT" value="13"/> 22 <value name="RST_VTX_CNT" value="14"/> 23 <value name="TILE_FLUSH" value="15"/> 24 <value name="STAT_EVENT" value="16"/> 25 <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" varset="chip" variants="A2XX-A4XX"/> 26 <value name="ZPASS_DONE" value="21"/> 27 <value name="CACHE_FLUSH_AND_INV_EVENT" value="22" varset="chip" variants="A2XX"/> 28 <value name="RB_DONE_TS" value="22" varset="chip" variants="A3XX-"/> 29 <value name="PERFCOUNTER_START" value="23" varset="chip" variants="A2XX-A4XX"/> 30 <value name="PERFCOUNTER_STOP" value="24" varset="chip" variants="A2XX-A4XX"/> 31 <value name="VS_FETCH_DONE" value="27"/> 32 <value name="FACENESS_FLUSH" value="28" varset="chip" variants="A2XX-A4XX"/> 33 34 <!-- a5xx events --> 35 <value name="WT_DONE_TS" value="8" varset="chip" variants="A5XX-"/> 36 <value name="FLUSH_SO_0" value="17" varset="chip" variants="A5XX-"/> 37 <value name="FLUSH_SO_1" value="18" varset="chip" variants="A5XX-"/> 38 <value name="FLUSH_SO_2" value="19" varset="chip" variants="A5XX-"/> 39 <value name="FLUSH_SO_3" value="20" varset="chip" variants="A5XX-"/> 40 <value name="PC_CCU_INVALIDATE_DEPTH" value="24" varset="chip" variants="A5XX-"/> 41 <value name="PC_CCU_INVALIDATE_COLOR" value="25" varset="chip" variants="A5XX-"/> 42 <value name="PC_CCU_RESOLVE_TS" value="26" varset="chip" variants="A6XX"/> 43 <value name="PC_CCU_FLUSH_DEPTH_TS" value="28" varset="chip" variants="A5XX-"/> 44 <value name="PC_CCU_FLUSH_COLOR_TS" value="29" varset="chip" variants="A5XX-"/> 45 <value name="BLIT" value="30" varset="chip" variants="A5XX-"/> 46 <value name="UNK_25" value="37" varset="chip" variants="A5XX"/> 47 <value name="LRZ_FLUSH" value="38" varset="chip" variants="A5XX-"/> 48 <value name="BLIT_OP_FILL_2D" value="39" varset="chip" variants="A5XX-"/> 49 <value name="BLIT_OP_COPY_2D" value="40" varset="chip" variants="A5XX-"/> 50 <value name="BLIT_OP_SCALE_2D" value="42" varset="chip" variants="A5XX-"/> 51 <value name="CONTEXT_DONE_2D" value="43" varset="chip" variants="A5XX-"/> 52 <value name="UNK_2C" value="44" varset="chip" variants="A5XX-"/> 53 <value name="UNK_2D" value="45" varset="chip" variants="A5XX-"/> 54 55 <!-- a6xx events --> 56 <value name="CACHE_INVALIDATE" value="49" varset="chip" variants="A6XX"/> 57</enum> 58 59<enum name="pc_di_primtype"> 60 <value name="DI_PT_NONE" value="0"/> 61 <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: --> 62 <value name="DI_PT_POINTLIST_PSIZE" value="1"/> 63 <value name="DI_PT_LINELIST" value="2"/> 64 <value name="DI_PT_LINESTRIP" value="3"/> 65 <value name="DI_PT_TRILIST" value="4"/> 66 <value name="DI_PT_TRIFAN" value="5"/> 67 <value name="DI_PT_TRISTRIP" value="6"/> 68 <value name="DI_PT_LINELOOP" value="7"/> <!-- a22x, a3xx --> 69 <value name="DI_PT_RECTLIST" value="8"/> 70 <value name="DI_PT_POINTLIST" value="9"/> 71 <value name="DI_PT_LINE_ADJ" value="0xa"/> 72 <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/> 73 <value name="DI_PT_TRI_ADJ" value="0xc"/> 74 <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/> 75 76 <value name="DI_PT_PATCHES0" value="0x1f"/> 77 <value name="DI_PT_PATCHES1" value="0x20"/> 78 <value name="DI_PT_PATCHES2" value="0x21"/> 79 <value name="DI_PT_PATCHES3" value="0x22"/> 80 <value name="DI_PT_PATCHES4" value="0x23"/> 81 <value name="DI_PT_PATCHES5" value="0x24"/> 82 <value name="DI_PT_PATCHES6" value="0x25"/> 83 <value name="DI_PT_PATCHES7" value="0x26"/> 84 <value name="DI_PT_PATCHES8" value="0x27"/> 85 <value name="DI_PT_PATCHES9" value="0x28"/> 86 <value name="DI_PT_PATCHES10" value="0x29"/> 87 <value name="DI_PT_PATCHES11" value="0x2a"/> 88 <value name="DI_PT_PATCHES12" value="0x2b"/> 89 <value name="DI_PT_PATCHES13" value="0x2c"/> 90 <value name="DI_PT_PATCHES14" value="0x2d"/> 91 <value name="DI_PT_PATCHES15" value="0x2e"/> 92 <value name="DI_PT_PATCHES16" value="0x2f"/> 93 <value name="DI_PT_PATCHES17" value="0x30"/> 94 <value name="DI_PT_PATCHES18" value="0x31"/> 95 <value name="DI_PT_PATCHES19" value="0x32"/> 96 <value name="DI_PT_PATCHES20" value="0x33"/> 97 <value name="DI_PT_PATCHES21" value="0x34"/> 98 <value name="DI_PT_PATCHES22" value="0x35"/> 99 <value name="DI_PT_PATCHES23" value="0x36"/> 100 <value name="DI_PT_PATCHES24" value="0x37"/> 101 <value name="DI_PT_PATCHES25" value="0x38"/> 102 <value name="DI_PT_PATCHES26" value="0x39"/> 103 <value name="DI_PT_PATCHES27" value="0x3a"/> 104 <value name="DI_PT_PATCHES28" value="0x3b"/> 105 <value name="DI_PT_PATCHES29" value="0x3c"/> 106 <value name="DI_PT_PATCHES30" value="0x3d"/> 107 <value name="DI_PT_PATCHES31" value="0x3e"/> 108</enum> 109 110<enum name="pc_di_src_sel"> 111 <value name="DI_SRC_SEL_DMA" value="0"/> 112 <value name="DI_SRC_SEL_IMMEDIATE" value="1"/> 113 <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/> 114 <value name="DI_SRC_SEL_AUTO_XFB" value="3"/> 115</enum> 116 117<enum name="pc_di_face_cull_sel"> 118 <value name="DI_FACE_CULL_NONE" value="0"/> 119 <value name="DI_FACE_CULL_FETCH" value="1"/> 120 <value name="DI_FACE_BACKFACE_CULL" value="2"/> 121 <value name="DI_FACE_FRONTFACE_CULL" value="3"/> 122</enum> 123 124<enum name="pc_di_index_size"> 125 <value name="INDEX_SIZE_IGN" value="0"/> 126 <value name="INDEX_SIZE_16_BIT" value="0"/> 127 <value name="INDEX_SIZE_32_BIT" value="1"/> 128 <value name="INDEX_SIZE_8_BIT" value="2"/> 129 <value name="INDEX_SIZE_INVALID"/> 130</enum> 131 132<enum name="pc_di_vis_cull_mode"> 133 <value name="IGNORE_VISIBILITY" value="0"/> 134 <value name="USE_VISIBILITY" value="1"/> 135</enum> 136 137<enum name="adreno_pm4_packet_type"> 138 <value name="CP_TYPE0_PKT" value="0x00000000"/> 139 <value name="CP_TYPE1_PKT" value="0x40000000"/> 140 <value name="CP_TYPE2_PKT" value="0x80000000"/> 141 <value name="CP_TYPE3_PKT" value="0xc0000000"/> 142 <value name="CP_TYPE4_PKT" value="0x40000000"/> 143 <value name="CP_TYPE7_PKT" value="0x70000000"/> 144</enum> 145 146<!-- 147 Note that in some cases, the same packet id is recycled on a later 148 generation, so variants attribute is used to distinguish. They 149 may not be completely accurate, we would probably have to analyze 150 the pfp and me/pm4 firmware to verify the packet is actually 151 handled on a particular generation. But it is at least enough to 152 disambiguate the packet-id's that were re-used for different 153 packets starting with a5xx. 154 --> 155<enum name="adreno_pm4_type3_packets"> 156 <doc>initialize CP's micro-engine</doc> 157 <value name="CP_ME_INIT" value="0x48"/> 158 <doc>skip N 32-bit words to get to the next packet</doc> 159 <value name="CP_NOP" value="0x10"/> 160 <doc> 161 indirect buffer dispatch. prefetch parser uses this packet 162 type to determine whether to pre-fetch the IB 163 </doc> 164 <value name="CP_PREEMPT_ENABLE" value="0x1c"/> 165 <value name="CP_PREEMPT_TOKEN" value="0x1e"/> 166 <value name="CP_INDIRECT_BUFFER" value="0x3f"/> 167 <doc> 168 Takes the same arguments as CP_INDIRECT_BUFFER, but jumps to 169 another buffer at the same level. Must be at the end of IB, and 170 doesn't work with draw state IB's. 171 </doc> 172 <value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" varset="chip" variants="A5XX-"/> 173 <doc>indirect buffer dispatch. same as IB, but init is pipelined</doc> 174 <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/> 175 <doc>wait for the IDLE state of the engine</doc> 176 <value name="CP_WAIT_FOR_IDLE" value="0x26"/> 177 <doc>wait until a register or memory location is a specific value</doc> 178 <value name="CP_WAIT_REG_MEM" value="0x3c"/> 179 <doc>wait until a register location is equal to a specific value</doc> 180 <value name="CP_WAIT_REG_EQ" value="0x52"/> 181 <doc>wait until a register location is >= a specific value</doc> 182 <value name="CP_WAIT_REG_GTE" value="0x53" varset="chip" variants="A2XX-A4XX"/> 183 <doc>wait until a read completes</doc> 184 <value name="CP_WAIT_UNTIL_READ" value="0x5c" varset="chip" variants="A2XX-A4XX"/> 185 <doc>wait until all base/size writes from an IB_PFD packet have completed</doc> 186 <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d"/> 187 <doc>register read/modify/write</doc> 188 <value name="CP_REG_RMW" value="0x21"/> 189 <doc>Set binning configuration registers</doc> 190 <value name="CP_SET_BIN_DATA" value="0x2f" varset="chip" variants="A2XX-A4XX"/> 191 <value name="CP_SET_BIN_DATA5" value="0x2f" varset="chip" variants="A5XX-"/> 192 <doc>reads register in chip and writes to memory</doc> 193 <value name="CP_REG_TO_MEM" value="0x3e"/> 194 <doc>write N 32-bit words to memory</doc> 195 <value name="CP_MEM_WRITE" value="0x3d"/> 196 <doc>write CP_PROG_COUNTER value to memory</doc> 197 <value name="CP_MEM_WRITE_CNTR" value="0x4f"/> 198 <doc>conditional execution of a sequence of packets</doc> 199 <value name="CP_COND_EXEC" value="0x44"/> 200 <doc>conditional write to memory or register</doc> 201 <value name="CP_COND_WRITE" value="0x45" varset="chip" variants="A2XX-A4XX"/> 202 <value name="CP_COND_WRITE5" value="0x45" varset="chip" variants="A5XX-"/> 203 <doc>generate an event that creates a write to memory when completed</doc> 204 <value name="CP_EVENT_WRITE" value="0x46"/> 205 <doc>generate a VS|PS_done event</doc> 206 <value name="CP_EVENT_WRITE_SHD" value="0x58"/> 207 <doc>generate a cache flush done event</doc> 208 <value name="CP_EVENT_WRITE_CFL" value="0x59"/> 209 <doc>generate a z_pass done event</doc> 210 <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/> 211 <doc> 212 not sure the real name, but this seems to be what is used for 213 opencl, instead of CP_DRAW_INDX.. 214 </doc> 215 <value name="CP_RUN_OPENCL" value="0x31"/> 216 <doc>initiate fetch of index buffer and draw</doc> 217 <value name="CP_DRAW_INDX" value="0x22"/> 218 <doc>draw using supplied indices in packet</doc> 219 <value name="CP_DRAW_INDX_2" value="0x36" varset="chip" variants="A2XX-A4XX"/> <!-- this is something different on a6xx and unused on a5xx --> 220 <doc>initiate fetch of index buffer and binIDs and draw</doc> 221 <value name="CP_DRAW_INDX_BIN" value="0x34" varset="chip" variants="A2XX-A4XX"/> 222 <doc>initiate fetch of bin IDs and draw using supplied indices</doc> 223 <value name="CP_DRAW_INDX_2_BIN" value="0x35" varset="chip" variants="A2XX-A4XX"/> 224 <doc>begin/end initiator for viz query extent processing</doc> 225 <value name="CP_VIZ_QUERY" value="0x23" varset="chip" variants="A2XX-A4XX"/> 226 <doc>fetch state sub-blocks and initiate shader code DMAs</doc> 227 <value name="CP_SET_STATE" value="0x25"/> 228 <doc>load constant into chip and to memory</doc> 229 <value name="CP_SET_CONSTANT" value="0x2d"/> 230 <doc>load sequencer instruction memory (pointer-based)</doc> 231 <value name="CP_IM_LOAD" value="0x27"/> 232 <doc>load sequencer instruction memory (code embedded in packet)</doc> 233 <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/> 234 <doc>load constants from a location in memory</doc> 235 <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" varset="chip" variants="A2XX"/> 236 <doc>selective invalidation of state pointers</doc> 237 <value name="CP_INVALIDATE_STATE" value="0x3b"/> 238 <doc>dynamically changes shader instruction memory partition</doc> 239 <value name="CP_SET_SHADER_BASES" value="0x4a" varset="chip" variants="A2XX-A4XX"/> 240 <doc>sets the 64-bit BIN_MASK register in the PFP</doc> 241 <value name="CP_SET_BIN_MASK" value="0x50" varset="chip" variants="A2XX-A4XX"/> 242 <doc>sets the 64-bit BIN_SELECT register in the PFP</doc> 243 <value name="CP_SET_BIN_SELECT" value="0x51" varset="chip" variants="A2XX-A4XX"/> 244 <doc>updates the current context, if needed</doc> 245 <value name="CP_CONTEXT_UPDATE" value="0x5e"/> 246 <doc>generate interrupt from the command stream</doc> 247 <value name="CP_INTERRUPT" value="0x40"/> 248 <doc>copy sequencer instruction memory to system memory</doc> 249 <value name="CP_IM_STORE" value="0x2c" varset="chip" variants="A2XX"/> 250 251 <!-- For a20x --> 252<!-- TODO handle variants.. 253 <doc> 254 Program an offset that will added to the BIN_BASE value of 255 the 3D_DRAW_INDX_BIN packet 256 </doc> 257 <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/> 258 --> 259 260 <!-- for a22x --> 261 <doc> 262 sets draw initiator flags register in PFP, gets bitwise-ORed into 263 every draw initiator 264 </doc> 265 <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/> 266 <doc>sets the register protection mode</doc> 267 <value name="CP_SET_PROTECTED_MODE" value="0x5f"/> 268 269 <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/> 270 271 <!-- for a3xx --> 272 <doc>load high level sequencer command</doc> 273 <value name="CP_LOAD_STATE" value="0x30" varset="chip" variants="A3XX"/> 274 <value name="CP_LOAD_STATE4" value="0x30" varset="chip" variants="A4XX-A5XX"/> 275 <doc>Conditionally load a IB based on a flag, prefetch enabled</doc> 276 <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/> 277 <doc>Conditionally load a IB based on a flag, prefetch disabled</doc> 278 <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" varset="chip" variants="A3XX"/> 279 <doc>Load a buffer with pre-fetch enabled</doc> 280 <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" varset="chip" variants="A5XX"/> 281 <doc>Set bin (?)</doc> 282 <value name="CP_SET_BIN" value="0x4c" varset="chip" variants="A2XX"/> 283 284 <doc>test 2 memory locations to dword values specified</doc> 285 <value name="CP_TEST_TWO_MEMS" value="0x71"/> 286 287 <doc>Write register, ignoring context state for context sensitive registers</doc> 288 <value name="CP_REG_WR_NO_CTXT" value="0x78"/> 289 290 <doc>Record the real-time when this packet is processed by PFP</doc> 291 <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/> 292 293 <!-- Used to switch GPU between secure and non-secure modes --> 294 <value name="CP_SET_SECURE_MODE" value="0x66"/> 295 296 <doc>PFP waits until the FIFO between the PFP and the ME is empty</doc> 297 <value name="CP_WAIT_FOR_ME" value="0x13"/> 298 299 <!-- for a4xx --> 300 <doc> 301 Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple 302 groups of registers. Looks like it can be used to create state 303 objects in GPU memory, and on state change only emit pointer 304 (via CP_SET_DRAW_STATE), which should be nice for reducing CPU 305 overhead: 306 307 (A4x) save PM4 stream pointers to execute upon a visible draw 308 </doc> 309 <value name="CP_SET_DRAW_STATE" value="0x43" varset="chip" variants="A4XX-"/> 310 <value name="CP_DRAW_INDX_OFFSET" value="0x38"/> 311 <value name="CP_DRAW_INDIRECT" value="0x28" varset="chip" variants="A4XX-"/> 312 <value name="CP_DRAW_INDX_INDIRECT" value="0x29" varset="chip" variants="A4XX-"/> 313 <value name="CP_DRAW_INDIRECT_MULTI" value="0x2a" varset="chip" variants="A6XX"/> 314 <value name="CP_DRAW_AUTO" value="0x24"/> 315 316 <doc> 317 Enable or disable predication globally. Also resets the 318 predicate to "passing" and the local bit to enabled when 319 enabling global predication. 320 </doc> 321 <value name="CP_DRAW_PRED_ENABLE_GLOBAL" value="0x19"/> 322 323 <doc> 324 Enable or disable predication locally. Unlike globally enabling 325 predication, this packet doesn't touch any other state. 326 Predication only happens when enabled globally and locally and a 327 predicate has been set. This should be used for internal draws 328 which aren't supposed to use the predication state: 329 330 CP_DRAW_PRED_ENABLE_LOCAL(0) 331 ... do draw... 332 CP_DRAW_PRED_ENABLE_LOCAL(1) 333 </doc> 334 <value name="CP_DRAW_PRED_ENABLE_LOCAL" value="0x1a"/> 335 336 <doc> 337 Latch a draw predicate into the internal register. 338 </doc> 339 <value name="CP_DRAW_PRED_SET" value="0x4e"/> 340 341 <doc> 342 for A4xx 343 Write to register with address that does not fit into type-0 pkt 344 </doc> 345 <value name="CP_WIDE_REG_WRITE" value="0x74" varset="chip" variants="A4XX"/> 346 347 <doc>copy from ME scratch RAM to a register</doc> 348 <value name="CP_SCRATCH_TO_REG" value="0x4d"/> 349 350 <doc>Copy from REG to ME scratch RAM</doc> 351 <value name="CP_REG_TO_SCRATCH" value="0x4a"/> 352 353 <doc>Wait for memory writes to complete</doc> 354 <value name="CP_WAIT_MEM_WRITES" value="0x12"/> 355 356 <doc>Conditional execution based on register comparison</doc> 357 <value name="CP_COND_REG_EXEC" value="0x47"/> 358 359 <doc>Memory to REG copy</doc> 360 <value name="CP_MEM_TO_REG" value="0x42"/> 361 362 <value name="CP_EXEC_CS_INDIRECT" value="0x41" varset="chip" variants="A4XX-"/> 363 <value name="CP_EXEC_CS" value="0x33"/> 364 365 <doc> 366 for a5xx 367 </doc> 368 <value name="CP_PERFCOUNTER_ACTION" value="0x50" varset="chip" variants="A5XX"/> 369 <!-- switches SMMU pagetable, used on a5xx+ only --> 370 <value name="CP_SMMU_TABLE_UPDATE" value="0x53" varset="chip" variants="A5XX-"/> 371 <!-- for a6xx --> 372 <doc>Tells CP the current mode of GPU operation</doc> 373 <value name="CP_SET_MARKER" value="0x65" varset="chip" variants="A6XX"/> 374 <doc>Instruct CP to set a few internal CP registers</doc> 375 <value name="CP_SET_PSEUDO_REG" value="0x56" varset="chip" variants="A6XX"/> 376 <!-- 377 pairs of regid and value.. seems to be used to program some TF 378 related regs: 379 --> 380 <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" varset="chip" variants="A5XX-"/> 381 <!-- A5XX Enable yield in RB only --> 382 <value name="CP_YIELD_ENABLE" value="0x1c" varset="chip" variants="A5XX"/> 383 <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" varset="chip" variants="A5XX-"/> 384 <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" varset="chip" variants="A5XX-"/> 385 <value name="CP_SET_SUBDRAW_SIZE" value="0x35" varset="chip" variants="A5XX-"/> 386 <value name="CP_WHERE_AM_I" value="0x62" varset="chip" variants="A5XX-"/> 387 <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" varset="chip" variants="A5XX-"/> 388 <!-- Enable/Disable/Defer A5x global preemption model --> 389 <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" varset="chip" variants="A5XX"/> 390 <!-- Enable/Disable A5x local preemption model --> 391 <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" varset="chip" variants="A5XX"/> 392 <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx --> 393 <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" varset="chip" variants="A5XX"/> 394 <!-- Inform CP about current render mode (needed for a5xx preemption) --> 395 <value name="CP_SET_RENDER_MODE" value="0x6c" varset="chip" variants="A5XX"/> 396 <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" varset="chip" variants="A5XX"/> 397 <!-- check if this works on earlier.. --> 398 <value name="CP_MEM_TO_MEM" value="0x73" varset="chip" variants="A5XX-"/> 399 <value name="CP_BLIT" value="0x2c" varset="chip" variants="A5XX-"/> 400 401 <!-- Test specified bit in specified register and set predicate --> 402 <value name="CP_REG_TEST" value="0x39" varset="chip" variants="A5XX-"/> 403 404 <!-- 405 Seems to set the mode flags which control which CP_SET_DRAW_STATE 406 packets are executed, based on their ENABLE_MASK values 407 408 CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE 409 packets w/ ENABLE_MASK & 0x6 to execute immediately 410 --> 411 <value name="CP_SET_MODE" value="0x63" varset="chip" variants="A6XX"/> 412 413 <!-- 414 Seems like there are now separate blocks of state for VS vs FS/CS 415 (probably these amounts to geometry vs fragments so that geometry 416 stage of the pipeline for next draw can start while fragment stage 417 of current draw is still running. The format of the payload of the 418 packets is the same, the only difference is the offsets of the regs 419 the firmware code that handles the packet writes. 420 421 Note that for CL, starting with a6xx, the preferred # of local 422 threads is no longer the same as the max, implying that the shader 423 core can now run warps from unrelated shaders (ie. 424 CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs 425 CL_KERNEL_WORK_GROUP_SIZE) 426 --> 427 <value name="CP_LOAD_STATE6_GEOM" value="0x32" varset="chip" variants="A6XX"/> 428 <value name="CP_LOAD_STATE6_FRAG" value="0x34" varset="chip" variants="A6XX"/> 429 <!-- 430 Note: For IBO state (Image/SSBOs) which have shared state across 431 shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for 432 compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are 433 interchangable. 434 --> 435 <value name="CP_LOAD_STATE6" value="0x36" varset="chip" variants="A6XX"/> 436 437 <!-- internal packets: --> 438 <value name="IN_IB_PREFETCH_END" value="0x17" varset="chip" variants="A2XX"/> 439 <value name="IN_SUBBLK_PREFETCH" value="0x1f" varset="chip" variants="A2XX"/> 440 <value name="IN_INSTR_PREFETCH" value="0x20" varset="chip" variants="A2XX"/> 441 <value name="IN_INSTR_MATCH" value="0x47" varset="chip" variants="A2XX"/> 442 <value name="IN_CONST_PREFETCH" value="0x49" varset="chip" variants="A2XX"/> 443 <value name="IN_INCR_UPDT_STATE" value="0x55" varset="chip" variants="A2XX"/> 444 <value name="IN_INCR_UPDT_CONST" value="0x56" varset="chip" variants="A2XX"/> 445 <value name="IN_INCR_UPDT_INSTR" value="0x57" varset="chip" variants="A2XX"/> 446 447 <!-- jmptable entry used to handle type4 packet on a5xx+: --> 448 <value name="PKT4" value="0x04" varset="chip" variants="A5XX-"/> 449 450 <!-- TODO do these exist on A5xx? --> 451 <value name="CP_SCRATCH_WRITE" value="0x4c" varset="chip" variants="A6XX"/> 452 <value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" varset="chip" variants="A6XX"/> 453 <value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" varset="chip" variants="A6XX"/> 454 <value name="CP_WAIT_MEM_GTE" value="0x14" varset="chip" variants="A6XX"/> 455 <value name="CP_WAIT_TWO_REGS" value="0x70" varset="chip" variants="A6XX"/> 456 <value name="CP_MEMCPY" value="0x75" varset="chip" variants="A6XX"/> 457 <value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" varset="chip" variants="A6XX"/> 458 <value name="CP_SET_CTXSWITCH_IB" value="0x55" varset="chip" variants="A6XX"/> 459 460 <!-- 461 Seems to always have the payload: 462 00000002 00008801 00004010 463 or: 464 00000002 00008801 00004090 465 or: 466 00000002 00008801 00000010 467 00000002 00008801 00010010 468 00000002 00008801 00d64010 469 ... 470 Note set for compute shaders.. 471 Is 0x8801 a register offset? 472 This appears to be a special sort of register write packet 473 more or less, but the firmware has some special handling.. 474 Seems like it intercepts/modifies certain register offsets, 475 but others are treated like a normal PKT4 reg write. I 476 guess there are some registers that the fw controls certain 477 bits. 478 --> 479 <value name="CP_REG_WRITE" value="0x6d" varset="chip" variants="A6XX"/> 480 481 <doc> 482 These first appear in a650_sqe.bin. They can in theory be used 483 to loop any sequence of IB1 commands, but in practice they are 484 used to loop over bins. There is a fixed-size per-iteration 485 prefix, used to set per-bin state, and then the following IB1 486 commands are executed until CP_END_BIN which are always the same 487 for each iteration and usually contain a list of 488 CP_INDIRECT_BUFFER calls to IB2 commands which setup state and 489 execute restore/draw/save commands. This replaces the previous 490 technique of just repeating the CP_INDIRECT_BUFFER calls and 491 "unrolling" the loop. 492 </doc> 493 <value name="CP_START_BIN" value="0x50" varset="chip" variants="A6XX"/> 494 <value name="CP_END_BIN" value="0x51" varset="chip" variants="A6XX"/> 495</enum> 496 497 498<domain name="CP_LOAD_STATE" width="32"> 499 <doc>Load state, a3xx (and later?)</doc> 500 <enum name="adreno_state_block"> 501 <value name="SB_VERT_TEX" value="0"/> 502 <value name="SB_VERT_MIPADDR" value="1"/> 503 <value name="SB_FRAG_TEX" value="2"/> 504 <value name="SB_FRAG_MIPADDR" value="3"/> 505 <value name="SB_VERT_SHADER" value="4"/> 506 <value name="SB_GEOM_SHADER" value="5"/> 507 <value name="SB_FRAG_SHADER" value="6"/> 508 <value name="SB_COMPUTE_SHADER" value="7"/> 509 </enum> 510 <enum name="adreno_state_type"> 511 <value name="ST_SHADER" value="0"/> 512 <value name="ST_CONSTANTS" value="1"/> 513 </enum> 514 <enum name="adreno_state_src"> 515 <value name="SS_DIRECT" value="0"> 516 <doc>inline with the CP_LOAD_STATE packet</doc> 517 </value> 518 <value name="SS_INVALID_ALL_IC" value="2"/> 519 <value name="SS_INVALID_PART_IC" value="3"/> 520 <value name="SS_INDIRECT" value="4"> 521 <doc>in buffer pointed to by EXT_SRC_ADDR</doc> 522 </value> 523 <value name="SS_INDIRECT_TCM" value="5"/> 524 <value name="SS_INDIRECT_STM" value="6"/> 525 </enum> 526 <reg32 offset="0" name="0"> 527 <bitfield name="DST_OFF" low="0" high="15" type="uint"/> 528 <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/> 529 <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/> 530 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/> 531 </reg32> 532 <reg32 offset="1" name="1"> 533 <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/> 534 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/> 535 </reg32> 536</domain> 537 538<domain name="CP_LOAD_STATE4" width="32" varset="chip"> 539 <doc>Load state, a4xx+</doc> 540 <enum name="a4xx_state_block"> 541 <!-- 542 unknown: 0x7 and 0xf <- seen in compute shader 543 544 STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption? 545 Seen in some GL shaders. Payload is NUM_UNIT dwords, and it contains 546 the gpuaddr of the following shader constants block. DST_OFF seems 547 to specify which shader stage: 548 549 16 -> vert 550 36 -> tcs 551 56 -> tes 552 76 -> geom 553 96 -> frag 554 555 Example: 556 557opcode: CP_LOAD_STATE4 (30) (12 dwords) 558 { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 } 559 { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 } 560 { EXT_SRC_ADDR_HI = 0 } 561 0000: c0264100 00000000 00000000 00000000 562 0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000 563 564opcode: CP_LOAD_STATE4 (30) (4 dwords) 565 { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } 566 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 } 567 { EXT_SRC_ADDR_HI = 0 } 568 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 569 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 570 0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000 571 572 STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader. NUM_UNITS * 2 dwords. 573 574 --> 575 <value name="SB4_VS_TEX" value="0x0"/> 576 <value name="SB4_HS_TEX" value="0x1"/> <!-- aka. TCS --> 577 <value name="SB4_DS_TEX" value="0x2"/> <!-- aka. TES --> 578 <value name="SB4_GS_TEX" value="0x3"/> 579 <value name="SB4_FS_TEX" value="0x4"/> 580 <value name="SB4_CS_TEX" value="0x5"/> 581 <value name="SB4_VS_SHADER" value="0x8"/> 582 <value name="SB4_HS_SHADER" value="0x9"/> 583 <value name="SB4_DS_SHADER" value="0xa"/> 584 <value name="SB4_GS_SHADER" value="0xb"/> 585 <value name="SB4_FS_SHADER" value="0xc"/> 586 <value name="SB4_CS_SHADER" value="0xd"/> 587 <!-- 588 for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each), 589 STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each) 590 591 Compute has it's own dedicated SSBO state, it seems, but the rest 592 of the stages share state 593 --> 594 <value name="SB4_SSBO" value="0xe"/> 595 <value name="SB4_CS_SSBO" value="0xf"/> 596 </enum> 597 <enum name="a4xx_state_type"> 598 <value name="ST4_SHADER" value="0"/> 599 <value name="ST4_CONSTANTS" value="1"/> 600 <value name="ST4_UBO" value="2"/> 601 </enum> 602 <enum name="a4xx_state_src"> 603 <value name="SS4_DIRECT" value="0"/> 604 <value name="SS4_INDIRECT" value="2"/> 605 </enum> 606 <reg32 offset="0" name="0"> 607 <bitfield name="DST_OFF" low="0" high="13" type="uint"/> 608 <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/> 609 <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/> 610 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/> 611 </reg32> 612 <reg32 offset="1" name="1"> 613 <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/> 614 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/> 615 </reg32> 616 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 617 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/> 618 </reg32> 619</domain> 620 621<!-- looks basically same CP_LOAD_STATE4 --> 622<domain name="CP_LOAD_STATE6" width="32" varset="chip"> 623 <doc>Load state, a6xx+</doc> 624 <enum name="a6xx_state_block"> 625 <value name="SB6_VS_TEX" value="0x0"/> 626 <value name="SB6_HS_TEX" value="0x1"/> <!-- aka. TCS --> 627 <value name="SB6_DS_TEX" value="0x2"/> <!-- aka. TES --> 628 <value name="SB6_GS_TEX" value="0x3"/> 629 <value name="SB6_FS_TEX" value="0x4"/> 630 <value name="SB6_CS_TEX" value="0x5"/> 631 <value name="SB6_VS_SHADER" value="0x8"/> 632 <value name="SB6_HS_SHADER" value="0x9"/> 633 <value name="SB6_DS_SHADER" value="0xa"/> 634 <value name="SB6_GS_SHADER" value="0xb"/> 635 <value name="SB6_FS_SHADER" value="0xc"/> 636 <value name="SB6_CS_SHADER" value="0xd"/> 637 <value name="SB6_IBO" value="0xe"/> 638 <value name="SB6_CS_IBO" value="0xf"/> 639 </enum> 640 <enum name="a6xx_state_type"> 641 <value name="ST6_SHADER" value="0"/> 642 <value name="ST6_CONSTANTS" value="1"/> 643 <value name="ST6_UBO" value="2"/> 644 <value name="ST6_IBO" value="3"/> 645 </enum> 646 <enum name="a6xx_state_src"> 647 <value name="SS6_DIRECT" value="0"/> 648 <value name="SS6_BINDLESS" value="1"/> <!-- TODO does this exist on a4xx/a5xx? --> 649 <value name="SS6_INDIRECT" value="2"/> 650 <doc> 651 SS6_UBO used by the a6xx vulkan blob with tesselation constants 652 in this case, EXT_SRC_ADDR is (ubo_id shl 16 | offset) 653 to load constants from a UBO loaded with DST_OFF = 14 and offset 0, 654 EXT_SRC_ADDR = 0xe0000 655 (offset is a guess, should be in bytes given that maxUniformBufferRange=64k) 656 </doc> 657 <value name="SS6_UBO" value="3"/> 658 </enum> 659 <reg32 offset="0" name="0"> 660 <bitfield name="DST_OFF" low="0" high="13" type="uint"/> 661 <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/> 662 <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/> 663 <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/> 664 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/> 665 </reg32> 666 <reg32 offset="1" name="1"> 667 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/> 668 </reg32> 669 <reg32 offset="2" name="2"> 670 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/> 671 </reg32> 672 <reg64 offset="1" name="EXT_SRC_ADDR" type="address"/> 673</domain> 674 675<bitset name="vgt_draw_initiator" inline="yes"> 676 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/> 677 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/> 678 <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/> 679 <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/> 680 <bitfield name="NOT_EOP" pos="12" type="boolean"/> 681 <bitfield name="SMALL_INDEX" pos="13" type="boolean"/> 682 <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/> 683 <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/> 684</bitset> 685 686<!-- changed on a4xx: --> 687<enum name="a4xx_index_size"> 688 <value name="INDEX4_SIZE_8_BIT" value="0"/> 689 <value name="INDEX4_SIZE_16_BIT" value="1"/> 690 <value name="INDEX4_SIZE_32_BIT" value="2"/> 691</enum> 692 693<enum name="a6xx_patch_type"> 694 <value name="TESS_QUADS" value="0"/> 695 <value name="TESS_TRIANGLES" value="1"/> 696 <value name="TESS_ISOLINES" value="2"/> 697</enum> 698 699<bitset name="vgt_draw_initiator_a4xx" inline="yes"> 700 <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 --> 701 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/> 702 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/> 703 <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/> 704 <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/> 705 <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/> 706 <bitfield name="GS_ENABLE" pos="16" type="boolean"/> 707 <bitfield name="TESS_ENABLE" pos="17" type="boolean"/> 708</bitset> 709 710<domain name="CP_DRAW_INDX" width="32"> 711 <reg32 offset="0" name="0"> 712 <bitfield name="VIZ_QUERY" low="0" high="31"/> 713 </reg32> 714 <reg32 offset="1" name="1" type="vgt_draw_initiator"/> 715 <reg32 offset="2" name="2"> 716 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/> 717 </reg32> 718 <reg32 offset="3" name="3"> 719 <bitfield name="INDX_BASE" low="0" high="31"/> 720 </reg32> 721 <reg32 offset="4" name="4"> 722 <bitfield name="INDX_SIZE" low="0" high="31"/> 723 </reg32> 724</domain> 725 726<domain name="CP_DRAW_INDX_2" width="32"> 727 <reg32 offset="0" name="0"> 728 <bitfield name="VIZ_QUERY" low="0" high="31"/> 729 </reg32> 730 <reg32 offset="1" name="1" type="vgt_draw_initiator"/> 731 <reg32 offset="2" name="2"> 732 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/> 733 </reg32> 734 <!-- followed by NUM_INDICES indices.. --> 735</domain> 736 737<domain name="CP_DRAW_INDX_OFFSET" width="32"> 738 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 739 <reg32 offset="1" name="1"> 740 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/> 741 </reg32> 742 <reg32 offset="2" name="2"> 743 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/> 744 </reg32> 745 <reg32 offset="3" name="3"> 746 <bitfield name="FIRST_INDX" low="0" high="31"/> 747 </reg32> 748 749 <stripe varset="chip" variants="A5XX-"> 750 <reg32 offset="4" name="4"> 751 <bitfield name="INDX_BASE_LO" low="0" high="31"/> 752 </reg32> 753 <reg32 offset="5" name="5"> 754 <bitfield name="INDX_BASE_HI" low="0" high="31"/> 755 </reg32> 756 <reg64 offset="4" name="INDX_BASE" type="address"/> 757 <reg32 offset="6" name="6"> 758 <!-- max # of elements in index buffer --> 759 <bitfield name="MAX_INDICES" low="0" high="31"/> 760 </reg32> 761 </stripe> 762 763 <reg32 offset="4" name="4"> 764 <bitfield name="INDX_BASE" low="0" high="31" type="address"/> 765 </reg32> 766 767 <reg32 offset="5" name="5"> 768 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/> 769 </reg32> 770</domain> 771 772<domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-"> 773 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 774 <stripe varset="chip" variants="A4XX"> 775 <reg32 offset="1" name="1"> 776 <bitfield name="INDIRECT" low="0" high="31"/> 777 </reg32> 778 </stripe> 779 <stripe varset="chip" variants="A5XX-"> 780 <reg32 offset="1" name="1"> 781 <bitfield name="INDIRECT_LO" low="0" high="31"/> 782 </reg32> 783 <reg32 offset="2" name="2"> 784 <bitfield name="INDIRECT_HI" low="0" high="31"/> 785 </reg32> 786 <reg64 offset="1" name="INDIRECT" type="address"/> 787 </stripe> 788</domain> 789 790<domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-"> 791 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 792 <stripe varset="chip" variants="A4XX"> 793 <reg32 offset="1" name="1"> 794 <bitfield name="INDX_BASE" low="0" high="31"/> 795 </reg32> 796 <reg32 offset="2" name="2"> 797 <!-- max # of bytes in index buffer --> 798 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/> 799 </reg32> 800 <reg32 offset="3" name="3"> 801 <bitfield name="INDIRECT" low="0" high="31"/> 802 </reg32> 803 </stripe> 804 <stripe varset="chip" variants="A5XX-"> 805 <reg32 offset="1" name="1"> 806 <bitfield name="INDX_BASE_LO" low="0" high="31"/> 807 </reg32> 808 <reg32 offset="2" name="2"> 809 <bitfield name="INDX_BASE_HI" low="0" high="31"/> 810 </reg32> 811 <reg64 offset="1" name="INDX_BASE" type="address"/> 812 <reg32 offset="3" name="3"> 813 <!-- max # of elements in index buffer --> 814 <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/> 815 </reg32> 816 <reg32 offset="4" name="4"> 817 <bitfield name="INDIRECT_LO" low="0" high="31"/> 818 </reg32> 819 <reg32 offset="5" name="5"> 820 <bitfield name="INDIRECT_HI" low="0" high="31"/> 821 </reg32> 822 <reg64 offset="4" name="INDIRECT" type="address"/> 823 </stripe> 824</domain> 825 826<domain name="CP_DRAW_INDIRECT_MULTI" width="32" varset="chip" prefix="chip" variants="A6XX-"> 827 <enum name="a6xx_draw_indirect_opcode"> 828 <value name="INDIRECT_OP_NORMAL" value="0x2"/> 829 <value name="INDIRECT_OP_INDEXED" value="0x4"/> 830 <value name="INDIRECT_OP_INDIRECT_COUNT" value="0x6"/> 831 <value name="INDIRECT_OP_INDIRECT_COUNT_INDEXED" value="0x7"/> 832 </enum> 833 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 834 <reg32 offset="1" name="1"> 835 <bitfield name="OPCODE" low="0" high="3" type="a6xx_draw_indirect_opcode" addvariant="yes"/> 836 <doc> 837 DST_OFF same as in CP_LOAD_STATE6 - vec4 VS const at this offset will 838 be updated for each draw to {draw_id, first_vertex, first_instance, 0} 839 value of 0 disables it 840 </doc> 841 <bitfield name="DST_OFF" low="8" high="21" type="hex"/> 842 </reg32> 843 <reg32 offset="2" name="DRAW_COUNT" type="uint"/> 844 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_NORMAL"> 845 <reg64 offset="3" name="INDIRECT" type="address"/> 846 <reg32 offset="5" name="STRIDE" type="uint"/> 847 </stripe> 848 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDEXED" prefix="INDEXED"> 849 <reg64 offset="3" name="INDEX" type="address"/> 850 <reg32 offset="5" name="MAX_INDICES" type="uint"/> 851 <reg64 offset="6" name="INDIRECT" type="address"/> 852 <reg32 offset="8" name="STRIDE" type="uint"/> 853 </stripe> 854 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT" prefix="INDIRECT"> 855 <reg64 offset="3" name="INDIRECT" type="address"/> 856 <reg64 offset="5" name="INDIRECT_COUNT" type="address"/> 857 <reg32 offset="7" name="STRIDE" type="uint"/> 858 </stripe> 859 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT_INDEXED" prefix="INDIRECT_INDEXED"> 860 <reg64 offset="3" name="INDEX" type="address"/> 861 <reg32 offset="5" name="MAX_INDICES" type="uint"/> 862 <reg64 offset="6" name="INDIRECT" type="address"/> 863 <reg64 offset="8" name="INDIRECT_COUNT" type="address"/> 864 <reg32 offset="10" name="STRIDE" type="uint"/> 865 </stripe> 866</domain> 867 868<domain name="CP_DRAW_PRED_ENABLE_GLOBAL" width="32" varset="chip"> 869 <reg32 offset="0" name="0"> 870 <bitfield name="ENABLE" pos="0" type="boolean"/> 871 </reg32> 872</domain> 873 874<domain name="CP_DRAW_PRED_ENABLE_LOCAL" width="32" varset="chip"> 875 <reg32 offset="0" name="0"> 876 <bitfield name="ENABLE" pos="0" type="boolean"/> 877 </reg32> 878</domain> 879 880<domain name="CP_DRAW_PRED_SET" width="32" varset="chip"> 881 <enum name="cp_draw_pred_src"> 882 <!-- 883 Sources 1-4 seem to be about combining reading 884 SO/primitive queries and setting the predicate, which is 885 a DX11-specific optimization (since in DX11 you can only 886 predicate on the result of queries). 887 --> 888 <value name="PRED_SRC_MEM" value="5"> 889 <doc> 890 Read a 64-bit value at the given address and 891 test if it equals/doesn't equal 0. 892 </doc> 893 </value> 894 </enum> 895 <enum name="cp_draw_pred_test"> 896 <value name="NE_0_PASS" value="0"/> 897 <value name="EQ_0_PASS" value="1"/> 898 </enum> 899 <reg32 offset="0" name="0"> 900 <bitfield name="SRC" low="4" high="7" type="cp_draw_pred_src"/> 901 <bitfield name="TEST" pos="8" type="cp_draw_pred_test"/> 902 </reg32> 903 <reg64 offset="1" name="MEM_ADDR" type="address"/> 904</domain> 905 906<domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-"> 907 <array offset="0" stride="3" length="100"> 908 <reg32 offset="0" name="0"> 909 <bitfield name="COUNT" low="0" high="15" type="uint"/> 910 <bitfield name="DIRTY" pos="16" type="boolean"/> 911 <bitfield name="DISABLE" pos="17" type="boolean"/> 912 <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/> 913 <bitfield name="LOAD_IMMED" pos="19" type="boolean"/> 914 <bitfield name="BINNING" pos="20" varset="chip" variants="A6XX-" type="boolean"/> 915 <bitfield name="GMEM" pos="21" varset="chip" variants="A6XX-" type="boolean"/> 916 <bitfield name="SYSMEM" pos="22" varset="chip" variants="A6XX-" type="boolean"/> 917 <bitfield name="GROUP_ID" low="24" high="28" type="uint"/> 918 </reg32> 919 <reg32 offset="1" name="1"> 920 <bitfield name="ADDR_LO" low="0" high="31" type="hex"/> 921 </reg32> 922 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 923 <bitfield name="ADDR_HI" low="0" high="31" type="hex"/> 924 </reg32> 925 </array> 926</domain> 927 928<domain name="CP_SET_BIN" width="32"> 929 <doc>value at offset 0 always seems to be 0x00000000..</doc> 930 <reg32 offset="0" name="0"/> 931 <reg32 offset="1" name="1"> 932 <bitfield name="X1" low="0" high="15" type="uint"/> 933 <bitfield name="Y1" low="16" high="31" type="uint"/> 934 </reg32> 935 <reg32 offset="2" name="2"> 936 <bitfield name="X2" low="0" high="15" type="uint"/> 937 <bitfield name="Y2" low="16" high="31" type="uint"/> 938 </reg32> 939</domain> 940 941<domain name="CP_SET_BIN_DATA" width="32"> 942 <reg32 offset="0" name="0"> 943 <!-- corresponds to VSC_PIPE[n].DATA_ADDR --> 944 <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/> 945 </reg32> 946 <reg32 offset="1" name="1"> 947 <!-- seesm to correspond to VSC_SIZE_ADDRESS --> 948 <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/> 949 </reg32> 950</domain> 951 952<domain name="CP_SET_BIN_DATA5" width="32"> 953 <reg32 offset="0" name="0"> 954 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: --> 955 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 956 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: --> 957 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 958 </reg32> 959 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 960 <reg32 offset="1" name="1"> 961 <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/> 962 </reg32> 963 <reg32 offset="2" name="2"> 964 <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/> 965 </reg32> 966 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 967 <reg32 offset="3" name="3"> 968 <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/> 969 </reg32> 970 <reg32 offset="4" name="4"> 971 <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/> 972 </reg32> 973 <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: --> 974 <reg32 offset="5" name="5"> 975 <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/> 976 </reg32> 977 <reg32 offset="6" name="6"> 978 <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/> 979 </reg32> 980</domain> 981 982<domain name="CP_SET_BIN_DATA5_OFFSET" width="32"> 983 <doc> 984 Like CP_SET_BIN_DATA5, but set the pointers as offsets from the 985 pointers stored in VSC_PIPE_{DATA,DATA2,SIZE}_ADDRESS. Useful 986 for Vulkan where these values aren't known when the command 987 stream is recorded. 988 </doc> 989 <reg32 offset="0" name="0"> 990 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: --> 991 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 992 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: --> 993 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 994 </reg32> 995 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 996 <reg32 offset="1" name="1"> 997 <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/> 998 </reg32> 999 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1000 <reg32 offset="2" name="2"> 1001 <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/> 1002 </reg32> 1003 <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS --> 1004 <reg32 offset="3" name="3"> 1005 <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/> 1006 </reg32> 1007</domain> 1008 1009<domain name="CP_REG_RMW" width="32"> 1010 <doc> 1011 Modifies DST_REG using two sources that can either be registers 1012 or immediates. If SRC1_ADD is set, then do the following: 1013 1014 $dst = (($dst & $src0) rot $rotate) + $src1 1015 1016 Otherwise: 1017 1018 $dst = (($dst & $src0) rot $rotate) | $src1 1019 1020 Here "rot" means rotate left. 1021 </doc> 1022 <reg32 offset="0" name="0"> 1023 <bitfield name="DST_REG" low="0" high="17" type="hex"/> 1024 <bitfield name="ROTATE" low="24" high="28" type="uint"/> 1025 <bitfield name="SRC1_ADD" pos="29" type="boolean"/> 1026 <bitfield name="SRC1_IS_REG" pos="30" type="boolean"/> 1027 <bitfield name="SRC0_IS_REG" pos="31" type="boolean"/> 1028 </reg32> 1029 <reg32 offset="1" name="1"> 1030 <bitfield name="SRC0" low="0" high="31" type="uint"/> 1031 </reg32> 1032 <reg32 offset="2" name="2"> 1033 <bitfield name="SRC1" low="0" high="31" type="uint"/> 1034 </reg32> 1035</domain> 1036 1037<domain name="CP_REG_TO_MEM" width="32"> 1038 <reg32 offset="0" name="0"> 1039 <bitfield name="REG" low="0" high="17" type="hex"/> 1040 <!-- number of registers/dwords copied is max(CNT, 1). --> 1041 <bitfield name="CNT" low="18" high="29" type="uint"/> 1042 <bitfield name="64B" pos="30" type="boolean"/> 1043 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1044 </reg32> 1045 <reg32 offset="1" name="1"> 1046 <bitfield name="DEST" low="0" high="31"/> 1047 </reg32> 1048 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1049 <bitfield name="DEST_HI" low="0" high="31"/> 1050 </reg32> 1051</domain> 1052 1053<domain name="CP_REG_TO_MEM_OFFSET_REG" width="32"> 1054 <doc> 1055 Like CP_REG_TO_MEM, but the memory address to write to can be 1056 offsetted using either one or two registers or scratch 1057 registers. 1058 </doc> 1059 <reg32 offset="0" name="0"> 1060 <bitfield name="REG" low="0" high="17" type="hex"/> 1061 <!-- number of registers/dwords copied is max(CNT, 1). --> 1062 <bitfield name="CNT" low="18" high="29" type="uint"/> 1063 <bitfield name="64B" pos="30" type="boolean"/> 1064 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1065 </reg32> 1066 <reg32 offset="1" name="1"> 1067 <bitfield name="DEST" low="0" high="31"/> 1068 </reg32> 1069 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1070 <bitfield name="DEST_HI" low="0" high="31"/> 1071 </reg32> 1072 <reg32 offset="3" name="3"> 1073 <bitfield name="OFFSET0" low="0" high="17" type="hex"/> 1074 <bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/> 1075 </reg32> 1076 <!-- followed by an optional identical OFFSET1 dword --> 1077</domain> 1078 1079<domain name="CP_REG_TO_MEM_OFFSET_MEM" width="32"> 1080 <doc> 1081 Like CP_REG_TO_MEM, but the memory address to write to can be 1082 offsetted using a DWORD in memory. 1083 </doc> 1084 <reg32 offset="0" name="0"> 1085 <bitfield name="REG" low="0" high="17" type="hex"/> 1086 <!-- number of registers/dwords copied is max(CNT, 1). --> 1087 <bitfield name="CNT" low="18" high="29" type="uint"/> 1088 <bitfield name="64B" pos="30" type="boolean"/> 1089 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1090 </reg32> 1091 <reg32 offset="1" name="1"> 1092 <bitfield name="DEST" low="0" high="31"/> 1093 </reg32> 1094 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1095 <bitfield name="DEST_HI" low="0" high="31"/> 1096 </reg32> 1097 <reg32 offset="3" name="3"> 1098 <bitfield name="OFFSET_LO" low="0" high="31" type="hex"/> 1099 </reg32> 1100 <reg32 offset="4" name="4"> 1101 <bitfield name="OFFSET_HI" low="0" high="31" type="hex"/> 1102 </reg32> 1103</domain> 1104 1105<domain name="CP_MEM_TO_REG" width="32"> 1106 <reg32 offset="0" name="0"> 1107 <bitfield name="REG" low="0" high="17" type="hex"/> 1108 <!-- number of registers/dwords copied is max(CNT, 1). --> 1109 <bitfield name="CNT" low="19" high="29" type="uint"/> 1110 <!-- shift each DWORD left by 2 while copying --> 1111 <bitfield name="SHIFT_BY_2" pos="30" type="boolean"/> 1112 <!-- does the same thing as CP_MEM_TO_MEM::UNK31 --> 1113 <bitfield name="UNK31" pos="31" type="boolean"/> 1114 </reg32> 1115 <reg32 offset="1" name="1"> 1116 <bitfield name="SRC" low="0" high="31"/> 1117 </reg32> 1118 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1119 <bitfield name="SRC_HI" low="0" high="31"/> 1120 </reg32> 1121</domain> 1122 1123<domain name="CP_MEM_TO_MEM" width="32"> 1124 <reg32 offset="0" name="0"> 1125 <!-- 1126 not sure how many src operands we have, but the low 1127 bits negate the n'th src argument. 1128 --> 1129 <bitfield name="NEG_A" pos="0" type="boolean"/> 1130 <bitfield name="NEG_B" pos="1" type="boolean"/> 1131 <bitfield name="NEG_C" pos="2" type="boolean"/> 1132 1133 <!-- if set treat src/dst as 64bit values --> 1134 <bitfield name="DOUBLE" pos="29" type="boolean"/> 1135 <!-- execute CP_WAIT_FOR_MEM_WRITES beforehand --> 1136 <bitfield name="WAIT_FOR_MEM_WRITES" pos="30" type="boolean"/> 1137 <!-- some other kind of wait --> 1138 <bitfield name="UNK31" pos="31" type="boolean"/> 1139 </reg32> 1140 <!-- 1141 followed by sequence of addresses.. the first is the 1142 destination and the rest are N src addresses which are 1143 summed (after being negated if NEG_x bit set) allowing 1144 to do things like 'result += end - start' (which turns 1145 out to be useful for queries and accumulating results 1146 across multiple tiles) 1147 --> 1148</domain> 1149 1150<domain name="CP_MEMCPY" width="32"> 1151 <reg32 offset="0" name="0"> 1152 <bitfield name="DWORDS" low="0" high="31" type="uint"/> 1153 </reg32> 1154 <reg32 offset="1" name="1"> 1155 <bitfield name="SRC_LO" low="0" high="31" type="hex"/> 1156 </reg32> 1157 <reg32 offset="2" name="2"> 1158 <bitfield name="SRC_HI" low="0" high="31" type="hex"/> 1159 </reg32> 1160 <reg32 offset="3" name="3"> 1161 <bitfield name="DST_LO" low="0" high="31" type="hex"/> 1162 </reg32> 1163 <reg32 offset="4" name="4"> 1164 <bitfield name="DST_HI" low="0" high="31" type="hex"/> 1165 </reg32> 1166</domain> 1167 1168<domain name="CP_REG_TO_SCRATCH" width="32"> 1169 <reg32 offset="0" name="0"> 1170 <bitfield name="REG" low="0" high="17" type="hex"/> 1171 <bitfield name="SCRATCH" low="20" high="22" type="uint"/> 1172 <!-- number of registers/dwords copied is CNT + 1. --> 1173 <bitfield name="CNT" low="24" high="26" type="uint"/> 1174 </reg32> 1175</domain> 1176 1177<domain name="CP_SCRATCH_TO_REG" width="32"> 1178 <reg32 offset="0" name="0"> 1179 <bitfield name="REG" low="0" high="17" type="hex"/> 1180 <!-- note: CP_MEM_TO_REG always sets this when writing to the register --> 1181 <bitfield name="UNK18" pos="18" type="boolean"/> 1182 <bitfield name="SCRATCH" low="20" high="22" type="uint"/> 1183 <!-- number of registers/dwords copied is CNT + 1. --> 1184 <bitfield name="CNT" low="24" high="26" type="uint"/> 1185 </reg32> 1186</domain> 1187 1188<domain name="CP_SCRATCH_WRITE" width="32"> 1189 <reg32 offset="0" name="0"> 1190 <bitfield name="SCRATCH" low="20" high="22" type="uint"/> 1191 </reg32> 1192 <!-- followed by one or more DWORDs to write to scratch registers --> 1193</domain> 1194 1195<domain name="CP_MEM_WRITE" width="32"> 1196 <reg32 offset="0" name="0"> 1197 <bitfield name="ADDR_LO" low="0" high="31"/> 1198 </reg32> 1199 <reg32 offset="1" name="1"> 1200 <bitfield name="ADDR_HI" low="0" high="31"/> 1201 </reg32> 1202 <!-- followed by the DWORDs to write --> 1203</domain> 1204 1205<enum name="cp_cond_function"> 1206 <value value="0" name="WRITE_ALWAYS"/> 1207 <value value="1" name="WRITE_LT"/> 1208 <value value="2" name="WRITE_LE"/> 1209 <value value="3" name="WRITE_EQ"/> 1210 <value value="4" name="WRITE_NE"/> 1211 <value value="5" name="WRITE_GE"/> 1212 <value value="6" name="WRITE_GT"/> 1213</enum> 1214 1215<domain name="CP_COND_WRITE" width="32"> 1216 <reg32 offset="0" name="0"> 1217 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/> 1218 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/> 1219 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> 1220 </reg32> 1221 <reg32 offset="1" name="1"> 1222 <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/> 1223 </reg32> 1224 <reg32 offset="2" name="2"> 1225 <bitfield name="REF" low="0" high="31"/> 1226 </reg32> 1227 <reg32 offset="3" name="3"> 1228 <bitfield name="MASK" low="0" high="31"/> 1229 </reg32> 1230 <reg32 offset="4" name="4"> 1231 <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/> 1232 </reg32> 1233 <reg32 offset="5" name="5"> 1234 <bitfield name="WRITE_DATA" low="0" high="31"/> 1235 </reg32> 1236</domain> 1237 1238<domain name="CP_COND_WRITE5" width="32"> 1239 <reg32 offset="0" name="0"> 1240 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/> 1241 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/> 1242 <!-- if both POLL_MEMORY and POLL_SCRATCH are false, it polls a register at POLL_ADDR_LO instead. --> 1243 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/> 1244 <bitfield name="POLL_SCRATCH" pos="5" type="boolean"/> 1245 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> 1246 </reg32> 1247 <reg32 offset="1" name="1"> 1248 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> 1249 </reg32> 1250 <reg32 offset="2" name="2"> 1251 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> 1252 </reg32> 1253 <reg32 offset="3" name="3"> 1254 <bitfield name="REF" low="0" high="31"/> 1255 </reg32> 1256 <reg32 offset="4" name="4"> 1257 <bitfield name="MASK" low="0" high="31"/> 1258 </reg32> 1259 <reg32 offset="5" name="5"> 1260 <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/> 1261 </reg32> 1262 <reg32 offset="6" name="6"> 1263 <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/> 1264 </reg32> 1265 <reg32 offset="7" name="7"> 1266 <bitfield name="WRITE_DATA" low="0" high="31"/> 1267 </reg32> 1268</domain> 1269 1270<domain name="CP_WAIT_MEM_GTE" width="32"> 1271 <doc> 1272 Wait until a memory value is greater than or equal to the 1273 reference, using signed comparison. 1274 </doc> 1275 <reg32 offset="0" name="0"> 1276 <!-- Reserved for flags, presumably? Unused in FW --> 1277 <bitfield name="RESERVED" low="0" high="31" type="hex"/> 1278 </reg32> 1279 <reg32 offset="1" name="1"> 1280 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> 1281 </reg32> 1282 <reg32 offset="2" name="2"> 1283 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> 1284 </reg32> 1285 <reg32 offset="3" name="3"> 1286 <bitfield name="REF" low="0" high="31"/> 1287 </reg32> 1288</domain> 1289 1290<domain name="CP_WAIT_REG_MEM" width="32"> 1291 <doc> 1292 This uses the same internal comparison as CP_COND_WRITE, 1293 but waits until the comparison is true instead. It busy-loops in 1294 the CP for the given number of cycles before trying again. 1295 </doc> 1296 <reg32 offset="0" name="0"> 1297 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/> 1298 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/> 1299 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/> 1300 <bitfield name="POLL_SCRATCH" pos="5" type="boolean"/> 1301 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> 1302 </reg32> 1303 <reg32 offset="1" name="1"> 1304 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> 1305 </reg32> 1306 <reg32 offset="2" name="2"> 1307 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> 1308 </reg32> 1309 <reg32 offset="3" name="3"> 1310 <bitfield name="REF" low="0" high="31"/> 1311 </reg32> 1312 <reg32 offset="4" name="4"> 1313 <bitfield name="MASK" low="0" high="31"/> 1314 </reg32> 1315 <reg32 offset="5" name="5"> 1316 <bitfield name="DELAY_LOOP_CYCLES" low="0" high="31"/> 1317 </reg32> 1318</domain> 1319 1320<domain name="CP_WAIT_TWO_REGS" width="32"> 1321 <doc> 1322 Waits for REG0 to not be 0 or REG1 to not equal REF 1323 </doc> 1324 <reg32 offset="0" name="0"> 1325 <bitfield name="REG0" low="0" high="17" type="hex"/> 1326 </reg32> 1327 <reg32 offset="1" name="1"> 1328 <bitfield name="REG1" low="0" high="17" type="hex"/> 1329 </reg32> 1330 <reg32 offset="2" name="2"> 1331 <bitfield name="REF" low="0" high="31" type="uint"/> 1332 </reg32> 1333</domain> 1334 1335<domain name="CP_DISPATCH_COMPUTE" width="32"> 1336 <reg32 offset="0" name="0"/> 1337 <reg32 offset="1" name="1"> 1338 <bitfield name="X" low="0" high="31"/> 1339 </reg32> 1340 <reg32 offset="2" name="2"> 1341 <bitfield name="Y" low="0" high="31"/> 1342 </reg32> 1343 <reg32 offset="3" name="3"> 1344 <bitfield name="Z" low="0" high="31"/> 1345 </reg32> 1346</domain> 1347 1348<domain name="CP_SET_RENDER_MODE" width="32"> 1349 <enum name="render_mode_cmd"> 1350 <value value="1" name="BYPASS"/> 1351 <value value="2" name="BINNING"/> 1352 <value value="3" name="GMEM"/> 1353 <value value="5" name="BLIT2D"/> 1354 <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? --> 1355 <value value="7" name="BLIT2DSCALE"/> 1356 <!-- 8 set before going back to BYPASS exiting 2D --> 1357 <value value="8" name="END2D"/> 1358 </enum> 1359 <reg32 offset="0" name="0"> 1360 <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/> 1361 <!-- 1362 normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in 1363 0x21xx range.. possibly (at least some) a5xx variants have a 1364 2d core? 1365 --> 1366 </reg32> 1367 <!-- I think first buffer is for GPU to save context in case of ctx switch? --> 1368 <reg32 offset="1" name="1"> 1369 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1370 </reg32> 1371 <reg32 offset="2" name="2"> 1372 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1373 </reg32> 1374 <reg32 offset="3" name="3"> 1375 <!-- 1376 set when in GMEM.. maybe indicates GMEM contents need to be 1377 preserved on ctx switch? 1378 --> 1379 <bitfield name="VSC_ENABLE" pos="3" type="boolean"/> 1380 <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/> 1381 </reg32> 1382 <reg32 offset="4" name="4"/> 1383 <!-- second buffer looks like some cmdstream.. length in dwords: --> 1384 <reg32 offset="5" name="5"> 1385 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/> 1386 </reg32> 1387 <reg32 offset="6" name="6"> 1388 <bitfield name="ADDR_1_LO" low="0" high="31"/> 1389 </reg32> 1390 <reg32 offset="7" name="7"> 1391 <bitfield name="ADDR_1_HI" low="0" high="31"/> 1392 </reg32> 1393</domain> 1394 1395<!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword --> 1396<domain name="CP_COMPUTE_CHECKPOINT" width="32"> 1397 <!-- I think first buffer is for GPU to save context in case of ctx switch? --> 1398 <reg32 offset="0" name="0"> 1399 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1400 </reg32> 1401 <reg32 offset="1" name="1"> 1402 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1403 </reg32> 1404 <reg32 offset="2" name="2"> 1405 </reg32> 1406 <!-- second buffer looks like some cmdstream.. length in dwords: --> 1407 <reg32 offset="3" name="3"> 1408 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/> 1409 </reg32> 1410 <reg32 offset="4" name="4"/> 1411 <reg32 offset="5" name="5"> 1412 <bitfield name="ADDR_1_LO" low="0" high="31"/> 1413 </reg32> 1414 <reg32 offset="6" name="6"> 1415 <bitfield name="ADDR_1_HI" low="0" high="31"/> 1416 </reg32> 1417 <reg32 offset="7" name="7"/> 1418</domain> 1419 1420<domain name="CP_PERFCOUNTER_ACTION" width="32"> 1421 <reg32 offset="0" name="0"> 1422 </reg32> 1423 <reg32 offset="1" name="1"> 1424 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1425 </reg32> 1426 <reg32 offset="2" name="2"> 1427 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1428 </reg32> 1429</domain> 1430 1431<domain name="CP_EVENT_WRITE" width="32"> 1432 <reg32 offset="0" name="0"> 1433 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/> 1434 <!-- when set, write back timestamp instead of value from packet: --> 1435 <bitfield name="TIMESTAMP" pos="30" type="boolean"/> 1436 <bitfield name="IRQ" pos="31" type="boolean"/> 1437 </reg32> 1438 <!-- 1439 TODO what is gpuaddr for, seems to be all 0's.. maybe needed for 1440 context switch? 1441 --> 1442 <reg32 offset="1" name="1"> 1443 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1444 </reg32> 1445 <reg32 offset="2" name="2"> 1446 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1447 </reg32> 1448 <reg32 offset="3" name="3"> 1449 <!-- ??? --> 1450 </reg32> 1451</domain> 1452 1453<domain name="CP_BLIT" width="32"> 1454 <enum name="cp_blit_cmd"> 1455 <value value="0" name="BLIT_OP_FILL"/> 1456 <value value="1" name="BLIT_OP_COPY"/> 1457 <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation --> 1458 </enum> 1459 <reg32 offset="0" name="0"> 1460 <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/> 1461 </reg32> 1462 <reg32 offset="1" name="1"> 1463 <bitfield name="SRC_X1" low="0" high="13" type="uint"/> 1464 <bitfield name="SRC_Y1" low="16" high="29" type="uint"/> 1465 </reg32> 1466 <reg32 offset="2" name="2"> 1467 <bitfield name="SRC_X2" low="0" high="13" type="uint"/> 1468 <bitfield name="SRC_Y2" low="16" high="29" type="uint"/> 1469 </reg32> 1470 <reg32 offset="3" name="3"> 1471 <bitfield name="DST_X1" low="0" high="13" type="uint"/> 1472 <bitfield name="DST_Y1" low="16" high="29" type="uint"/> 1473 </reg32> 1474 <reg32 offset="4" name="4"> 1475 <bitfield name="DST_X2" low="0" high="13" type="uint"/> 1476 <bitfield name="DST_Y2" low="16" high="29" type="uint"/> 1477 </reg32> 1478</domain> 1479 1480<domain name="CP_EXEC_CS" width="32"> 1481 <reg32 offset="0" name="0"> 1482 </reg32> 1483 <reg32 offset="1" name="1"> 1484 <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/> 1485 </reg32> 1486 <reg32 offset="2" name="2"> 1487 <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/> 1488 </reg32> 1489 <reg32 offset="3" name="3"> 1490 <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/> 1491 </reg32> 1492</domain> 1493 1494<domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-"> 1495 <reg32 offset="0" name="0"> 1496 </reg32> 1497 <stripe varset="chip" variants="A4XX"> 1498 <reg32 offset="1" name="1"> 1499 <bitfield name="ADDR" low="0" high="31"/> 1500 </reg32> 1501 <reg32 offset="2" name="2"> 1502 <!-- localsize is value minus one: --> 1503 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 1504 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 1505 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 1506 </reg32> 1507 </stripe> 1508 <stripe varset="chip" variants="A5XX-"> 1509 <reg32 offset="1" name="1"> 1510 <bitfield name="ADDR_LO" low="0" high="31"/> 1511 </reg32> 1512 <reg32 offset="2" name="2"> 1513 <bitfield name="ADDR_HI" low="0" high="31"/> 1514 </reg32> 1515 <reg32 offset="3" name="3"> 1516 <!-- localsize is value minus one: --> 1517 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 1518 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 1519 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 1520 </reg32> 1521 </stripe> 1522</domain> 1523 1524<domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-"> 1525 <doc>Tell CP the current operation mode, indicates save and restore procedure</doc> 1526 <enum name="a6xx_marker"> 1527 <value value="1" name="RM6_BYPASS"/> 1528 <value value="2" name="RM6_BINNING"/> 1529 <value value="4" name="RM6_GMEM"/> 1530 <value value="5" name="RM6_ENDVIS"/> 1531 <value value="6" name="RM6_RESOLVE"/> 1532 <value value="7" name="RM6_YIELD"/> 1533 <value value="8" name="RM6_COMPUTE"/> 1534 <value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) --> 1535 1536 <!-- 1537 These values come from a6xx_set_marker() in the 1538 downstream kernel, and they can only be set by the kernel 1539 --> 1540 <value value="0xd" name="RM6_IB1LIST_START"/> 1541 <value value="0xe" name="RM6_IB1LIST_END"/> 1542 <!-- IFPC - inter-frame power collapse --> 1543 <value value="0x100" name="RM6_IFPC_ENABLE"/> 1544 <value value="0x101" name="RM6_IFPC_DISABLE"/> 1545 </enum> 1546 <reg32 offset="0" name="0"> 1547 <!-- 1548 NOTE: blob driver and some versions of freedreno/turnip set 1549 b4, which is unused (at least by current sqe fw), but interferes 1550 with parsing if we extend the size of the bitfield to include 1551 b8 (only sent by kernel mode driver). Really, the way the 1552 parsing works in the firmware, only b0-b3 are considered, but 1553 if b8 is set, the low bits are interpreted differently. To 1554 model this, without getting confused by spurious b4, this is 1555 described as two overlapping bitfields: 1556 --> 1557 <bitfield name="MODE" low="0" high="8" type="a6xx_marker"/> 1558 <bitfield name="MARKER" low="0" high="3" type="a6xx_marker"/> 1559 </reg32> 1560</domain> 1561 1562<domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-"> 1563 <doc>Set internal CP registers, used to indicate context save data addresses</doc> 1564 <enum name="pseudo_reg"> 1565 <value value="0" name="SMMU_INFO"/> 1566 <value value="1" name="NON_SECURE_SAVE_ADDR"/> 1567 <value value="2" name="SECURE_SAVE_ADDR"/> 1568 <value value="3" name="NON_PRIV_SAVE_ADDR"/> 1569 <value value="4" name="COUNTER"/> 1570 </enum> 1571 <array offset="0" stride="3" length="100"> 1572 <reg32 offset="0" name="0"> 1573 <bitfield name="PSEUDO_REG" low="0" high="2" type="pseudo_reg"/> 1574 </reg32> 1575 <reg32 offset="1" name="1"> 1576 <bitfield name="LO" low="0" high="31"/> 1577 </reg32> 1578 <reg32 offset="2" name="2"> 1579 <bitfield name="HI" low="0" high="31"/> 1580 </reg32> 1581 </array> 1582</domain> 1583 1584<domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-"> 1585 <doc> 1586 Tests bit in specified register and sets predicate for CP_COND_REG_EXEC. 1587 So: 1588 1589 opcode: CP_REG_TEST (39) (2 dwords) 1590 { REG = 0xc10 | BIT = 0 } 1591 0000: 70b90001 00000c10 1592 opcode: CP_COND_REG_EXEC (47) (3 dwords) 1593 0000: 70c70002 10000000 00000004 1594 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) 1595 1596 Will execute the CP_INDIRECT_BUFFER only if b0 in the register at 1597 offset 0x0c10 is 1 1598 </doc> 1599 <reg32 offset="0" name="0"> 1600 <!-- the register to test --> 1601 <bitfield name="REG" low="0" high="17"/> 1602 <!-- the bit to test --> 1603 <bitfield name="BIT" low="20" high="24" type="uint"/> 1604 <!-- execute CP_WAIT_FOR_ME beforehand --> 1605 <bitfield name="WAIT_FOR_ME" pos="25" type="boolean"/> 1606 </reg32> 1607</domain> 1608 1609<!-- I *think* this existed at least as far back as a4xx --> 1610<domain name="CP_COND_REG_EXEC" width="32"> 1611 <enum name="compare_mode"> 1612 <!-- use the predicate bit set by CP_REG_TEST --> 1613 <value value="1" name="PRED_TEST"/> 1614 <!-- compare two registers directly for equality --> 1615 <value value="2" name="REG_COMPARE"/> 1616 <!-- test if certain render modes are set via CP_SET_MARKER --> 1617 <value value="3" name="RENDER_MODE" varset="chip" variants="A6XX-"/> 1618 </enum> 1619 <reg32 offset="0" name="0"> 1620 <bitfield name="REG0" low="0" high="17" type="hex"/> 1621 1622 <!-- 1623 Note: these bits have the same meaning, and use the same 1624 internal mechanism as the bits in CP_SET_DRAW_STATE. 1625 When RENDER_MODE is selected, they're used as 1626 a bitmask of which modes pass the test. 1627 --> 1628 1629 <!-- RM6_BINNING --> 1630 <bitfield name="BINNING" pos="25" varset="chip" variants="A6XX-" type="boolean"/> 1631 <!-- all others --> 1632 <bitfield name="GMEM" pos="26" varset="chip" variants="A6XX-" type="boolean"/> 1633 <!-- RM6_BYPASS --> 1634 <bitfield name="SYSMEM" pos="27" varset="chip" variants="A6XX-" type="boolean"/> 1635 1636 <bitfield name="MODE" low="28" high="31" type="compare_mode"/> 1637 </reg32> 1638 1639 <!-- in REG_COMPARE mode, there's an extra DWORD here with REG1 --> 1640 1641 <reg32 offset="1" name="1"> 1642 <bitfield name="DWORDS" low="0" high="31" type="uint"/> 1643 </reg32> 1644</domain> 1645 1646<domain name="CP_COND_EXEC" width="32"> 1647 <doc> 1648 Executes the following DWORDs of commands if the dword at ADDR0 1649 is not equal to 0 and the dword at ADDR1 is less than REF 1650 (signed comparison). 1651 </doc> 1652 <reg32 offset="0" name="0"> 1653 <bitfield name="ADDR0_LO" low="0" high="31"/> 1654 </reg32> 1655 <reg32 offset="1" name="1"> 1656 <bitfield name="ADDR0_HI" low="0" high="31"/> 1657 </reg32> 1658 <reg32 offset="2" name="2"> 1659 <bitfield name="ADDR1_LO" low="0" high="31"/> 1660 </reg32> 1661 <reg32 offset="3" name="3"> 1662 <bitfield name="ADDR1_HI" low="0" high="31"/> 1663 </reg32> 1664 <reg32 offset="4" name="4"> 1665 <bitfield name="REF" low="0" high="31"/> 1666 </reg32> 1667 <reg32 offset="5" name="5"> 1668 <bitfield name="DWORDS" low="0" high="31" type="uint"/> 1669 </reg32> 1670</domain> 1671 1672<domain name="CP_SET_CTXSWITCH_IB" width="32"> 1673 <doc> 1674 Used by the userspace driver to set various IB's which are 1675 executed during context save/restore for handling 1676 state that isn't restored by the 1677 context switch routine itself. 1678 </doc> 1679 <enum name="ctxswitch_ib"> 1680 <value name="RESTORE_IB" value="0"> 1681 <doc>Executed unconditionally when switching back to the context.</doc> 1682 </value> 1683 <value name="YIELD_RESTORE_IB" value="1"> 1684 <doc> 1685 Executed when switching back after switching 1686 away during execution of 1687 a CP_SET_MARKER packet with RM6_YIELD as the 1688 payload *and* the normal save routine was 1689 bypassed for a shorter one. I think this is 1690 connected to the "skipsaverestore" bit set by 1691 the kernel when preempting. 1692 </doc> 1693 </value> 1694 <value name="SAVE_IB" value="2"> 1695 <doc> 1696 Executed when switching away from the context, 1697 except for context switches initiated via 1698 CP_YIELD. 1699 </doc> 1700 </value> 1701 <value name="RB_SAVE_IB" value="3"> 1702 <doc> 1703 This can only be set by the RB (i.e. the kernel) 1704 and executes with protected mode off, but 1705 is otherwise similar to SAVE_IB. 1706 </doc> 1707 </value> 1708 </enum> 1709 <reg32 offset="0" name="0"> 1710 <bitfield name="ADDR_LO" low="0" high="31"/> 1711 </reg32> 1712 <reg32 offset="1" name="1"> 1713 <bitfield name="ADDR_HI" low="0" high="31"/> 1714 </reg32> 1715 <reg32 offset="2" name="2"> 1716 <bitfield name="DWORDS" low="0" high="19" type="uint"/> 1717 <bitfield name="TYPE" low="20" high="21" type="ctxswitch_ib"/> 1718 </reg32> 1719</domain> 1720 1721<domain name="CP_REG_WRITE" width="32"> 1722 <enum name="reg_tracker"> 1723 <doc> 1724 Keep shadow copies of these registers and only set them 1725 when drawing, avoiding redundant writes: 1726 - VPC_CNTL_0 1727 - HLSQ_CONTROL_1_REG 1728 - HLSQ_UNKNOWN_B980 1729 </doc> 1730 <value name="TRACK_CNTL_REG" value="0x1"/> 1731 <doc> 1732 Track RB_RENDER_CNTL, and insert a WFI in the following 1733 situation: 1734 - There is a write that disables binning 1735 - There was a draw with binning left enabled, but in 1736 BYPASS mode 1737 Presumably this is a hang workaround? 1738 </doc> 1739 <value name="TRACK_RENDER_CNTL" value="0x2"/> 1740 <doc> 1741 Do a mysterious CP_EVENT_WRITE 0x3f when the low bit of 1742 the data to write is 0. Used by the Vulkan blob with 1743 PC_MULTIVIEW_CNTL, but this isn't predicated on particular 1744 register(s) like the others. 1745 </doc> 1746 <value name="UNK_EVENT_WRITE" value="0x4"/> 1747 </enum> 1748 <reg32 offset="0" name="0"> 1749 <bitfield name="TRACKER" low="0" high="2" type="reg_tracker"/> 1750 </reg32> 1751</domain> 1752 1753<domain name="CP_SMMU_TABLE_UPDATE" width="32"> 1754 <doc> 1755 Note that the SMMU's definition of TTBRn can take different forms 1756 depending on the pgtable format. But a5xx+ only uses aarch64 1757 format. 1758 </doc> 1759 <reg32 offset="0" name="0"> 1760 <bitfield name="TTBR0_LO" low="0" high="31"/> 1761 </reg32> 1762 <reg32 offset="1" name="1"> 1763 <bitfield name="TTBR0_HI" low="0" high="15"/> 1764 <bitfield name="ASID" low="16" high="31"/> 1765 </reg32> 1766 <reg32 offset="2" name="2"> 1767 <doc>Unused, does not apply to aarch64 pgtable format</doc> 1768 <bitfield name="CONTEXTIDR" low="0" high="31"/> 1769 </reg32> 1770 <reg32 offset="3" name="3"> 1771 <bitfield name="CONTEXTBANK" low="0" high="31"/> 1772 </reg32> 1773</domain> 1774 1775<domain name="CP_START_BIN" width="32"> 1776 <reg32 offset="0" name="BIN_COUNT" type="uint"/> 1777 <reg64 offset="1" name="PREFIX_ADDR" type="address"/> 1778 <reg32 offset="3" name="PREFIX_DWORDS"> 1779 <doc> 1780 Size of prefix for each bin. For each bin index i, the 1781 prefix commands at PREFIX_ADDR + i * PREFIX_DWORDS are 1782 executed in an IB2 before the IB1 commands following 1783 this packet. 1784 </doc> 1785 </reg32> 1786 <reg32 offset="4" name="BODY_DWORDS"> 1787 <doc>Number of dwords after this packet until CP_END_BIN</doc> 1788 </reg32> 1789</domain> 1790 1791</database> 1792 1793