1 /*
2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "util/os_misc.h"
26 #include "pipe/p_defines.h"
27 #include "pipe/p_screen.h"
28 #include "pipe/p_state.h"
29
30 #include "util/u_cpu_detect.h"
31 #include "util/u_debug.h"
32 #include "util/u_memory.h"
33 #include "util/format/u_format.h"
34 #include "util/u_hash_table.h"
35 #include "util/u_screen.h"
36 #include "util/u_transfer_helper.h"
37 #include "util/ralloc.h"
38
39 #include <xf86drm.h>
40 #include "drm-uapi/drm_fourcc.h"
41 #include "drm-uapi/vc4_drm.h"
42 #include "vc4_screen.h"
43 #include "vc4_context.h"
44 #include "vc4_resource.h"
45
46 static const struct debug_named_value vc4_debug_options[] = {
47 { "cl", VC4_DEBUG_CL,
48 "Dump command list during creation" },
49 { "surf", VC4_DEBUG_SURFACE,
50 "Dump surface layouts" },
51 { "qpu", VC4_DEBUG_QPU,
52 "Dump generated QPU instructions" },
53 { "qir", VC4_DEBUG_QIR,
54 "Dump QPU IR during program compile" },
55 { "nir", VC4_DEBUG_NIR,
56 "Dump NIR during program compile" },
57 { "tgsi", VC4_DEBUG_TGSI,
58 "Dump TGSI during program compile" },
59 { "shaderdb", VC4_DEBUG_SHADERDB,
60 "Dump program compile information for shader-db analysis" },
61 { "perf", VC4_DEBUG_PERF,
62 "Print during performance-related events" },
63 { "norast", VC4_DEBUG_NORAST,
64 "Skip actual hardware execution of commands" },
65 { "always_flush", VC4_DEBUG_ALWAYS_FLUSH,
66 "Flush after each draw call" },
67 { "always_sync", VC4_DEBUG_ALWAYS_SYNC,
68 "Wait for finish after each flush" },
69 #ifdef USE_VC4_SIMULATOR
70 { "dump", VC4_DEBUG_DUMP,
71 "Write a GPU command stream trace file" },
72 #endif
73 { NULL }
74 };
75
76 DEBUG_GET_ONCE_FLAGS_OPTION(vc4_debug, "VC4_DEBUG", vc4_debug_options, 0)
77 uint32_t vc4_debug;
78
79 static const char *
vc4_screen_get_name(struct pipe_screen * pscreen)80 vc4_screen_get_name(struct pipe_screen *pscreen)
81 {
82 struct vc4_screen *screen = vc4_screen(pscreen);
83
84 if (!screen->name) {
85 screen->name = ralloc_asprintf(screen,
86 "VC4 V3D %d.%d",
87 screen->v3d_ver / 10,
88 screen->v3d_ver % 10);
89 }
90
91 return screen->name;
92 }
93
94 static const char *
vc4_screen_get_vendor(struct pipe_screen * pscreen)95 vc4_screen_get_vendor(struct pipe_screen *pscreen)
96 {
97 return "Broadcom";
98 }
99
100 static void
vc4_screen_destroy(struct pipe_screen * pscreen)101 vc4_screen_destroy(struct pipe_screen *pscreen)
102 {
103 struct vc4_screen *screen = vc4_screen(pscreen);
104
105 _mesa_hash_table_destroy(screen->bo_handles, NULL);
106 vc4_bufmgr_destroy(pscreen);
107 slab_destroy_parent(&screen->transfer_pool);
108 if (screen->ro)
109 screen->ro->destroy(screen->ro);
110
111 #ifdef USE_VC4_SIMULATOR
112 vc4_simulator_destroy(screen);
113 #endif
114
115 u_transfer_helper_destroy(pscreen->transfer_helper);
116
117 close(screen->fd);
118 ralloc_free(pscreen);
119 }
120
121 static bool
vc4_has_feature(struct vc4_screen * screen,uint32_t feature)122 vc4_has_feature(struct vc4_screen *screen, uint32_t feature)
123 {
124 struct drm_vc4_get_param p = {
125 .param = feature,
126 };
127 int ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &p);
128
129 if (ret != 0)
130 return false;
131
132 return p.value;
133 }
134
135 static int
vc4_screen_get_param(struct pipe_screen * pscreen,enum pipe_cap param)136 vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
137 {
138 struct vc4_screen *screen = vc4_screen(pscreen);
139
140 switch (param) {
141 /* Supported features (boolean caps). */
142 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
143 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
144 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
145 case PIPE_CAP_NPOT_TEXTURES:
146 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
147 case PIPE_CAP_TEXTURE_MULTISAMPLE:
148 case PIPE_CAP_TEXTURE_SWIZZLE:
149 case PIPE_CAP_TEXTURE_BARRIER:
150 case PIPE_CAP_TGSI_TEXCOORD:
151 return 1;
152
153 case PIPE_CAP_NATIVE_FENCE_FD:
154 return screen->has_syncobj;
155
156 case PIPE_CAP_TILE_RASTER_ORDER:
157 return vc4_has_feature(screen,
158 DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER);
159
160 /* lying for GL 2.0 */
161 case PIPE_CAP_OCCLUSION_QUERY:
162 case PIPE_CAP_POINT_SPRITE:
163 return 1;
164
165 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
166 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
167 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
168 return 1;
169
170 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
171 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
172 return 1;
173
174 /* Texturing. */
175 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
176 return 2048;
177 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
178 return VC4_MAX_MIP_LEVELS;
179 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
180 /* Note: Not supported in hardware, just faking it. */
181 return 5;
182
183 case PIPE_CAP_MAX_VARYINGS:
184 return 8;
185
186 case PIPE_CAP_VENDOR_ID:
187 return 0x14E4;
188 case PIPE_CAP_ACCELERATED:
189 return 1;
190 case PIPE_CAP_VIDEO_MEMORY: {
191 uint64_t system_memory;
192
193 if (!os_get_total_physical_memory(&system_memory))
194 return 0;
195
196 return (int)(system_memory >> 20);
197 }
198 case PIPE_CAP_UMA:
199 return 1;
200
201 case PIPE_CAP_ALPHA_TEST:
202 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
203 case PIPE_CAP_TWO_SIDED_COLOR:
204 case PIPE_CAP_TEXRECT:
205 return 0;
206
207 case PIPE_CAP_SUPPORTED_PRIM_MODES:
208 return screen->prim_types;
209
210 default:
211 return u_pipe_screen_get_param_defaults(pscreen, param);
212 }
213 }
214
215 static float
vc4_screen_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)216 vc4_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
217 {
218 switch (param) {
219 case PIPE_CAPF_MAX_LINE_WIDTH:
220 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
221 return 32;
222
223 case PIPE_CAPF_MAX_POINT_WIDTH:
224 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
225 return 512.0f;
226
227 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
228 return 0.0f;
229 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
230 return 0.0f;
231
232 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
233 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
234 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
235 return 0.0f;
236 default:
237 fprintf(stderr, "unknown paramf %d\n", param);
238 return 0;
239 }
240 }
241
242 static int
vc4_screen_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)243 vc4_screen_get_shader_param(struct pipe_screen *pscreen,
244 enum pipe_shader_type shader,
245 enum pipe_shader_cap param)
246 {
247 if (shader != PIPE_SHADER_VERTEX &&
248 shader != PIPE_SHADER_FRAGMENT) {
249 return 0;
250 }
251
252 /* this is probably not totally correct.. but it's a start: */
253 switch (param) {
254 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
255 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
256 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
257 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
258 return 16384;
259
260 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
261 return vc4_screen(pscreen)->has_control_flow;
262
263 case PIPE_SHADER_CAP_MAX_INPUTS:
264 return 8;
265 case PIPE_SHADER_CAP_MAX_OUTPUTS:
266 return shader == PIPE_SHADER_FRAGMENT ? 1 : 8;
267 case PIPE_SHADER_CAP_MAX_TEMPS:
268 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
269 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
270 return 16 * 1024 * sizeof(float);
271 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
272 return 1;
273 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
274 return 0;
275 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
276 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
277 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
278 return 0;
279 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
280 return 1;
281 case PIPE_SHADER_CAP_SUBROUTINES:
282 return 0;
283 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
284 return 0;
285 case PIPE_SHADER_CAP_INTEGERS:
286 return 1;
287 case PIPE_SHADER_CAP_INT64_ATOMICS:
288 case PIPE_SHADER_CAP_FP16:
289 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
290 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
291 case PIPE_SHADER_CAP_INT16:
292 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
293 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
294 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
295 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
296 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
297 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
298 return 0;
299 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
300 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
301 return VC4_MAX_TEXTURE_SAMPLERS;
302 case PIPE_SHADER_CAP_PREFERRED_IR:
303 return PIPE_SHADER_IR_NIR;
304 case PIPE_SHADER_CAP_SUPPORTED_IRS:
305 return 1 << PIPE_SHADER_IR_NIR;
306 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
307 return 32;
308 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
309 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
310 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
311 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
312 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
313 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
314 return 0;
315 default:
316 fprintf(stderr, "unknown shader param %d\n", param);
317 return 0;
318 }
319 return 0;
320 }
321
322 static bool
vc4_screen_is_format_supported(struct pipe_screen * pscreen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned usage)323 vc4_screen_is_format_supported(struct pipe_screen *pscreen,
324 enum pipe_format format,
325 enum pipe_texture_target target,
326 unsigned sample_count,
327 unsigned storage_sample_count,
328 unsigned usage)
329 {
330 struct vc4_screen *screen = vc4_screen(pscreen);
331
332 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
333 return false;
334
335 if (sample_count > 1 && sample_count != VC4_MAX_SAMPLES)
336 return false;
337
338 if (target >= PIPE_MAX_TEXTURE_TYPES) {
339 return false;
340 }
341
342 if (usage & PIPE_BIND_VERTEX_BUFFER) {
343 switch (format) {
344 case PIPE_FORMAT_R32G32B32A32_FLOAT:
345 case PIPE_FORMAT_R32G32B32_FLOAT:
346 case PIPE_FORMAT_R32G32_FLOAT:
347 case PIPE_FORMAT_R32_FLOAT:
348 case PIPE_FORMAT_R32G32B32A32_SNORM:
349 case PIPE_FORMAT_R32G32B32_SNORM:
350 case PIPE_FORMAT_R32G32_SNORM:
351 case PIPE_FORMAT_R32_SNORM:
352 case PIPE_FORMAT_R32G32B32A32_SSCALED:
353 case PIPE_FORMAT_R32G32B32_SSCALED:
354 case PIPE_FORMAT_R32G32_SSCALED:
355 case PIPE_FORMAT_R32_SSCALED:
356 case PIPE_FORMAT_R16G16B16A16_UNORM:
357 case PIPE_FORMAT_R16G16B16_UNORM:
358 case PIPE_FORMAT_R16G16_UNORM:
359 case PIPE_FORMAT_R16_UNORM:
360 case PIPE_FORMAT_R16G16B16A16_SNORM:
361 case PIPE_FORMAT_R16G16B16_SNORM:
362 case PIPE_FORMAT_R16G16_SNORM:
363 case PIPE_FORMAT_R16_SNORM:
364 case PIPE_FORMAT_R16G16B16A16_USCALED:
365 case PIPE_FORMAT_R16G16B16_USCALED:
366 case PIPE_FORMAT_R16G16_USCALED:
367 case PIPE_FORMAT_R16_USCALED:
368 case PIPE_FORMAT_R16G16B16A16_SSCALED:
369 case PIPE_FORMAT_R16G16B16_SSCALED:
370 case PIPE_FORMAT_R16G16_SSCALED:
371 case PIPE_FORMAT_R16_SSCALED:
372 case PIPE_FORMAT_R8G8B8A8_UNORM:
373 case PIPE_FORMAT_R8G8B8_UNORM:
374 case PIPE_FORMAT_R8G8_UNORM:
375 case PIPE_FORMAT_R8_UNORM:
376 case PIPE_FORMAT_R8G8B8A8_SNORM:
377 case PIPE_FORMAT_R8G8B8_SNORM:
378 case PIPE_FORMAT_R8G8_SNORM:
379 case PIPE_FORMAT_R8_SNORM:
380 case PIPE_FORMAT_R8G8B8A8_USCALED:
381 case PIPE_FORMAT_R8G8B8_USCALED:
382 case PIPE_FORMAT_R8G8_USCALED:
383 case PIPE_FORMAT_R8_USCALED:
384 case PIPE_FORMAT_R8G8B8A8_SSCALED:
385 case PIPE_FORMAT_R8G8B8_SSCALED:
386 case PIPE_FORMAT_R8G8_SSCALED:
387 case PIPE_FORMAT_R8_SSCALED:
388 break;
389 default:
390 return false;
391 }
392 }
393
394 if ((usage & PIPE_BIND_RENDER_TARGET) &&
395 !vc4_rt_format_supported(format)) {
396 return false;
397 }
398
399 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
400 (!vc4_tex_format_supported(format) ||
401 (format == PIPE_FORMAT_ETC1_RGB8 && !screen->has_etc1))) {
402 return false;
403 }
404
405 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
406 format != PIPE_FORMAT_S8_UINT_Z24_UNORM &&
407 format != PIPE_FORMAT_X8Z24_UNORM) {
408 return false;
409 }
410
411 if ((usage & PIPE_BIND_INDEX_BUFFER) &&
412 format != PIPE_FORMAT_R8_UINT &&
413 format != PIPE_FORMAT_R16_UINT) {
414 return false;
415 }
416
417 return true;
418 }
419
vc4_get_modifiers(struct pipe_screen * pscreen,int * num)420 static const uint64_t *vc4_get_modifiers(struct pipe_screen *pscreen, int *num)
421 {
422 struct vc4_screen *screen = vc4_screen(pscreen);
423 static const uint64_t all_modifiers[] = {
424 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
425 DRM_FORMAT_MOD_LINEAR,
426 };
427 int m;
428
429 /* We support both modifiers (tiled and linear) for all sampler
430 * formats, but if we don't have the DRM_VC4_GET_TILING ioctl
431 * we shouldn't advertise the tiled formats.
432 */
433 if (screen->has_tiling_ioctl) {
434 m = 0;
435 *num = 2;
436 } else{
437 m = 1;
438 *num = 1;
439 }
440
441 return &all_modifiers[m];
442 }
443
444 static void
vc4_screen_query_dmabuf_modifiers(struct pipe_screen * pscreen,enum pipe_format format,int max,uint64_t * modifiers,unsigned int * external_only,int * count)445 vc4_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
446 enum pipe_format format, int max,
447 uint64_t *modifiers,
448 unsigned int *external_only,
449 int *count)
450 {
451 const uint64_t *available_modifiers;
452 int i;
453 bool tex_will_lower;
454 int num_modifiers;
455
456 available_modifiers = vc4_get_modifiers(pscreen, &num_modifiers);
457
458 if (!modifiers) {
459 *count = num_modifiers;
460 return;
461 }
462
463 *count = MIN2(max, num_modifiers);
464 tex_will_lower = !vc4_tex_format_supported(format);
465 for (i = 0; i < *count; i++) {
466 modifiers[i] = available_modifiers[i];
467 if (external_only)
468 external_only[i] = tex_will_lower;
469 }
470 }
471
472 static bool
vc4_screen_is_dmabuf_modifier_supported(struct pipe_screen * pscreen,uint64_t modifier,enum pipe_format format,bool * external_only)473 vc4_screen_is_dmabuf_modifier_supported(struct pipe_screen *pscreen,
474 uint64_t modifier,
475 enum pipe_format format,
476 bool *external_only)
477 {
478 const uint64_t *available_modifiers;
479 int i, num_modifiers;
480
481 available_modifiers = vc4_get_modifiers(pscreen, &num_modifiers);
482
483 for (i = 0; i < num_modifiers; i++) {
484 if (modifier == available_modifiers[i]) {
485 if (external_only)
486 *external_only = !vc4_tex_format_supported(format);
487
488 return true;
489 }
490 }
491
492 return false;
493 }
494
495 static bool
vc4_get_chip_info(struct vc4_screen * screen)496 vc4_get_chip_info(struct vc4_screen *screen)
497 {
498 struct drm_vc4_get_param ident0 = {
499 .param = DRM_VC4_PARAM_V3D_IDENT0,
500 };
501 struct drm_vc4_get_param ident1 = {
502 .param = DRM_VC4_PARAM_V3D_IDENT1,
503 };
504 int ret;
505
506 ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident0);
507 if (ret != 0) {
508 if (errno == EINVAL) {
509 /* Backwards compatibility with 2835 kernels which
510 * only do V3D 2.1.
511 */
512 screen->v3d_ver = 21;
513 return true;
514 } else {
515 fprintf(stderr, "Couldn't get V3D IDENT0: %s\n",
516 strerror(errno));
517 return false;
518 }
519 }
520 ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident1);
521 if (ret != 0) {
522 fprintf(stderr, "Couldn't get V3D IDENT1: %s\n",
523 strerror(errno));
524 return false;
525 }
526
527 uint32_t major = (ident0.value >> 24) & 0xff;
528 uint32_t minor = (ident1.value >> 0) & 0xf;
529 screen->v3d_ver = major * 10 + minor;
530
531 if (screen->v3d_ver != 21 && screen->v3d_ver != 26) {
532 fprintf(stderr,
533 "V3D %d.%d not supported by this version of Mesa.\n",
534 screen->v3d_ver / 10,
535 screen->v3d_ver % 10);
536 return false;
537 }
538
539 return true;
540 }
541
542 struct pipe_screen *
vc4_screen_create(int fd,struct renderonly * ro)543 vc4_screen_create(int fd, struct renderonly *ro)
544 {
545 struct vc4_screen *screen = rzalloc(NULL, struct vc4_screen);
546 uint64_t syncobj_cap = 0;
547 struct pipe_screen *pscreen;
548 int err;
549
550 pscreen = &screen->base;
551
552 pscreen->destroy = vc4_screen_destroy;
553 pscreen->get_param = vc4_screen_get_param;
554 pscreen->get_paramf = vc4_screen_get_paramf;
555 pscreen->get_shader_param = vc4_screen_get_shader_param;
556 pscreen->context_create = vc4_context_create;
557 pscreen->is_format_supported = vc4_screen_is_format_supported;
558
559 screen->fd = fd;
560 screen->ro = ro;
561
562 list_inithead(&screen->bo_cache.time_list);
563 (void) mtx_init(&screen->bo_handles_mutex, mtx_plain);
564 screen->bo_handles = util_hash_table_create_ptr_keys();
565
566 screen->has_control_flow =
567 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_BRANCHES);
568 screen->has_etc1 =
569 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_ETC1);
570 screen->has_threaded_fs =
571 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_THREADED_FS);
572 screen->has_madvise =
573 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_MADVISE);
574 screen->has_perfmon_ioctl =
575 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_PERFMON);
576
577 err = drmGetCap(fd, DRM_CAP_SYNCOBJ, &syncobj_cap);
578 if (err == 0 && syncobj_cap)
579 screen->has_syncobj = true;
580
581 if (!vc4_get_chip_info(screen))
582 goto fail;
583
584 util_cpu_detect();
585
586 slab_create_parent(&screen->transfer_pool, sizeof(struct vc4_transfer), 16);
587
588 vc4_fence_screen_init(screen);
589
590 vc4_debug = debug_get_option_vc4_debug();
591 if (vc4_debug & VC4_DEBUG_SHADERDB)
592 vc4_debug |= VC4_DEBUG_NORAST;
593
594 #ifdef USE_VC4_SIMULATOR
595 vc4_simulator_init(screen);
596 #endif
597
598 vc4_resource_screen_init(pscreen);
599
600 pscreen->get_name = vc4_screen_get_name;
601 pscreen->get_vendor = vc4_screen_get_vendor;
602 pscreen->get_device_vendor = vc4_screen_get_vendor;
603 pscreen->get_compiler_options = vc4_screen_get_compiler_options;
604 pscreen->query_dmabuf_modifiers = vc4_screen_query_dmabuf_modifiers;
605 pscreen->is_dmabuf_modifier_supported = vc4_screen_is_dmabuf_modifier_supported;
606
607 if (screen->has_perfmon_ioctl) {
608 pscreen->get_driver_query_group_info = vc4_get_driver_query_group_info;
609 pscreen->get_driver_query_info = vc4_get_driver_query_info;
610 }
611
612 /* Generate the bitmask of supported draw primitives. */
613 screen->prim_types = BITFIELD_BIT(PIPE_PRIM_POINTS) |
614 BITFIELD_BIT(PIPE_PRIM_LINES) |
615 BITFIELD_BIT(PIPE_PRIM_LINE_LOOP) |
616 BITFIELD_BIT(PIPE_PRIM_LINE_STRIP) |
617 BITFIELD_BIT(PIPE_PRIM_TRIANGLES) |
618 BITFIELD_BIT(PIPE_PRIM_TRIANGLE_STRIP) |
619 BITFIELD_BIT(PIPE_PRIM_TRIANGLE_FAN);
620
621
622 return pscreen;
623
624 fail:
625 close(fd);
626 ralloc_free(pscreen);
627 return NULL;
628 }
629