1#! /usr/bin/env perl 2# Copyright 2005-2020 The OpenSSL Project Authors. All Rights Reserved. 3# 4# Licensed under the OpenSSL license (the "License"). You may not use 5# this file except in compliance with the License. You can obtain a copy 6# in the file LICENSE in the source distribution or at 7# https://www.openssl.org/source/license.html 8 9# 10# ==================================================================== 11# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL 12# project. The module is, however, dual licensed under OpenSSL and 13# CRYPTOGAMS licenses depending on where you obtain it. For further 14# details see http://www.openssl.org/~appro/cryptogams/. 15# ==================================================================== 16# 17# July 2004 18# 19# 2.22x RC4 tune-up:-) It should be noted though that my hand [as in 20# "hand-coded assembler"] doesn't stand for the whole improvement 21# coefficient. It turned out that eliminating RC4_CHAR from config 22# line results in ~40% improvement (yes, even for C implementation). 23# Presumably it has everything to do with AMD cache architecture and 24# RAW or whatever penalties. Once again! The module *requires* config 25# line *without* RC4_CHAR! As for coding "secret," I bet on partial 26# register arithmetics. For example instead of 'inc %r8; and $255,%r8' 27# I simply 'inc %r8b'. Even though optimization manual discourages 28# to operate on partial registers, it turned out to be the best bet. 29# At least for AMD... How IA32E would perform remains to be seen... 30 31# November 2004 32# 33# As was shown by Marc Bevand reordering of couple of load operations 34# results in even higher performance gain of 3.3x:-) At least on 35# Opteron... For reference, 1x in this case is RC4_CHAR C-code 36# compiled with gcc 3.3.2, which performs at ~54MBps per 1GHz clock. 37# Latter means that if you want to *estimate* what to expect from 38# *your* Opteron, then multiply 54 by 3.3 and clock frequency in GHz. 39 40# November 2004 41# 42# Intel P4 EM64T core was found to run the AMD64 code really slow... 43# The only way to achieve comparable performance on P4 was to keep 44# RC4_CHAR. Kind of ironic, huh? As it's apparently impossible to 45# compose blended code, which would perform even within 30% marginal 46# on either AMD and Intel platforms, I implement both cases. See 47# rc4_skey.c for further details... 48 49# April 2005 50# 51# P4 EM64T core appears to be "allergic" to 64-bit inc/dec. Replacing 52# those with add/sub results in 50% performance improvement of folded 53# loop... 54 55# May 2005 56# 57# As was shown by Zou Nanhai loop unrolling can improve Intel EM64T 58# performance by >30% [unlike P4 32-bit case that is]. But this is 59# provided that loads are reordered even more aggressively! Both code 60# paths, AMD64 and EM64T, reorder loads in essentially same manner 61# as my IA-64 implementation. On Opteron this resulted in modest 5% 62# improvement [I had to test it], while final Intel P4 performance 63# achieves respectful 432MBps on 2.8GHz processor now. For reference. 64# If executed on Xeon, current RC4_CHAR code-path is 2.7x faster than 65# RC4_INT code-path. While if executed on Opteron, it's only 25% 66# slower than the RC4_INT one [meaning that if CPU µ-arch detection 67# is not implemented, then this final RC4_CHAR code-path should be 68# preferred, as it provides better *all-round* performance]. 69 70# March 2007 71# 72# Intel Core2 was observed to perform poorly on both code paths:-( It 73# apparently suffers from some kind of partial register stall, which 74# occurs in 64-bit mode only [as virtually identical 32-bit loop was 75# observed to outperform 64-bit one by almost 50%]. Adding two movzb to 76# cloop1 boosts its performance by 80%! This loop appears to be optimal 77# fit for Core2 and therefore the code was modified to skip cloop8 on 78# this CPU. 79 80# May 2010 81# 82# Intel Westmere was observed to perform suboptimally. Adding yet 83# another movzb to cloop1 improved performance by almost 50%! Core2 84# performance is improved too, but nominally... 85 86# May 2011 87# 88# The only code path that was not modified is P4-specific one. Non-P4 89# Intel code path optimization is heavily based on submission by Maxim 90# Perminov, Maxim Locktyukhin and Jim Guilford of Intel. I've used 91# some of the ideas even in attempt to optimize the original RC4_INT 92# code path... Current performance in cycles per processed byte (less 93# is better) and improvement coefficients relative to previous 94# version of this module are: 95# 96# Opteron 5.3/+0%(*) 97# P4 6.5 98# Core2 6.2/+15%(**) 99# Westmere 4.2/+60% 100# Sandy Bridge 4.2/+120% 101# Atom 9.3/+80% 102# VIA Nano 6.4/+4% 103# Ivy Bridge 4.1/+30% 104# Bulldozer 4.5/+30%(*) 105# 106# (*) But corresponding loop has less instructions, which should have 107# positive effect on upcoming Bulldozer, which has one less ALU. 108# For reference, Intel code runs at 6.8 cpb rate on Opteron. 109# (**) Note that Core2 result is ~15% lower than corresponding result 110# for 32-bit code, meaning that it's possible to improve it, 111# but more than likely at the cost of the others (see rc4-586.pl 112# to get the idea)... 113 114$flavour = shift; 115$output = shift; 116if ($flavour =~ /\./) { $output = $flavour; undef $flavour; } 117 118$win64=0; $win64=1 if ($flavour =~ /[nm]asm|mingw64/ || $output =~ /\.asm$/); 119 120$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1; 121( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or 122( $xlate="${dir}../../perlasm/x86_64-xlate.pl" and -f $xlate) or 123die "can't locate x86_64-xlate.pl"; 124 125open OUT,"| \"$^X\" \"$xlate\" $flavour \"$output\""; 126*STDOUT=*OUT; 127 128$dat="%rdi"; # arg1 129$len="%rsi"; # arg2 130$inp="%rdx"; # arg3 131$out="%rcx"; # arg4 132 133{ 134$code=<<___; 135.text 136.extern OPENSSL_ia32cap_P 137 138.globl RC4 139.type RC4,\@function,4 140.align 16 141RC4: 142.cfi_startproc 143 or $len,$len 144 jne .Lentry 145 ret 146.Lentry: 147 push %rbx 148.cfi_push %rbx 149 push %r12 150.cfi_push %r12 151 push %r13 152.cfi_push %r13 153.Lprologue: 154 mov $len,%r11 155 mov $inp,%r12 156 mov $out,%r13 157___ 158my $len="%r11"; # reassign input arguments 159my $inp="%r12"; 160my $out="%r13"; 161 162my @XX=("%r10","%rsi"); 163my @TX=("%rax","%rbx"); 164my $YY="%rcx"; 165my $TY="%rdx"; 166 167$code.=<<___; 168 xor $XX[0],$XX[0] 169 xor $YY,$YY 170 171 lea 8($dat),$dat 172 mov -8($dat),$XX[0]#b 173 mov -4($dat),$YY#b 174 cmpl \$-1,256($dat) 175 je .LRC4_CHAR 176 mov OPENSSL_ia32cap_P(%rip),%r8d 177 xor $TX[1],$TX[1] 178 inc $XX[0]#b 179 sub $XX[0],$TX[1] 180 sub $inp,$out 181 movl ($dat,$XX[0],4),$TX[0]#d 182 test \$-16,$len 183 jz .Lloop1 184 bt \$30,%r8d # Intel CPU? 185 jc .Lintel 186 and \$7,$TX[1] 187 lea 1($XX[0]),$XX[1] 188 jz .Loop8 189 sub $TX[1],$len 190.Loop8_warmup: 191 add $TX[0]#b,$YY#b 192 movl ($dat,$YY,4),$TY#d 193 movl $TX[0]#d,($dat,$YY,4) 194 movl $TY#d,($dat,$XX[0],4) 195 add $TY#b,$TX[0]#b 196 inc $XX[0]#b 197 movl ($dat,$TX[0],4),$TY#d 198 movl ($dat,$XX[0],4),$TX[0]#d 199 xorb ($inp),$TY#b 200 movb $TY#b,($out,$inp) 201 lea 1($inp),$inp 202 dec $TX[1] 203 jnz .Loop8_warmup 204 205 lea 1($XX[0]),$XX[1] 206 jmp .Loop8 207.align 16 208.Loop8: 209___ 210for ($i=0;$i<8;$i++) { 211$code.=<<___ if ($i==7); 212 add \$8,$XX[1]#b 213___ 214$code.=<<___; 215 add $TX[0]#b,$YY#b 216 movl ($dat,$YY,4),$TY#d 217 movl $TX[0]#d,($dat,$YY,4) 218 movl `4*($i==7?-1:$i)`($dat,$XX[1],4),$TX[1]#d 219 ror \$8,%r8 # ror is redundant when $i=0 220 movl $TY#d,4*$i($dat,$XX[0],4) 221 add $TX[0]#b,$TY#b 222 movb ($dat,$TY,4),%r8b 223___ 224push(@TX,shift(@TX)); #push(@XX,shift(@XX)); # "rotate" registers 225} 226$code.=<<___; 227 add \$8,$XX[0]#b 228 ror \$8,%r8 229 sub \$8,$len 230 231 xor ($inp),%r8 232 mov %r8,($out,$inp) 233 lea 8($inp),$inp 234 235 test \$-8,$len 236 jnz .Loop8 237 cmp \$0,$len 238 jne .Lloop1 239 jmp .Lexit 240 241.align 16 242.Lintel: 243 test \$-32,$len 244 jz .Lloop1 245 and \$15,$TX[1] 246 jz .Loop16_is_hot 247 sub $TX[1],$len 248.Loop16_warmup: 249 add $TX[0]#b,$YY#b 250 movl ($dat,$YY,4),$TY#d 251 movl $TX[0]#d,($dat,$YY,4) 252 movl $TY#d,($dat,$XX[0],4) 253 add $TY#b,$TX[0]#b 254 inc $XX[0]#b 255 movl ($dat,$TX[0],4),$TY#d 256 movl ($dat,$XX[0],4),$TX[0]#d 257 xorb ($inp),$TY#b 258 movb $TY#b,($out,$inp) 259 lea 1($inp),$inp 260 dec $TX[1] 261 jnz .Loop16_warmup 262 263 mov $YY,$TX[1] 264 xor $YY,$YY 265 mov $TX[1]#b,$YY#b 266 267.Loop16_is_hot: 268 lea ($dat,$XX[0],4),$XX[1] 269___ 270sub RC4_loop { 271 my $i=shift; 272 my $j=$i<0?0:$i; 273 my $xmm="%xmm".($j&1); 274 275 $code.=" add \$16,$XX[0]#b\n" if ($i==15); 276 $code.=" movdqu ($inp),%xmm2\n" if ($i==15); 277 $code.=" add $TX[0]#b,$YY#b\n" if ($i<=0); 278 $code.=" movl ($dat,$YY,4),$TY#d\n"; 279 $code.=" pxor %xmm0,%xmm2\n" if ($i==0); 280 $code.=" psllq \$8,%xmm1\n" if ($i==0); 281 $code.=" pxor $xmm,$xmm\n" if ($i<=1); 282 $code.=" movl $TX[0]#d,($dat,$YY,4)\n"; 283 $code.=" add $TY#b,$TX[0]#b\n"; 284 $code.=" movl `4*($j+1)`($XX[1]),$TX[1]#d\n" if ($i<15); 285 $code.=" movz $TX[0]#b,$TX[0]#d\n"; 286 $code.=" movl $TY#d,4*$j($XX[1])\n"; 287 $code.=" pxor %xmm1,%xmm2\n" if ($i==0); 288 $code.=" lea ($dat,$XX[0],4),$XX[1]\n" if ($i==15); 289 $code.=" add $TX[1]#b,$YY#b\n" if ($i<15); 290 $code.=" pinsrw \$`($j>>1)&7`,($dat,$TX[0],4),$xmm\n"; 291 $code.=" movdqu %xmm2,($out,$inp)\n" if ($i==0); 292 $code.=" lea 16($inp),$inp\n" if ($i==0); 293 $code.=" movl ($XX[1]),$TX[1]#d\n" if ($i==15); 294} 295 RC4_loop(-1); 296$code.=<<___; 297 jmp .Loop16_enter 298.align 16 299.Loop16: 300___ 301 302for ($i=0;$i<16;$i++) { 303 $code.=".Loop16_enter:\n" if ($i==1); 304 RC4_loop($i); 305 push(@TX,shift(@TX)); # "rotate" registers 306} 307$code.=<<___; 308 mov $YY,$TX[1] 309 xor $YY,$YY # keyword to partial register 310 sub \$16,$len 311 mov $TX[1]#b,$YY#b 312 test \$-16,$len 313 jnz .Loop16 314 315 psllq \$8,%xmm1 316 pxor %xmm0,%xmm2 317 pxor %xmm1,%xmm2 318 movdqu %xmm2,($out,$inp) 319 lea 16($inp),$inp 320 321 cmp \$0,$len 322 jne .Lloop1 323 jmp .Lexit 324 325.align 16 326.Lloop1: 327 add $TX[0]#b,$YY#b 328 movl ($dat,$YY,4),$TY#d 329 movl $TX[0]#d,($dat,$YY,4) 330 movl $TY#d,($dat,$XX[0],4) 331 add $TY#b,$TX[0]#b 332 inc $XX[0]#b 333 movl ($dat,$TX[0],4),$TY#d 334 movl ($dat,$XX[0],4),$TX[0]#d 335 xorb ($inp),$TY#b 336 movb $TY#b,($out,$inp) 337 lea 1($inp),$inp 338 dec $len 339 jnz .Lloop1 340 jmp .Lexit 341 342.align 16 343.LRC4_CHAR: 344 add \$1,$XX[0]#b 345 movzb ($dat,$XX[0]),$TX[0]#d 346 test \$-8,$len 347 jz .Lcloop1 348 jmp .Lcloop8 349.align 16 350.Lcloop8: 351 mov ($inp),%r8d 352 mov 4($inp),%r9d 353___ 354# unroll 2x4-wise, because 64-bit rotates kill Intel P4... 355for ($i=0;$i<4;$i++) { 356$code.=<<___; 357 add $TX[0]#b,$YY#b 358 lea 1($XX[0]),$XX[1] 359 movzb ($dat,$YY),$TY#d 360 movzb $XX[1]#b,$XX[1]#d 361 movzb ($dat,$XX[1]),$TX[1]#d 362 movb $TX[0]#b,($dat,$YY) 363 cmp $XX[1],$YY 364 movb $TY#b,($dat,$XX[0]) 365 jne .Lcmov$i # Intel cmov is sloooow... 366 mov $TX[0],$TX[1] 367.Lcmov$i: 368 add $TX[0]#b,$TY#b 369 xor ($dat,$TY),%r8b 370 ror \$8,%r8d 371___ 372push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers 373} 374for ($i=4;$i<8;$i++) { 375$code.=<<___; 376 add $TX[0]#b,$YY#b 377 lea 1($XX[0]),$XX[1] 378 movzb ($dat,$YY),$TY#d 379 movzb $XX[1]#b,$XX[1]#d 380 movzb ($dat,$XX[1]),$TX[1]#d 381 movb $TX[0]#b,($dat,$YY) 382 cmp $XX[1],$YY 383 movb $TY#b,($dat,$XX[0]) 384 jne .Lcmov$i # Intel cmov is sloooow... 385 mov $TX[0],$TX[1] 386.Lcmov$i: 387 add $TX[0]#b,$TY#b 388 xor ($dat,$TY),%r9b 389 ror \$8,%r9d 390___ 391push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers 392} 393$code.=<<___; 394 lea -8($len),$len 395 mov %r8d,($out) 396 lea 8($inp),$inp 397 mov %r9d,4($out) 398 lea 8($out),$out 399 400 test \$-8,$len 401 jnz .Lcloop8 402 cmp \$0,$len 403 jne .Lcloop1 404 jmp .Lexit 405___ 406$code.=<<___; 407.align 16 408.Lcloop1: 409 add $TX[0]#b,$YY#b 410 movzb $YY#b,$YY#d 411 movzb ($dat,$YY),$TY#d 412 movb $TX[0]#b,($dat,$YY) 413 movb $TY#b,($dat,$XX[0]) 414 add $TX[0]#b,$TY#b 415 add \$1,$XX[0]#b 416 movzb $TY#b,$TY#d 417 movzb $XX[0]#b,$XX[0]#d 418 movzb ($dat,$TY),$TY#d 419 movzb ($dat,$XX[0]),$TX[0]#d 420 xorb ($inp),$TY#b 421 lea 1($inp),$inp 422 movb $TY#b,($out) 423 lea 1($out),$out 424 sub \$1,$len 425 jnz .Lcloop1 426 jmp .Lexit 427 428.align 16 429.Lexit: 430 sub \$1,$XX[0]#b 431 movl $XX[0]#d,-8($dat) 432 movl $YY#d,-4($dat) 433 434 mov (%rsp),%r13 435.cfi_restore %r13 436 mov 8(%rsp),%r12 437.cfi_restore %r12 438 mov 16(%rsp),%rbx 439.cfi_restore %rbx 440 add \$24,%rsp 441.cfi_adjust_cfa_offset -24 442.Lepilogue: 443 ret 444.cfi_endproc 445.size RC4,.-RC4 446___ 447} 448 449$idx="%r8"; 450$ido="%r9"; 451 452$code.=<<___; 453.globl RC4_set_key 454.type RC4_set_key,\@function,3 455.align 16 456RC4_set_key: 457.cfi_startproc 458 lea 8($dat),$dat 459 lea ($inp,$len),$inp 460 neg $len 461 mov $len,%rcx 462 xor %eax,%eax 463 xor $ido,$ido 464 xor %r10,%r10 465 xor %r11,%r11 466 467 mov OPENSSL_ia32cap_P(%rip),$idx#d 468 bt \$20,$idx#d # RC4_CHAR? 469 jc .Lc1stloop 470 jmp .Lw1stloop 471 472.align 16 473.Lw1stloop: 474 mov %eax,($dat,%rax,4) 475 add \$1,%al 476 jnc .Lw1stloop 477 478 xor $ido,$ido 479 xor $idx,$idx 480.align 16 481.Lw2ndloop: 482 mov ($dat,$ido,4),%r10d 483 add ($inp,$len,1),$idx#b 484 add %r10b,$idx#b 485 add \$1,$len 486 mov ($dat,$idx,4),%r11d 487 cmovz %rcx,$len 488 mov %r10d,($dat,$idx,4) 489 mov %r11d,($dat,$ido,4) 490 add \$1,$ido#b 491 jnc .Lw2ndloop 492 jmp .Lexit_key 493 494.align 16 495.Lc1stloop: 496 mov %al,($dat,%rax) 497 add \$1,%al 498 jnc .Lc1stloop 499 500 xor $ido,$ido 501 xor $idx,$idx 502.align 16 503.Lc2ndloop: 504 mov ($dat,$ido),%r10b 505 add ($inp,$len),$idx#b 506 add %r10b,$idx#b 507 add \$1,$len 508 mov ($dat,$idx),%r11b 509 jnz .Lcnowrap 510 mov %rcx,$len 511.Lcnowrap: 512 mov %r10b,($dat,$idx) 513 mov %r11b,($dat,$ido) 514 add \$1,$ido#b 515 jnc .Lc2ndloop 516 movl \$-1,256($dat) 517 518.align 16 519.Lexit_key: 520 xor %eax,%eax 521 mov %eax,-8($dat) 522 mov %eax,-4($dat) 523 ret 524.cfi_endproc 525.size RC4_set_key,.-RC4_set_key 526 527.globl RC4_options 528.type RC4_options,\@abi-omnipotent 529.align 16 530RC4_options: 531.cfi_startproc 532 lea .Lopts(%rip),%rax 533 mov OPENSSL_ia32cap_P(%rip),%edx 534 bt \$20,%edx 535 jc .L8xchar 536 bt \$30,%edx 537 jnc .Ldone 538 add \$25,%rax 539 ret 540.L8xchar: 541 add \$12,%rax 542.Ldone: 543 ret 544.cfi_endproc 545.align 64 546.Lopts: 547.asciz "rc4(8x,int)" 548.asciz "rc4(8x,char)" 549.asciz "rc4(16x,int)" 550.asciz "RC4 for x86_64, CRYPTOGAMS by <appro\@openssl.org>" 551.align 64 552.size RC4_options,.-RC4_options 553___ 554 555# EXCEPTION_DISPOSITION handler (EXCEPTION_RECORD *rec,ULONG64 frame, 556# CONTEXT *context,DISPATCHER_CONTEXT *disp) 557if ($win64) { 558$rec="%rcx"; 559$frame="%rdx"; 560$context="%r8"; 561$disp="%r9"; 562 563$code.=<<___; 564.extern __imp_RtlVirtualUnwind 565.type stream_se_handler,\@abi-omnipotent 566.align 16 567stream_se_handler: 568 push %rsi 569 push %rdi 570 push %rbx 571 push %rbp 572 push %r12 573 push %r13 574 push %r14 575 push %r15 576 pushfq 577 sub \$64,%rsp 578 579 mov 120($context),%rax # pull context->Rax 580 mov 248($context),%rbx # pull context->Rip 581 582 lea .Lprologue(%rip),%r10 583 cmp %r10,%rbx # context->Rip<prologue label 584 jb .Lin_prologue 585 586 mov 152($context),%rax # pull context->Rsp 587 588 lea .Lepilogue(%rip),%r10 589 cmp %r10,%rbx # context->Rip>=epilogue label 590 jae .Lin_prologue 591 592 lea 24(%rax),%rax 593 594 mov -8(%rax),%rbx 595 mov -16(%rax),%r12 596 mov -24(%rax),%r13 597 mov %rbx,144($context) # restore context->Rbx 598 mov %r12,216($context) # restore context->R12 599 mov %r13,224($context) # restore context->R13 600 601.Lin_prologue: 602 mov 8(%rax),%rdi 603 mov 16(%rax),%rsi 604 mov %rax,152($context) # restore context->Rsp 605 mov %rsi,168($context) # restore context->Rsi 606 mov %rdi,176($context) # restore context->Rdi 607 608 jmp .Lcommon_seh_exit 609.size stream_se_handler,.-stream_se_handler 610 611.type key_se_handler,\@abi-omnipotent 612.align 16 613key_se_handler: 614 push %rsi 615 push %rdi 616 push %rbx 617 push %rbp 618 push %r12 619 push %r13 620 push %r14 621 push %r15 622 pushfq 623 sub \$64,%rsp 624 625 mov 152($context),%rax # pull context->Rsp 626 mov 8(%rax),%rdi 627 mov 16(%rax),%rsi 628 mov %rsi,168($context) # restore context->Rsi 629 mov %rdi,176($context) # restore context->Rdi 630 631.Lcommon_seh_exit: 632 633 mov 40($disp),%rdi # disp->ContextRecord 634 mov $context,%rsi # context 635 mov \$154,%ecx # sizeof(CONTEXT) 636 .long 0xa548f3fc # cld; rep movsq 637 638 mov $disp,%rsi 639 xor %rcx,%rcx # arg1, UNW_FLAG_NHANDLER 640 mov 8(%rsi),%rdx # arg2, disp->ImageBase 641 mov 0(%rsi),%r8 # arg3, disp->ControlPc 642 mov 16(%rsi),%r9 # arg4, disp->FunctionEntry 643 mov 40(%rsi),%r10 # disp->ContextRecord 644 lea 56(%rsi),%r11 # &disp->HandlerData 645 lea 24(%rsi),%r12 # &disp->EstablisherFrame 646 mov %r10,32(%rsp) # arg5 647 mov %r11,40(%rsp) # arg6 648 mov %r12,48(%rsp) # arg7 649 mov %rcx,56(%rsp) # arg8, (NULL) 650 call *__imp_RtlVirtualUnwind(%rip) 651 652 mov \$1,%eax # ExceptionContinueSearch 653 add \$64,%rsp 654 popfq 655 pop %r15 656 pop %r14 657 pop %r13 658 pop %r12 659 pop %rbp 660 pop %rbx 661 pop %rdi 662 pop %rsi 663 ret 664.size key_se_handler,.-key_se_handler 665 666.section .pdata 667.align 4 668 .rva .LSEH_begin_RC4 669 .rva .LSEH_end_RC4 670 .rva .LSEH_info_RC4 671 672 .rva .LSEH_begin_RC4_set_key 673 .rva .LSEH_end_RC4_set_key 674 .rva .LSEH_info_RC4_set_key 675 676.section .xdata 677.align 8 678.LSEH_info_RC4: 679 .byte 9,0,0,0 680 .rva stream_se_handler 681.LSEH_info_RC4_set_key: 682 .byte 9,0,0,0 683 .rva key_se_handler 684___ 685} 686 687sub reg_part { 688my ($reg,$conv)=@_; 689 if ($reg =~ /%r[0-9]+/) { $reg .= $conv; } 690 elsif ($conv eq "b") { $reg =~ s/%[er]([^x]+)x?/%$1l/; } 691 elsif ($conv eq "w") { $reg =~ s/%[er](.+)/%$1/; } 692 elsif ($conv eq "d") { $reg =~ s/%[er](.+)/%e$1/; } 693 return $reg; 694} 695 696$code =~ s/(%[a-z0-9]+)#([bwd])/reg_part($1,$2)/gem; 697$code =~ s/\`([^\`]*)\`/eval $1/gem; 698 699print $code; 700 701close STDOUT or die "error closing STDOUT: $!"; 702