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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Drockchip-pcie-host.txt4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
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Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
18 - brcm,bcm7278-pcie # Broadcom 7278 Arm
19 - brcm,bcm7216-pcie # Broadcom 7216 Arm
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/kernel/linux/linux-5.10/drivers/pci/controller/dwc/
Dpcie-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
33 #include "pcie-designware.h"
35 #include <soc/tegra/bpmp-abi.h>
322 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
327 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
342 * NOTE:- Since this scenario is uncommon and link as such is not in apply_bad_link_workaround()
344 * transitioning to Gen-2 speed in apply_bad_link_workaround()
346 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in apply_bad_link_workaround()
350 if (pcie->init_link_width > current_link_width) { in apply_bad_link_workaround()
351 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); in apply_bad_link_workaround()
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/kernel/linux/linux-5.10/include/uapi/linux/
Dpci_regs.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
123 /* 0x35-0x3b are reserved */
129 /* Header type 1 (PCI-to-PCI bridges) */
157 /* 0x35-0x3b is reserved */
159 /* 0x3c-0x3d are same as for htype 0 */
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/kernel/linux/linux-5.10/drivers/pci/controller/
Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
34 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
175 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
176 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
177 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
267 int nr; /* No. of MSI available, depends on chip */
294 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
302 return (log2_in - 12) + 0x1c; in brcm_pcie_encode_ibar_size()
305 return log2_in - 15; in brcm_pcie_encode_ibar_size()
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Dpcie-rockchip-host.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
40 #include "pcie-rockchip.h"
79 if (pci_is_root_bus(bus) || pci_is_root_bus(bus->parent)) in rockchip_pcie_valid_device()
90 if (rockchip->legacy_phy) in rockchip_pcie_lane_map()
91 return GENMASK(MAX_LANE_NUM - 1, 0); in rockchip_pcie_lane_map()
96 /* The link may be using a reverse-indexed mapping. */ in rockchip_pcie_lane_map()
108 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where; in rockchip_pcie_rd_own_conf()
135 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset; in rockchip_pcie_wr_own_conf()
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Dpcie-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
72 /* PCIe V2 per-port registers */
125 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
143 * struct mtk_pcie_soc - differentiate between host generations
161 * struct mtk_pcie_port - PCIe port information
205 * struct mtk_pcie - PCIe host information
208 * @free_ck: free-run reference clock
209 * @mem: non-prefetchable memory resource
211 * @soc: pointer to SoC-dependent operations
224 struct device *dev = pcie->dev; in mtk_pcie_subsys_powerdown()
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/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath9k/
Dar9002_hw.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
29 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271); in ar9002_hw_init_mode_regs()
30 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271); in ar9002_hw_init_mode_regs()
31 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg); in ar9002_hw_init_mode_regs()
35 INIT_INI_ARRAY(&ah->iniPcieSerdes, in ar9002_hw_init_mode_regs()
39 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1); in ar9002_hw_init_mode_regs()
40 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1); in ar9002_hw_init_mode_regs()
42 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2); in ar9002_hw_init_mode_regs()
43 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2); in ar9002_hw_init_mode_regs()
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Dar9003_hw.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
45 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], in ar9003_hw_init_mode_regs()
47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], in ar9003_hw_init_mode_regs()
51 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], in ar9003_hw_init_mode_regs()
53 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], in ar9003_hw_init_mode_regs()
57 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], in ar9003_hw_init_mode_regs()
61 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], in ar9003_hw_init_mode_regs()
63 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], in ar9003_hw_init_mode_regs()
67 INIT_INI_ARRAY(&ah->iniModesRxGain, in ar9003_hw_init_mode_regs()
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/kernel/linux/linux-5.10/arch/sh/drivers/pci/
Dpcie-sh7786.c1 // SPDX-License-Identifier: GPL-2.0
3 * Low-Level PCI Express Support for the SH7786
5 * Copyright (C) 2009 - 2011 Paul Mundt
15 #include <linux/dma-mapping.h>
21 #include "pcie-sh7786.h"
47 .end = 0xfd000000 + SZ_8M - 1,
52 .end = 0xc0000000 + SZ_512M - 1,
57 .end = 0x10000000 + SZ_64M - 1,
62 .end = 0xfe100000 + SZ_1M - 1,
71 .end = 0xfd800000 + SZ_8M - 1,
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/kernel/linux/linux-5.10/drivers/net/wireless/intel/iwlegacy/
Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
19 #include <linux/dma-mapping.h>
39 return -ETIMEDOUT; in _il_poll_bit()
48 spin_lock_irqsave(&p->reg_lock, reg_flags); in il_set_bit()
50 spin_unlock_irqrestore(&p->reg_lock, reg_flags); in il_set_bit()
59 spin_lock_irqsave(&p->reg_lock, reg_flags); in il_clear_bit()
61 spin_unlock_irqrestore(&p->reg_lock, reg_flags); in il_clear_bit()
79 * to/from host DRAM when sleeping/waking for power-saving. in _il_grab_nic_access()
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/kernel/linux/linux-5.10/drivers/net/ethernet/atheros/atl1c/
Datl1c_main.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
14 * atl1c_pci_tbl - PCI Device ID Table
35 MODULE_AUTHOR("Qualcomm Atheros Inc., <nic-devel@qualcomm.com>");
65 if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) { in atl1c_pcie_patch()
74 /* aspm/PCIE setting only for l2cb 1.0 */ in atl1c_pcie_patch()
75 if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10) { in atl1c_pcie_patch()
88 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d) { in atl1c_pcie_patch()
98 /* FIXME: no need any more ? */
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/kernel/linux/linux-5.10/drivers/net/ethernet/atheros/alx/
Dhw.c28 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
58 return -ETIMEDOUT; in alx_wait_mdio_idle()
70 clk_sel = hw->link_speed != SPEED_UNKNOWN ? in alx_read_phy_core()
104 clk_sel = hw->link_speed != SPEED_UNKNOWN ? in alx_write_phy_core()
175 spin_lock(&hw->mdio_lock); in alx_read_phy_reg()
177 spin_unlock(&hw->mdio_lock); in alx_read_phy_reg()
186 spin_lock(&hw->mdio_lock); in alx_write_phy_reg()
188 spin_unlock(&hw->mdio_lock); in alx_write_phy_reg()
197 spin_lock(&hw->mdio_lock); in alx_read_phy_ext()
199 spin_unlock(&hw->mdio_lock); in alx_read_phy_ext()
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/kernel/linux/linux-5.10/drivers/net/ethernet/realtek/
Dr8169_main.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
26 #include <linux/dma-mapping.h>
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
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/kernel/linux/linux-5.10/drivers/net/ethernet/intel/e1000e/
Dnetdev.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
34 static int debug = -1;
108 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
123 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) in __ew32_prepare()
129 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) in __ew32()
132 writel(val, hw->hw_addr + reg); in __ew32()
136 * e1000_regdump - register printout routine
146 switch (reginfo->ofs) { in e1000_regdump()
160 pr_info("%-15s %08x\n", in e1000_regdump()
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/kernel/linux/linux-5.10/drivers/pci/
Dquirks.c1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
5 * should be handled in arch-specific code.
63 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
64 f->class == (u32) PCI_ANY_ID) && in pci_do_fixups()
65 (f->vendor == dev->vendor || in pci_do_fixups()
66 f->vendor == (u16) PCI_ANY_ID) && in pci_do_fixups()
67 (f->device == dev->device || in pci_do_fixups()
68 f->device == (u16) PCI_ANY_ID)) { in pci_do_fixups()
71 hook = offset_to_ptr(&f->hook_offset); in pci_do_fixups()
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/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
Dhw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
48 rtlpci->reg_bcn_ctrl_val |= set_bits; in _rtl92de_set_bcn_ctrl_reg()
49 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; in _rtl92de_set_bcn_ctrl_reg()
50 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); in _rtl92de_set_bcn_ctrl_reg()
99 *((u32 *) (val)) = rtlpci->receive_config; in rtl92de_get_hw_reg()
102 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; in rtl92de_get_hw_reg()
108 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, in rtl92de_get_hw_reg()
123 *((bool *) (val)) = ppsc->fw_current_inpsmode; in rtl92de_get_hw_reg()
136 *((bool *)(val)) = rtlpriv->dm.interrupt_migration; in rtl92de_get_hw_reg()
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/rockchip/
Drk3399.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
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