| /kernel/linux/linux-5.10/drivers/soc/fsl/qe/ |
| D | ucc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * QE UCC API Set - UCC specific routines implementations.
33 if (ucc_num > UCC_MAX_NUM - 1) in ucc_set_qe_mux_mii_mng()
34 return -EINVAL; in ucc_set_qe_mux_mii_mng()
37 qe_clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG, in ucc_set_qe_mux_mii_mng()
50 * 'ucc_num' is the UCC number, from 0 - 7.
62 case 0: guemr = &qe_immr->ucc1.slow.guemr; in ucc_set_type()
64 case 1: guemr = &qe_immr->ucc2.slow.guemr; in ucc_set_type()
66 case 2: guemr = &qe_immr->ucc3.slow.guemr; in ucc_set_type()
68 case 3: guemr = &qe_immr->ucc4.slow.guemr; in ucc_set_type()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | micrel.txt | 7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
9 Configure the LED mode with single value. The list of PHYs and the
20 See the respective PHY datasheet for the mode values.
22 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
23 bit selects 25 MHz mode
25 Setting the RMII Reference Clock Select bit enables 25 MHz rather
26 than 50 MHz clock mode.
29 non-standard, inverted function of this configuration bit.
30 Specifically, a clock reference ("rmii-ref" below) is always needed to
31 actually select a mode.
[all …]
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| D | amlogic,meson-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Neil Armstrong <narmstrong@baylibre.com>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
[all …]
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| /kernel/linux/linux-5.10/Documentation/timers/ |
| D | no_hz.rst | 2 NO_HZ: Reducing Scheduling-Clock Ticks
7 reduce the number of scheduling-clock interrupts, thereby improving energy
9 some types of computationally intensive high-performance computing (HPC)
10 applications and for real-time applications.
12 There are three main ways of managing scheduling-clock interrupts
13 (also known as "scheduling-clock ticks" or simply "ticks"):
15 1. Never omit scheduling-clock ticks (CONFIG_HZ_PERIODIC=y or
16 CONFIG_NO_HZ=n for older kernels). You normally will -not-
19 2. Omit scheduling-clock ticks on idle CPUs (CONFIG_NO_HZ_IDLE=y or
23 3. Omit scheduling-clock ticks on CPUs that are either idle or that
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/gma500/ |
| D | psb_intel_display.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
46 /* The single-channel range is 25-112Mhz, and dual-channel
47 * is 80-224Mhz. Prefer single channel as much as possible.
66 static void psb_intel_clock(int refclk, struct gma_clock_t *clock) in psb_intel_clock() argument
68 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in psb_intel_clock()
69 clock->p = clock->p1 * clock->p2; in psb_intel_clock()
70 clock->vco = refclk * clock->m / (clock->n + 2); in psb_intel_clock()
71 clock->dot = clock->vco / clock->p; in psb_intel_clock()
76 * or -1 if the panel fitter is not present or not in use
[all …]
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| D | cdv_intel_display.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
56 /* The single-channel range is 25-112Mhz, and dual-channel
57 * is 80-224Mhz. Prefer single channel as much as possible.
117 ret__ = -ETIMEDOUT; \
196 * mode set.
208 * DPLL reference clock is on in the DPLL control register, but before
213 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select) in cdv_dpll_set_clock_cdv() argument
216 int pipe = gma_crtc->pipe; in cdv_dpll_set_clock_cdv()
243 * refclka mean use clock from same PLL in cdv_dpll_set_clock_cdv()
[all …]
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| /kernel/linux/linux-5.10/sound/pci/echoaudio/ |
| D | layla24_dsp.c | 3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA.
25 Translation from C++ and adaptation for use in ALSA-Driver
32 static int set_input_clock(struct echoaudio *chip, u16 clock);
34 static int set_digital_mode(struct echoaudio *chip, u8 mode);
44 return -ENODEV; in init_hw()
47 dev_err(chip->card->dev, in init_hw()
48 "init_hw - could not initialize DSP comm page\n"); in init_hw()
52 chip->device_id = device_id; in init_hw()
[all …]
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| D | mona_dsp.c | 3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
33 static int set_input_clock(struct echoaudio *chip, u16 clock);
35 static int set_digital_mode(struct echoaudio *chip, u8 mode);
45 return -ENODEV; in init_hw()
48 dev_err(chip->card->dev, in init_hw()
49 "init_hw - could not initialize DSP comm page\n"); in init_hw()
53 chip->device_id = device_id; in init_hw()
[all …]
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| D | echoaudio_3g.c | 3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
41 return -EIO; in check_asic_status()
43 chip->comm_page->ext_box_status = cpu_to_le32(E3G_ASIC_NOT_LOADED); in check_asic_status()
44 chip->asic_loaded = false; in check_asic_status()
49 chip->dsp_code = NULL; in check_asic_status()
50 return -EIO; in check_asic_status()
53 box_status = le32_to_cpu(chip->comm_page->ext_box_status); in check_asic_status()
[all …]
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| D | gina24_dsp.c | 3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
33 static int set_input_clock(struct echoaudio *chip, u16 clock);
35 static int set_digital_mode(struct echoaudio *chip, u8 mode);
45 return -ENODEV; in init_hw()
48 dev_err(chip->card->dev, in init_hw()
49 "init_hw - could not initialize DSP comm page\n"); in init_hw()
53 chip->device_id = device_id; in init_hw()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | exynos-dw-mshc.txt | 7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
26 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
27 unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | atombios_crtc.c | 2 * Copyright 2007-8 Advanced Micro Devices, Inc.
32 #include "atom-bits.h"
40 struct drm_display_mode *mode, in amdgpu_atombios_crtc_overscan_setup() argument
43 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_overscan_setup()
52 args.ucCRTC = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_overscan_setup()
54 switch (amdgpu_crtc->rmx_type) { in amdgpu_atombios_crtc_overscan_setup()
56 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
57 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
58 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
59 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | tegra124-nyan-blaze-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 clock@60006000 {
4 emc-timings-1 {
5 nvidia,ram-code = <1>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
[all …]
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| D | tegra124-apalis-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
8 clock@60006000 {
9 emc-timings-1 {
10 nvidia,ram-code = <1>;
12 timing-12750000 {
13 clock-frequency = <12750000>;
14 nvidia,parent-clock-frequency = <408000000>;
16 clock-names = "emc-parent";
18 timing-20400000 {
[all …]
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| D | tegra124-jetson-tk1-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 clock@60006000 {
4 emc-timings-3 {
5 nvidia,ram-code = <3>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/ |
| D | omap-usb-host.txt | 5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
16 from 1 to 3. If the port mode is not specified, that port is treated
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
21 "ohci-phy-6pin-datse0",
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/mgag200/ |
| D | mgag200_mode.c | 1 // SPDX-License-Identifier: GPL-2.0-only
35 struct drm_device *dev = crtc->dev; in mga_crtc_load_lut()
41 if (!crtc->enabled) in mga_crtc_load_lut()
44 if (!mdev->display_pipe.plane.state) in mga_crtc_load_lut()
47 fb = mdev->display_pipe.plane.state->fb; in mga_crtc_load_lut()
49 r_ptr = crtc->gamma_store; in mga_crtc_load_lut()
50 g_ptr = r_ptr + crtc->gamma_size; in mga_crtc_load_lut()
51 b_ptr = g_ptr + crtc->gamma_size; in mga_crtc_load_lut()
55 if (fb && fb->format->cpp[0] * 8 == 16) { in mga_crtc_load_lut()
56 int inc = (fb->format->depth == 15) ? 8 : 4; in mga_crtc_load_lut()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/zynqmp/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Xilinx
9 #include <linux/clk-provider.h>
11 #include "clk-zynqmp.h"
14 * struct zynqmp_pll - PLL clock
15 * @hw: Handle between common and hardware-specific interfaces
16 * @clk_id: PLL clock ID
43 * zynqmp_pll_get_mode() - Get mode of PLL
44 * @hw: Handle between common and hardware-specific interfaces
46 * Return: Mode of PLL
[all …]
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| /kernel/linux/linux-5.10/drivers/video/fbdev/ |
| D | valkyriefb.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * Vmode-switching changes and vmode 15/17 modifications created 29 August
13 * Ported to 68k Macintosh by David Huggins-Daines <dhd@debian.org>
20 * pmc-valkyrie.h: Console support for PowerMac "control" display adaptor.
23 * pmc-valkyrie.c: Console support for PowerMac "control" display adaptor.
28 * pmc-control.h: Console support for PowerMac "control" display adaptor.
31 * pmc-control.c: Console support for PowerMac "control" display adaptor.
39 /* Valkyrie registers are word-aligned on m68k */
65 struct vpreg mode; member
78 * Dot clock rate is
[all …]
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| /kernel/linux/linux-5.10/Documentation/ABI/testing/ |
| D | sysfs-bus-iio-counter-104-quad-8 | 7 Contact: linux-iio@vger.kernel.org
16 Contact: linux-iio@vger.kernel.org
20 Count mode for channel Y. Four count modes are available:
21 normal, range limit, non-recycle, and modulo-n. The preset value
22 for channel Y is used by the count mode where required.
36 Non-recycle:
37 Counter is disabled whenever a 24-bit count overflow or
38 underflow takes place. The counter is re-enabled when a
42 Modulo-N:
52 Contact: linux-iio@vger.kernel.org
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | silabs,si5341.txt | 2 i2c clock generator.
6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
12 The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
15 The internal structure of the clock generators can be found in [2].
20 The driver can be used in "as is" mode, reading the current settings from the
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
27 The driver currently only supports XTAL input mode, and does not support any
34 - compatible: shall be one of the following:
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/frequency/ |
| D | adf4350.txt | 4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
10 ADF435x Reference Clock (CLKIN).
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
[all …]
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| /kernel/linux/linux-5.10/Documentation/networking/ |
| D | generic-hdlc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 - Normal (routed) and Ethernet-bridged (Ethernet device emulation)
16 - ARP support (no InARP support in the kernel - there is an
17 experimental InARP user-space daemon available on:
20 2. raw HDLC - either IP (IPv4) interface or Ethernet device emulation
25 Generic HDLC is a protocol driver only - it needs a low-level driver
28 Ethernet device emulation (using HDLC or Frame-Relay PVC) is compatible
40 gcc -O2 -Wall -o sethdlc sethdlc.c
44 Use sethdlc to set physical interface, clock rate, HDLC mode used,
48 sethdlc hdlc0 clock int rate 128000
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| /kernel/linux/linux-5.10/sound/firewire/digi00x/ |
| D | digi00x-proc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * digi00x-proc.c - a part of driver for Digidesign Digi 002/003 family
5 * Copyright (c) 2014-2015 Takashi Sakamoto
11 enum snd_dg00x_optical_mode *mode) in get_optical_iface_mode() argument
16 err = snd_fw_transaction(dg00x->unit, TCODE_READ_QUADLET_REQUEST, in get_optical_iface_mode()
20 *mode = be32_to_cpu(data) & 0x01; in get_optical_iface_mode()
32 [SND_DG00X_CLOCK_WORD] = "word clock", in proc_read_clock()
38 struct snd_dg00x *dg00x = entry->private_data; in proc_read_clock()
39 enum snd_dg00x_optical_mode mode; in proc_read_clock() local
41 enum snd_dg00x_clock clock; in proc_read_clock() local
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra20-pmc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra20-pmc
18 - nvidia,tegra30-pmc
19 - nvidia,tegra114-pmc
[all …]
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