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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dti,dp83822.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Dan Murphy <dmurphy@ti.com>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
24 - $ref: "ethernet-phy.yaml#"
30 ti,link-loss-low:
33 DP83822 PHY in Fiber mode only.
[all …]
Dmicrel.txt7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
9 Configure the LED mode with single value. The list of PHYs and the
20 See the respective PHY datasheet for the mode values.
22 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
23 bit selects 25 MHz mode
26 than 50 MHz clock mode.
29 non-standard, inverted function of this configuration bit.
30 Specifically, a clock reference ("rmii-ref" below) is always needed to
31 actually select a mode.
33 - clocks, clock-names: contains clocks according to the common clock bindings.
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Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-phy.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
22 SGMII The DP83869HM supports Media Conversion in Managed mode. In this mode,
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Dkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
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/kernel/linux/linux-5.10/drivers/net/phy/
Dmarvell.c1 // SPDX-License-Identifier: GPL-2.0+
317 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in marvell_config_intr()
369 err = marvell_set_polarity(phydev, phydev->mdix_ctrl); in marvell_config_aneg()
384 if (phydev->autoneg != AUTONEG_ENABLE || changed) { in marvell_config_aneg()
434 * marvell,reg-init property stored in the of_node for the phydev.
436 * marvell,reg-init = <reg-page reg mask value>,...;
438 * There may be one or more sets of <reg-page reg mask value>:
440 * reg-page: which register bank to use.
442 * mask: if non-zero, ANDed with existing register value.
451 if (!phydev->mdio.dev.of_node) in marvell_of_reg_init()
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Dlxt.c1 // SPDX-License-Identifier: GPL-2.0+
42 /* ------------------------------------------------------------------------- */
78 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in lxt970_config_intr()
102 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in lxt971_config_intr()
132 } while (status >= 0 && retry-- && status == control); in lxt973a2_update_link()
138 phydev->link = 0; in lxt973a2_update_link()
140 phydev->link = 1; in lxt973a2_update_link()
156 if (AUTONEG_ENABLE == phydev->autoneg) { in lxt973a2_read_status()
173 } while (lpa == adv && retry--); in lxt973a2_read_status()
175 mii_lpa_to_linkmode_lpa_t(phydev->lp_advertising, lpa); in lxt973a2_read_status()
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Ddp83822.c1 // SPDX-License-Identifier: GPL-2.0
101 /* SOR1 mode */
140 struct net_device *ndev = phydev->attached_dev; in dp83822_set_wol()
144 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { in dp83822_set_wol()
145 mac = (const u8 *)ndev->dev_addr; in dp83822_set_wol()
148 return -EINVAL; in dp83822_set_wol()
162 if (wol->wolopts & WAKE_MAGIC) in dp83822_set_wol()
167 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83822_set_wol()
170 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83822_set_wol()
173 (wol->sopass[3] << 8) | wol->sopass[2]); in dp83822_set_wol()
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Dmarvell10g.c1 // SPDX-License-Identifier: GPL-2.0+
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
18 * XAUI PHYXS -- <appropriate PCS as above>
20 * and no switching of the host interface mode occurs.
22 * If both the fiber and copper ports are connected, the first to gain
72 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
76 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
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Dmicrel.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2010-2013 Micrel, Inc.
31 /* Operation Mode Strap Override */
58 /* bitmap of PHY register to set interrupt mode */
160 const struct kszphy_type *type = phydev->drv->driver_data; in kszphy_config_intr()
164 if (type && type->interrupt_level_mask) in kszphy_config_intr()
165 mask = type->interrupt_level_mask; in kszphy_config_intr()
177 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in kszphy_config_intr()
213 return -EINVAL; in kszphy_setup_led()
227 phydev_err(phydev, "failed to set led mode\n"); in kszphy_setup_led()
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Dsfp.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/mdio/mdio-i2c.h>
147 "mod-def0",
149 "tx-fault",
150 "tx-disable",
151 "rate-select0",
162 /* t_start_up (SFF-8431) or t_init (SFF-8472) is the time required for a
163 * non-cooled module to initialise its laser safety circuitry. We wait
195 * The SFF-8472 specifies t_serial ("Time from power on until module is
206 * 0x56 (which with mdio-i2c, translates to a PHY address of 22).
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/kernel/linux/linux-5.10/drivers/net/ethernet/intel/e1000/
De1000_param.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
12 #define OPTION_UNSET -1
30 * Valid Range: 80-256 for 82542 and 82543 gigabit ethernet controllers
31 * Valid Range: 80-4096 for 82544 and newer
39 * Valid Range: 80-256 for 82542 and 82543 gigabit ethernet controllers
40 * Valid Range: 80-4096 for 82544 and newer
49 * - 0 - auto-negotiate at all supported speeds
50 * - 10 - only link at 10 Mbps
51 * - 100 - only link at 100 Mbps
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/kernel/linux/linux-5.10/drivers/net/hippi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 1600Mbit/sec dual-simplex switched or point-to-point network. HIPPI
12 can run over copper (25m) or fiber (300m on multi-mode or 10km on
13 single-mode). HIPPI networks are commonly used for clusters and to
/kernel/linux/linux-5.10/drivers/net/
Dsungem_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * (c) 2002-2007, Benjamin Herrenscmidt (benh@kernel.crashing.org)
10 * - Add support for PHYs that provide an IRQ line
11 * - Eventually moved the entire polling state machine in
14 * - On LXT971 & BCM5201, Apple uses some chip specific regs
17 * - Apple has some additional power management code for some
53 return phy->mdio_read(phy->dev, id, reg); in __sungem_phy_read()
58 phy->mdio_write(phy->dev, id, reg, val); in __sungem_phy_write()
63 return phy->mdio_read(phy->dev, phy->mii_id, reg); in sungem_phy_read()
68 phy->mdio_write(phy->dev, phy->mii_id, reg, val); in sungem_phy_write()
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/kernel/linux/linux-5.10/drivers/net/ethernet/intel/e1000e/
Dmac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
7 * e1000e_get_bus_info_pcie - Get PCIe bus information
16 struct e1000_mac_info *mac = &hw->mac; in e1000e_get_bus_info_pcie()
17 struct e1000_bus_info *bus = &hw->bus; in e1000e_get_bus_info_pcie()
18 struct e1000_adapter *adapter = hw->adapter; in e1000e_get_bus_info_pcie()
21 cap_offset = adapter->pdev->pcie_cap; in e1000e_get_bus_info_pcie()
23 bus->width = e1000_bus_width_unknown; in e1000e_get_bus_info_pcie()
25 pci_read_config_word(adapter->pdev, in e1000e_get_bus_info_pcie()
28 bus->width = (enum e1000_bus_width)((pcie_link_status & in e1000e_get_bus_info_pcie()
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/kernel/linux/linux-5.10/Documentation/networking/device_drivers/ethernet/intel/
De1000e.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2008-2018 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Additional Configurations
16 - Support
48 ---------------------
49 :Valid Range: 0,1,3,4,100-100000
82 - 0: Off
86 - 1: Dynamic mode
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De1000.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999 - 2013 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Speed and Duplex Configuration
16 - Additional Configurations
17 - Support
50 -------
54 :Valid Range: 0x01-0x0F, 0x20-0x2F
57 This parameter is a bit-mask that specifies the speed and duplex settings
[all …]
Di40e.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Intel(R) Ethernet Flow Director
16 - Additional Configurations
17 - Known Issues
18 - Support
47 ----------------------
49 …intel.com/content/dam/www/public/us/en/documents/release-notes/xl710-ethernet-controller-feature-m…
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/kernel/linux/linux-5.10/drivers/net/ethernet/marvell/
Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
39 PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
[all …]
Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
264 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
265 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
266 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
268 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
[all …]
/kernel/linux/linux-5.10/drivers/net/dsa/microchip/
Dksz_common.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 2017-2019 Microchip Technology Inc.
36 u32 fiber:1; /* port is fiber */ member
158 void ksz_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
184 int ret = regmap_read(dev->regmap[0], reg, &value); in ksz_read8()
193 int ret = regmap_read(dev->regmap[1], reg, &value); in ksz_read16()
202 int ret = regmap_read(dev->regmap[2], reg, &value); in ksz_read32()
213 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); in ksz_read64()
222 return regmap_write(dev->regmap[0], reg, value); in ksz_write8()
227 return regmap_write(dev->regmap[1], reg, value); in ksz_write16()
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Dksz8795.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/platform_data/microchip-ksz.h>
67 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); in ksz_cfg()
73 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), in ksz_port_cfg()
131 mutex_lock(&dev->alu_mutex); in ksz8795_r_mib_cnt()
137 for (loop = 2; loop > 0; loop--) { in ksz8795_r_mib_cnt()
148 mutex_unlock(&dev->alu_mutex); in ksz8795_r_mib_cnt()
159 addr -= SWITCH_COUNTER_NUM; in ksz8795_r_mib_pkt()
160 ctrl_addr = (KS_MIB_TOTAL_RX_1 - KS_MIB_TOTAL_RX_0) * port; in ksz8795_r_mib_pkt()
164 mutex_lock(&dev->alu_mutex); in ksz8795_r_mib_pkt()
[all …]
/kernel/linux/linux-5.10/drivers/atm/
Dfore200e.h1 /* SPDX-License-Identifier: GPL-2.0 */
52 #define RSD_REQUIRED (((MAX_PDU_SIZE - SMALL_BUFFER_SIZE + LARGE_BUFFER_SIZE) / LARGE_BUFFER_SIZE)…
56 /* RSD_REQUIRED receive segment descriptors are enough to describe a max-sized PDU,
61 #define RSD_EXTENSION ((RSD_REQUIRED - RSD_FIXED) + 1)
65 #define FORE200E_DEV(d) ((struct fore200e*)((d)->dev_data))
66 #define FORE200E_VCC(d) ((struct fore200e_vcc*)((d)->dev_data))
256 OPCODE_SET_OC3, /* set OC-3 registers */
257 OPCODE_GET_OC3, /* get OC-3 registers */
318 /* OC-3 registers */
321 u32 reg[ 128 ]; /* see the PMC Sierra PC5346 S/UNI-155-Lite
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/kernel/linux/linux-5.10/drivers/media/i2c/m5mols/
Dm5mols_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Register map for M-5MOLS 8M Pixel camera sensor with ISP
27 * The category means set including relevant command of M-5MOLS.
42 * Category 0 - SYSTEM mode
44 * The SYSTEM mode in the M-5MOLS means area available to handle with the whole
45 * & all-round system of sensor. It deals with version/interrupt/setting mode &
46 * even sensor's status. Especially, the M-5MOLS sensor with ISP varies by
62 #define REG_SYSINIT 0x00 /* SYSTEM mode */
63 #define REG_PARAMETER 0x01 /* PARAMETER mode */
64 #define REG_MONITOR 0x02 /* MONITOR mode */
[all …]
/kernel/linux/linux-5.10/drivers/scsi/bfa/
Dbfa_defs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
4 * Copyright (c) 2014- QLogic Corporation.
8 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
34 BFA_MFG_TYPE_LIGHTNING_P0 = 902, /* Lightning mezz card - old */
102 * All numerical fields are in big-endian format.
125 BFA_STATUS_ETIMER = 5, /* Timer expired - Retry, if persists,
129 BFA_STATUS_SFP_UNSUPP = 10, /* Unsupported SFP - Replace SFP */
132 BFA_STATUS_DEVBUSY = 13, /* Device busy - Retry operation */
148 BFA_STATUS_IOC_FAILURE = 56, /* IOC failure - Retry, if persists
[all …]
/kernel/linux/linux-5.10/drivers/net/fddi/
Ddefza.h1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* FDDI network adapter driver for DEC FDDIcontroller 700/700-C devices.
36 #define FZA_RESET_CLR 0x0000 /* run self-test and return to work */
43 #define FZA_EVENT_NXM_ERR 0x0080 /* non-existent memory access error;
45 * unsupported partial-word accesses
93 #define FZA_HALT_HOST 0x01 /* host-directed HALT */
95 #define FZA_HALT_NXM 0x03 /* adapter non-existent memory ref. */
102 #define FZA_TEST_FATAL 0x00 /* self-test catastrophic failure */
106 #define FZA_TEST_SRAM_STUCK1 0x04 /* SRAM stuck-at range 1 */
107 #define FZA_TEST_SRAM_STUCK2 0x05 /* SRAM stuck-at range 2 */
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