1// SPDX-License-Identifier: GPL-2.0 2#include "bcm283x.dtsi" 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/soc/bcm2835-pm.h> 6 7/ { 8 compatible = "brcm,bcm2711"; 9 10 #address-cells = <2>; 11 #size-cells = <1>; 12 13 interrupt-parent = <&gicv2>; 14 15 vc4: gpu { 16 compatible = "brcm,bcm2711-vc5"; 17 status = "disabled"; 18 }; 19 20 clk_27MHz: clk-27M { 21 #clock-cells = <0>; 22 compatible = "fixed-clock"; 23 clock-frequency = <27000000>; 24 clock-output-names = "27MHz-clock"; 25 }; 26 27 clk_108MHz: clk-108M { 28 #clock-cells = <0>; 29 compatible = "fixed-clock"; 30 clock-frequency = <108000000>; 31 clock-output-names = "108MHz-clock"; 32 }; 33 34 soc { 35 /* 36 * Defined ranges: 37 * Common BCM283x peripherals 38 * BCM2711-specific peripherals 39 * ARM-local peripherals 40 */ 41 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>, 42 <0x7c000000 0x0 0xfc000000 0x02000000>, 43 <0x40000000 0x0 0xff800000 0x00800000>; 44 /* Emulate a contiguous 30-bit address range for DMA */ 45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>; 46 47 /* 48 * This node is the provider for the enable-method for 49 * bringing up secondary cores. 50 */ 51 local_intc: local_intc@40000000 { 52 compatible = "brcm,bcm2836-l1-intc"; 53 reg = <0x40000000 0x100>; 54 }; 55 56 gicv2: interrupt-controller@40041000 { 57 interrupt-controller; 58 #interrupt-cells = <3>; 59 compatible = "arm,gic-400"; 60 reg = <0x40041000 0x1000>, 61 <0x40042000 0x2000>, 62 <0x40044000 0x2000>, 63 <0x40046000 0x2000>; 64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 65 IRQ_TYPE_LEVEL_HIGH)>; 66 }; 67 68 avs_monitor: avs-monitor@7d5d2000 { 69 compatible = "brcm,bcm2711-avs-monitor", 70 "syscon", "simple-mfd"; 71 reg = <0x7d5d2000 0xf00>; 72 73 thermal: thermal { 74 compatible = "brcm,bcm2711-thermal"; 75 #thermal-sensor-cells = <0>; 76 }; 77 }; 78 79 dma: dma@7e007000 { 80 compatible = "brcm,bcm2835-dma"; 81 reg = <0x7e007000 0xb00>; 82 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 89 /* DMA lite 7 - 10 */ 90 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 94 interrupt-names = "dma0", 95 "dma1", 96 "dma2", 97 "dma3", 98 "dma4", 99 "dma5", 100 "dma6", 101 "dma7", 102 "dma8", 103 "dma9", 104 "dma10"; 105 #dma-cells = <1>; 106 brcm,dma-channel-mask = <0x07f5>; 107 }; 108 109 pm: watchdog@7e100000 { 110 compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; 111 #power-domain-cells = <1>; 112 #reset-cells = <1>; 113 reg = <0x7e100000 0x114>, 114 <0x7e00a000 0x24>, 115 <0x7ec11000 0x20>; 116 clocks = <&clocks BCM2835_CLOCK_V3D>, 117 <&clocks BCM2835_CLOCK_PERI_IMAGE>, 118 <&clocks BCM2835_CLOCK_H264>, 119 <&clocks BCM2835_CLOCK_ISP>; 120 clock-names = "v3d", "peri_image", "h264", "isp"; 121 system-power-controller; 122 }; 123 124 rng@7e104000 { 125 compatible = "brcm,bcm2711-rng200"; 126 reg = <0x7e104000 0x28>; 127 }; 128 129 uart2: serial@7e201400 { 130 compatible = "arm,pl011", "arm,primecell"; 131 reg = <0x7e201400 0x200>; 132 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 133 clocks = <&clocks BCM2835_CLOCK_UART>, 134 <&clocks BCM2835_CLOCK_VPU>; 135 clock-names = "uartclk", "apb_pclk"; 136 arm,primecell-periphid = <0x00241011>; 137 status = "disabled"; 138 }; 139 140 uart3: serial@7e201600 { 141 compatible = "arm,pl011", "arm,primecell"; 142 reg = <0x7e201600 0x200>; 143 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&clocks BCM2835_CLOCK_UART>, 145 <&clocks BCM2835_CLOCK_VPU>; 146 clock-names = "uartclk", "apb_pclk"; 147 arm,primecell-periphid = <0x00241011>; 148 status = "disabled"; 149 }; 150 151 uart4: serial@7e201800 { 152 compatible = "arm,pl011", "arm,primecell"; 153 reg = <0x7e201800 0x200>; 154 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&clocks BCM2835_CLOCK_UART>, 156 <&clocks BCM2835_CLOCK_VPU>; 157 clock-names = "uartclk", "apb_pclk"; 158 arm,primecell-periphid = <0x00241011>; 159 status = "disabled"; 160 }; 161 162 uart5: serial@7e201a00 { 163 compatible = "arm,pl011", "arm,primecell"; 164 reg = <0x7e201a00 0x200>; 165 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&clocks BCM2835_CLOCK_UART>, 167 <&clocks BCM2835_CLOCK_VPU>; 168 clock-names = "uartclk", "apb_pclk"; 169 arm,primecell-periphid = <0x00241011>; 170 status = "disabled"; 171 }; 172 173 spi3: spi@7e204600 { 174 compatible = "brcm,bcm2835-spi"; 175 reg = <0x7e204600 0x0200>; 176 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 177 clocks = <&clocks BCM2835_CLOCK_VPU>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 status = "disabled"; 181 }; 182 183 spi4: spi@7e204800 { 184 compatible = "brcm,bcm2835-spi"; 185 reg = <0x7e204800 0x0200>; 186 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&clocks BCM2835_CLOCK_VPU>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 status = "disabled"; 191 }; 192 193 spi5: spi@7e204a00 { 194 compatible = "brcm,bcm2835-spi"; 195 reg = <0x7e204a00 0x0200>; 196 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&clocks BCM2835_CLOCK_VPU>; 198 #address-cells = <1>; 199 #size-cells = <0>; 200 status = "disabled"; 201 }; 202 203 spi6: spi@7e204c00 { 204 compatible = "brcm,bcm2835-spi"; 205 reg = <0x7e204c00 0x0200>; 206 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&clocks BCM2835_CLOCK_VPU>; 208 #address-cells = <1>; 209 #size-cells = <0>; 210 status = "disabled"; 211 }; 212 213 i2c3: i2c@7e205600 { 214 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 215 reg = <0x7e205600 0x200>; 216 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&clocks BCM2835_CLOCK_VPU>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 status = "disabled"; 221 }; 222 223 i2c4: i2c@7e205800 { 224 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 225 reg = <0x7e205800 0x200>; 226 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&clocks BCM2835_CLOCK_VPU>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 status = "disabled"; 231 }; 232 233 i2c5: i2c@7e205a00 { 234 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 235 reg = <0x7e205a00 0x200>; 236 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&clocks BCM2835_CLOCK_VPU>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 status = "disabled"; 241 }; 242 243 i2c6: i2c@7e205c00 { 244 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 245 reg = <0x7e205c00 0x200>; 246 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&clocks BCM2835_CLOCK_VPU>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 status = "disabled"; 251 }; 252 253 pixelvalve0: pixelvalve@7e206000 { 254 compatible = "brcm,bcm2711-pixelvalve0"; 255 reg = <0x7e206000 0x100>; 256 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 257 status = "disabled"; 258 }; 259 260 pixelvalve1: pixelvalve@7e207000 { 261 compatible = "brcm,bcm2711-pixelvalve1"; 262 reg = <0x7e207000 0x100>; 263 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 264 status = "disabled"; 265 }; 266 267 pixelvalve2: pixelvalve@7e20a000 { 268 compatible = "brcm,bcm2711-pixelvalve2"; 269 reg = <0x7e20a000 0x100>; 270 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 271 status = "disabled"; 272 }; 273 274 pwm1: pwm@7e20c800 { 275 compatible = "brcm,bcm2835-pwm"; 276 reg = <0x7e20c800 0x28>; 277 clocks = <&clocks BCM2835_CLOCK_PWM>; 278 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; 279 assigned-clock-rates = <10000000>; 280 #pwm-cells = <2>; 281 status = "disabled"; 282 }; 283 284 pixelvalve4: pixelvalve@7e216000 { 285 compatible = "brcm,bcm2711-pixelvalve4"; 286 reg = <0x7e216000 0x100>; 287 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 288 status = "disabled"; 289 }; 290 291 hvs: hvs@7e400000 { 292 compatible = "brcm,bcm2711-hvs"; 293 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 294 }; 295 296 pixelvalve3: pixelvalve@7ec12000 { 297 compatible = "brcm,bcm2711-pixelvalve3"; 298 reg = <0x7ec12000 0x100>; 299 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 300 status = "disabled"; 301 }; 302 303 dvp: clock@7ef00000 { 304 compatible = "brcm,brcm2711-dvp"; 305 reg = <0x7ef00000 0x10>; 306 clocks = <&clk_108MHz>; 307 #clock-cells = <1>; 308 #reset-cells = <1>; 309 }; 310 311 hdmi0: hdmi@7ef00700 { 312 compatible = "brcm,bcm2711-hdmi0"; 313 reg = <0x7ef00700 0x300>, 314 <0x7ef00300 0x200>, 315 <0x7ef00f00 0x80>, 316 <0x7ef00f80 0x80>, 317 <0x7ef01b00 0x200>, 318 <0x7ef01f00 0x400>, 319 <0x7ef00200 0x80>, 320 <0x7ef04300 0x100>, 321 <0x7ef20000 0x100>; 322 reg-names = "hdmi", 323 "dvp", 324 "phy", 325 "rm", 326 "packet", 327 "metadata", 328 "csc", 329 "cec", 330 "hd"; 331 clock-names = "hdmi", "bvb", "audio", "cec"; 332 resets = <&dvp 0>; 333 ddc = <&ddc0>; 334 dmas = <&dma 10>; 335 dma-names = "audio-rx"; 336 status = "disabled"; 337 }; 338 339 ddc0: i2c@7ef04500 { 340 compatible = "brcm,bcm2711-hdmi-i2c"; 341 reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>; 342 reg-names = "bsc", "auto-i2c"; 343 clock-frequency = <97500>; 344 status = "disabled"; 345 }; 346 347 hdmi1: hdmi@7ef05700 { 348 compatible = "brcm,bcm2711-hdmi1"; 349 reg = <0x7ef05700 0x300>, 350 <0x7ef05300 0x200>, 351 <0x7ef05f00 0x80>, 352 <0x7ef05f80 0x80>, 353 <0x7ef06b00 0x200>, 354 <0x7ef06f00 0x400>, 355 <0x7ef00280 0x80>, 356 <0x7ef09300 0x100>, 357 <0x7ef20000 0x100>; 358 reg-names = "hdmi", 359 "dvp", 360 "phy", 361 "rm", 362 "packet", 363 "metadata", 364 "csc", 365 "cec", 366 "hd"; 367 ddc = <&ddc1>; 368 clock-names = "hdmi", "bvb", "audio", "cec"; 369 resets = <&dvp 1>; 370 dmas = <&dma 17>; 371 dma-names = "audio-rx"; 372 status = "disabled"; 373 }; 374 375 ddc1: i2c@7ef09500 { 376 compatible = "brcm,bcm2711-hdmi-i2c"; 377 reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>; 378 reg-names = "bsc", "auto-i2c"; 379 clock-frequency = <97500>; 380 status = "disabled"; 381 }; 382 }; 383 384 /* 385 * emmc2 has different DMA constraints based on SoC revisions. It was 386 * moved into its own bus, so as for RPi4's firmware to update them. 387 * The firmware will find whether the emmc2bus alias is defined, and if 388 * so, it'll edit the dma-ranges property below accordingly. 389 */ 390 emmc2bus: emmc2bus { 391 compatible = "simple-bus"; 392 #address-cells = <2>; 393 #size-cells = <1>; 394 395 ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; 396 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>; 397 398 emmc2: mmc@7e340000 { 399 compatible = "brcm,bcm2711-emmc2"; 400 reg = <0x0 0x7e340000 0x100>; 401 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&clocks BCM2711_CLOCK_EMMC2>; 403 status = "disabled"; 404 }; 405 }; 406 407 arm-pmu { 408 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3"; 409 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 413 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 414 }; 415 416 timer { 417 compatible = "arm,armv8-timer"; 418 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 419 IRQ_TYPE_LEVEL_LOW)>, 420 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 421 IRQ_TYPE_LEVEL_LOW)>, 422 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 423 IRQ_TYPE_LEVEL_LOW)>, 424 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 425 IRQ_TYPE_LEVEL_LOW)>; 426 /* This only applies to the ARMv7 stub */ 427 arm,cpu-registers-not-fw-configured; 428 }; 429 430 cpus: cpus { 431 #address-cells = <1>; 432 #size-cells = <0>; 433 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit 434 435 cpu0: cpu@0 { 436 device_type = "cpu"; 437 compatible = "arm,cortex-a72"; 438 reg = <0>; 439 enable-method = "spin-table"; 440 cpu-release-addr = <0x0 0x000000d8>; 441 }; 442 443 cpu1: cpu@1 { 444 device_type = "cpu"; 445 compatible = "arm,cortex-a72"; 446 reg = <1>; 447 enable-method = "spin-table"; 448 cpu-release-addr = <0x0 0x000000e0>; 449 }; 450 451 cpu2: cpu@2 { 452 device_type = "cpu"; 453 compatible = "arm,cortex-a72"; 454 reg = <2>; 455 enable-method = "spin-table"; 456 cpu-release-addr = <0x0 0x000000e8>; 457 }; 458 459 cpu3: cpu@3 { 460 device_type = "cpu"; 461 compatible = "arm,cortex-a72"; 462 reg = <3>; 463 enable-method = "spin-table"; 464 cpu-release-addr = <0x0 0x000000f0>; 465 }; 466 }; 467 468 scb { 469 compatible = "simple-bus"; 470 #address-cells = <2>; 471 #size-cells = <1>; 472 473 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, 474 <0x6 0x00000000 0x6 0x00000000 0x40000000>; 475 476 pcie0: pcie@7d500000 { 477 compatible = "brcm,bcm2711-pcie"; 478 reg = <0x0 0x7d500000 0x9310>; 479 device_type = "pci"; 480 #address-cells = <3>; 481 #interrupt-cells = <1>; 482 #size-cells = <2>; 483 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 485 interrupt-names = "pcie", "msi"; 486 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 487 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 488 IRQ_TYPE_LEVEL_HIGH>, 489 <0 0 0 2 &gicv2 GIC_SPI 144 490 IRQ_TYPE_LEVEL_HIGH>, 491 <0 0 0 3 &gicv2 GIC_SPI 145 492 IRQ_TYPE_LEVEL_HIGH>, 493 <0 0 0 4 &gicv2 GIC_SPI 146 494 IRQ_TYPE_LEVEL_HIGH>; 495 msi-controller; 496 msi-parent = <&pcie0>; 497 498 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 499 0x0 0x04000000>; 500 /* 501 * The wrapper around the PCIe block has a bug 502 * preventing it from accessing beyond the first 3GB of 503 * memory. 504 */ 505 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 506 0x0 0xc0000000>; 507 brcm,enable-ssc; 508 }; 509 510 genet: ethernet@7d580000 { 511 compatible = "brcm,bcm2711-genet-v5"; 512 reg = <0x0 0x7d580000 0x10000>; 513 #address-cells = <0x1>; 514 #size-cells = <0x1>; 515 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 517 status = "disabled"; 518 519 genet_mdio: mdio@e14 { 520 compatible = "brcm,genet-mdio-v5"; 521 reg = <0xe14 0x8>; 522 reg-names = "mdio"; 523 #address-cells = <0x1>; 524 #size-cells = <0x0>; 525 }; 526 }; 527 }; 528}; 529 530&clk_osc { 531 clock-frequency = <54000000>; 532}; 533 534&clocks { 535 compatible = "brcm,bcm2711-cprman"; 536}; 537 538&cpu_thermal { 539 coefficients = <(-487) 410040>; 540 thermal-sensors = <&thermal>; 541}; 542 543&dsi0 { 544 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 545}; 546 547&dsi1 { 548 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 549}; 550 551&gpio { 552 compatible = "brcm,bcm2711-gpio"; 553 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 557 558 gpio-ranges = <&gpio 0 0 58>; 559 560 gpclk0_gpio49: gpclk0_gpio49 { 561 pin-gpclk { 562 pins = "gpio49"; 563 function = "alt1"; 564 bias-disable; 565 }; 566 }; 567 gpclk1_gpio50: gpclk1_gpio50 { 568 pin-gpclk { 569 pins = "gpio50"; 570 function = "alt1"; 571 bias-disable; 572 }; 573 }; 574 gpclk2_gpio51: gpclk2_gpio51 { 575 pin-gpclk { 576 pins = "gpio51"; 577 function = "alt1"; 578 bias-disable; 579 }; 580 }; 581 582 i2c0_gpio46: i2c0_gpio46 { 583 pin-sda { 584 function = "alt0"; 585 pins = "gpio46"; 586 bias-pull-up; 587 }; 588 pin-scl { 589 function = "alt0"; 590 pins = "gpio47"; 591 bias-disable; 592 }; 593 }; 594 i2c1_gpio46: i2c1_gpio46 { 595 pin-sda { 596 function = "alt1"; 597 pins = "gpio46"; 598 bias-pull-up; 599 }; 600 pin-scl { 601 function = "alt1"; 602 pins = "gpio47"; 603 bias-disable; 604 }; 605 }; 606 i2c3_gpio2: i2c3_gpio2 { 607 pin-sda { 608 function = "alt5"; 609 pins = "gpio2"; 610 bias-pull-up; 611 }; 612 pin-scl { 613 function = "alt5"; 614 pins = "gpio3"; 615 bias-disable; 616 }; 617 }; 618 i2c3_gpio4: i2c3_gpio4 { 619 pin-sda { 620 function = "alt5"; 621 pins = "gpio4"; 622 bias-pull-up; 623 }; 624 pin-scl { 625 function = "alt5"; 626 pins = "gpio5"; 627 bias-disable; 628 }; 629 }; 630 i2c4_gpio6: i2c4_gpio6 { 631 pin-sda { 632 function = "alt5"; 633 pins = "gpio6"; 634 bias-pull-up; 635 }; 636 pin-scl { 637 function = "alt5"; 638 pins = "gpio7"; 639 bias-disable; 640 }; 641 }; 642 i2c4_gpio8: i2c4_gpio8 { 643 pin-sda { 644 function = "alt5"; 645 pins = "gpio8"; 646 bias-pull-up; 647 }; 648 pin-scl { 649 function = "alt5"; 650 pins = "gpio9"; 651 bias-disable; 652 }; 653 }; 654 i2c5_gpio10: i2c5_gpio10 { 655 pin-sda { 656 function = "alt5"; 657 pins = "gpio10"; 658 bias-pull-up; 659 }; 660 pin-scl { 661 function = "alt5"; 662 pins = "gpio11"; 663 bias-disable; 664 }; 665 }; 666 i2c5_gpio12: i2c5_gpio12 { 667 pin-sda { 668 function = "alt5"; 669 pins = "gpio12"; 670 bias-pull-up; 671 }; 672 pin-scl { 673 function = "alt5"; 674 pins = "gpio13"; 675 bias-disable; 676 }; 677 }; 678 i2c6_gpio0: i2c6_gpio0 { 679 pin-sda { 680 function = "alt5"; 681 pins = "gpio0"; 682 bias-pull-up; 683 }; 684 pin-scl { 685 function = "alt5"; 686 pins = "gpio1"; 687 bias-disable; 688 }; 689 }; 690 i2c6_gpio22: i2c6_gpio22 { 691 pin-sda { 692 function = "alt5"; 693 pins = "gpio22"; 694 bias-pull-up; 695 }; 696 pin-scl { 697 function = "alt5"; 698 pins = "gpio23"; 699 bias-disable; 700 }; 701 }; 702 i2c_slave_gpio8: i2c_slave_gpio8 { 703 pins-i2c-slave { 704 pins = "gpio8", 705 "gpio9", 706 "gpio10", 707 "gpio11"; 708 function = "alt3"; 709 }; 710 }; 711 712 jtag_gpio48: jtag_gpio48 { 713 pins-jtag { 714 pins = "gpio48", 715 "gpio49", 716 "gpio50", 717 "gpio51", 718 "gpio52", 719 "gpio53"; 720 function = "alt4"; 721 }; 722 }; 723 724 mii_gpio28: mii_gpio28 { 725 pins-mii { 726 pins = "gpio28", 727 "gpio29", 728 "gpio30", 729 "gpio31"; 730 function = "alt4"; 731 }; 732 }; 733 mii_gpio36: mii_gpio36 { 734 pins-mii { 735 pins = "gpio36", 736 "gpio37", 737 "gpio38", 738 "gpio39"; 739 function = "alt5"; 740 }; 741 }; 742 743 pcm_gpio50: pcm_gpio50 { 744 pins-pcm { 745 pins = "gpio50", 746 "gpio51", 747 "gpio52", 748 "gpio53"; 749 function = "alt2"; 750 }; 751 }; 752 753 pwm0_0_gpio12: pwm0_0_gpio12 { 754 pin-pwm { 755 pins = "gpio12"; 756 function = "alt0"; 757 bias-disable; 758 }; 759 }; 760 pwm0_0_gpio18: pwm0_0_gpio18 { 761 pin-pwm { 762 pins = "gpio18"; 763 function = "alt5"; 764 bias-disable; 765 }; 766 }; 767 pwm1_0_gpio40: pwm1_0_gpio40 { 768 pin-pwm { 769 pins = "gpio40"; 770 function = "alt0"; 771 bias-disable; 772 }; 773 }; 774 pwm0_1_gpio13: pwm0_1_gpio13 { 775 pin-pwm { 776 pins = "gpio13"; 777 function = "alt0"; 778 bias-disable; 779 }; 780 }; 781 pwm0_1_gpio19: pwm0_1_gpio19 { 782 pin-pwm { 783 pins = "gpio19"; 784 function = "alt5"; 785 bias-disable; 786 }; 787 }; 788 pwm1_1_gpio41: pwm1_1_gpio41 { 789 pin-pwm { 790 pins = "gpio41"; 791 function = "alt0"; 792 bias-disable; 793 }; 794 }; 795 pwm0_1_gpio45: pwm0_1_gpio45 { 796 pin-pwm { 797 pins = "gpio45"; 798 function = "alt0"; 799 bias-disable; 800 }; 801 }; 802 pwm0_0_gpio52: pwm0_0_gpio52 { 803 pin-pwm { 804 pins = "gpio52"; 805 function = "alt1"; 806 bias-disable; 807 }; 808 }; 809 pwm0_1_gpio53: pwm0_1_gpio53 { 810 pin-pwm { 811 pins = "gpio53"; 812 function = "alt1"; 813 bias-disable; 814 }; 815 }; 816 817 rgmii_gpio35: rgmii_gpio35 { 818 pin-start-stop { 819 pins = "gpio35"; 820 function = "alt4"; 821 }; 822 pin-rx-ok { 823 pins = "gpio36"; 824 function = "alt4"; 825 }; 826 }; 827 rgmii_irq_gpio34: rgmii_irq_gpio34 { 828 pin-irq { 829 pins = "gpio34"; 830 function = "alt5"; 831 }; 832 }; 833 rgmii_irq_gpio39: rgmii_irq_gpio39 { 834 pin-irq { 835 pins = "gpio39"; 836 function = "alt4"; 837 }; 838 }; 839 rgmii_mdio_gpio28: rgmii_mdio_gpio28 { 840 pins-mdio { 841 pins = "gpio28", 842 "gpio29"; 843 function = "alt5"; 844 }; 845 }; 846 rgmii_mdio_gpio37: rgmii_mdio_gpio37 { 847 pins-mdio { 848 pins = "gpio37", 849 "gpio38"; 850 function = "alt4"; 851 }; 852 }; 853 854 spi0_gpio46: spi0_gpio46 { 855 pins-spi { 856 pins = "gpio46", 857 "gpio47", 858 "gpio48", 859 "gpio49"; 860 function = "alt2"; 861 }; 862 }; 863 spi2_gpio46: spi2_gpio46 { 864 pins-spi { 865 pins = "gpio46", 866 "gpio47", 867 "gpio48", 868 "gpio49", 869 "gpio50"; 870 function = "alt5"; 871 }; 872 }; 873 spi3_gpio0: spi3_gpio0 { 874 pins-spi { 875 pins = "gpio0", 876 "gpio1", 877 "gpio2", 878 "gpio3"; 879 function = "alt3"; 880 }; 881 }; 882 spi4_gpio4: spi4_gpio4 { 883 pins-spi { 884 pins = "gpio4", 885 "gpio5", 886 "gpio6", 887 "gpio7"; 888 function = "alt3"; 889 }; 890 }; 891 spi5_gpio12: spi5_gpio12 { 892 pins-spi { 893 pins = "gpio12", 894 "gpio13", 895 "gpio14", 896 "gpio15"; 897 function = "alt3"; 898 }; 899 }; 900 spi6_gpio18: spi6_gpio18 { 901 pins-spi { 902 pins = "gpio18", 903 "gpio19", 904 "gpio20", 905 "gpio21"; 906 function = "alt3"; 907 }; 908 }; 909 910 uart2_gpio0: uart2_gpio0 { 911 pin-tx { 912 pins = "gpio0"; 913 function = "alt4"; 914 bias-disable; 915 }; 916 pin-rx { 917 pins = "gpio1"; 918 function = "alt4"; 919 bias-pull-up; 920 }; 921 }; 922 uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 { 923 pin-cts { 924 pins = "gpio2"; 925 function = "alt4"; 926 bias-pull-up; 927 }; 928 pin-rts { 929 pins = "gpio3"; 930 function = "alt4"; 931 bias-disable; 932 }; 933 }; 934 uart3_gpio4: uart3_gpio4 { 935 pin-tx { 936 pins = "gpio4"; 937 function = "alt4"; 938 bias-disable; 939 }; 940 pin-rx { 941 pins = "gpio5"; 942 function = "alt4"; 943 bias-pull-up; 944 }; 945 }; 946 uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 { 947 pin-cts { 948 pins = "gpio6"; 949 function = "alt4"; 950 bias-pull-up; 951 }; 952 pin-rts { 953 pins = "gpio7"; 954 function = "alt4"; 955 bias-disable; 956 }; 957 }; 958 uart4_gpio8: uart4_gpio8 { 959 pin-tx { 960 pins = "gpio8"; 961 function = "alt4"; 962 bias-disable; 963 }; 964 pin-rx { 965 pins = "gpio9"; 966 function = "alt4"; 967 bias-pull-up; 968 }; 969 }; 970 uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 { 971 pin-cts { 972 pins = "gpio10"; 973 function = "alt4"; 974 bias-pull-up; 975 }; 976 pin-rts { 977 pins = "gpio11"; 978 function = "alt4"; 979 bias-disable; 980 }; 981 }; 982 uart5_gpio12: uart5_gpio12 { 983 pin-tx { 984 pins = "gpio12"; 985 function = "alt4"; 986 bias-disable; 987 }; 988 pin-rx { 989 pins = "gpio13"; 990 function = "alt4"; 991 bias-pull-up; 992 }; 993 }; 994 uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 { 995 pin-cts { 996 pins = "gpio14"; 997 function = "alt4"; 998 bias-pull-up; 999 }; 1000 pin-rts { 1001 pins = "gpio15"; 1002 function = "alt4"; 1003 bias-disable; 1004 }; 1005 }; 1006}; 1007 1008&rmem { 1009 #address-cells = <2>; 1010}; 1011 1012&cma { 1013 /* 1014 * arm64 reserves the CMA by default somewhere in ZONE_DMA32, 1015 * that's not good enough for the BCM2711 as some devices can 1016 * only address the lower 1G of memory (ZONE_DMA). 1017 */ 1018 alloc-ranges = <0x0 0x00000000 0x40000000>; 1019}; 1020 1021&i2c0 { 1022 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 1023 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1024}; 1025 1026&i2c1 { 1027 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 1028 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1029}; 1030 1031&mailbox { 1032 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1033}; 1034 1035&sdhci { 1036 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1037}; 1038 1039&sdhost { 1040 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1041}; 1042 1043&spi { 1044 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1045}; 1046 1047&spi1 { 1048 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1049}; 1050 1051&spi2 { 1052 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1053}; 1054 1055&system_timer { 1056 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1060}; 1061 1062&txp { 1063 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1064}; 1065 1066&uart0 { 1067 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1068}; 1069 1070&uart1 { 1071 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1072}; 1073 1074&usb { 1075 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1076}; 1077 1078&vec { 1079 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1080}; 1081