1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Single-step support.
4 *
5 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
6 */
7 #include <linux/kernel.h>
8 #include <linux/kprobes.h>
9 #include <linux/ptrace.h>
10 #include <linux/prefetch.h>
11 #include <asm/sstep.h>
12 #include <asm/processor.h>
13 #include <linux/uaccess.h>
14 #include <asm/cpu_has_feature.h>
15 #include <asm/cputable.h>
16 #include <asm/disassemble.h>
17
18 extern char system_call_common[];
19 extern char system_call_vectored_emulate[];
20
21 #ifdef CONFIG_PPC64
22 /* Bits in SRR1 that are copied from MSR */
23 #define MSR_MASK 0xffffffff87c0ffffUL
24 #else
25 #define MSR_MASK 0x87c0ffff
26 #endif
27
28 /* Bits in XER */
29 #define XER_SO 0x80000000U
30 #define XER_OV 0x40000000U
31 #define XER_CA 0x20000000U
32 #define XER_OV32 0x00080000U
33 #define XER_CA32 0x00040000U
34
35 #ifdef CONFIG_PPC_FPU
36 /*
37 * Functions in ldstfp.S
38 */
39 extern void get_fpr(int rn, double *p);
40 extern void put_fpr(int rn, const double *p);
41 extern void get_vr(int rn, __vector128 *p);
42 extern void put_vr(int rn, __vector128 *p);
43 extern void load_vsrn(int vsr, const void *p);
44 extern void store_vsrn(int vsr, void *p);
45 extern void conv_sp_to_dp(const float *sp, double *dp);
46 extern void conv_dp_to_sp(const double *dp, float *sp);
47 #endif
48
49 #ifdef __powerpc64__
50 /*
51 * Functions in quad.S
52 */
53 extern int do_lq(unsigned long ea, unsigned long *regs);
54 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
55 extern int do_lqarx(unsigned long ea, unsigned long *regs);
56 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
57 unsigned int *crp);
58 #endif
59
60 #ifdef __LITTLE_ENDIAN__
61 #define IS_LE 1
62 #define IS_BE 0
63 #else
64 #define IS_LE 0
65 #define IS_BE 1
66 #endif
67
68 /*
69 * Emulate the truncation of 64 bit values in 32-bit mode.
70 */
truncate_if_32bit(unsigned long msr,unsigned long val)71 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
72 unsigned long val)
73 {
74 #ifdef __powerpc64__
75 if ((msr & MSR_64BIT) == 0)
76 val &= 0xffffffffUL;
77 #endif
78 return val;
79 }
80
81 /*
82 * Determine whether a conditional branch instruction would branch.
83 */
branch_taken(unsigned int instr,const struct pt_regs * regs,struct instruction_op * op)84 static nokprobe_inline int branch_taken(unsigned int instr,
85 const struct pt_regs *regs,
86 struct instruction_op *op)
87 {
88 unsigned int bo = (instr >> 21) & 0x1f;
89 unsigned int bi;
90
91 if ((bo & 4) == 0) {
92 /* decrement counter */
93 op->type |= DECCTR;
94 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
95 return 0;
96 }
97 if ((bo & 0x10) == 0) {
98 /* check bit from CR */
99 bi = (instr >> 16) & 0x1f;
100 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
101 return 0;
102 }
103 return 1;
104 }
105
address_ok(struct pt_regs * regs,unsigned long ea,int nb)106 static nokprobe_inline long address_ok(struct pt_regs *regs,
107 unsigned long ea, int nb)
108 {
109 if (!user_mode(regs))
110 return 1;
111 if (__access_ok(ea, nb))
112 return 1;
113 if (__access_ok(ea, 1))
114 /* Access overlaps the end of the user region */
115 regs->dar = TASK_SIZE_MAX - 1;
116 else
117 regs->dar = ea;
118 return 0;
119 }
120
121 /*
122 * Calculate effective address for a D-form instruction
123 */
dform_ea(unsigned int instr,const struct pt_regs * regs)124 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
125 const struct pt_regs *regs)
126 {
127 int ra;
128 unsigned long ea;
129
130 ra = (instr >> 16) & 0x1f;
131 ea = (signed short) instr; /* sign-extend */
132 if (ra)
133 ea += regs->gpr[ra];
134
135 return ea;
136 }
137
138 #ifdef __powerpc64__
139 /*
140 * Calculate effective address for a DS-form instruction
141 */
dsform_ea(unsigned int instr,const struct pt_regs * regs)142 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
143 const struct pt_regs *regs)
144 {
145 int ra;
146 unsigned long ea;
147
148 ra = (instr >> 16) & 0x1f;
149 ea = (signed short) (instr & ~3); /* sign-extend */
150 if (ra)
151 ea += regs->gpr[ra];
152
153 return ea;
154 }
155
156 /*
157 * Calculate effective address for a DQ-form instruction
158 */
dqform_ea(unsigned int instr,const struct pt_regs * regs)159 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
160 const struct pt_regs *regs)
161 {
162 int ra;
163 unsigned long ea;
164
165 ra = (instr >> 16) & 0x1f;
166 ea = (signed short) (instr & ~0xf); /* sign-extend */
167 if (ra)
168 ea += regs->gpr[ra];
169
170 return ea;
171 }
172 #endif /* __powerpc64 */
173
174 /*
175 * Calculate effective address for an X-form instruction
176 */
xform_ea(unsigned int instr,const struct pt_regs * regs)177 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
178 const struct pt_regs *regs)
179 {
180 int ra, rb;
181 unsigned long ea;
182
183 ra = (instr >> 16) & 0x1f;
184 rb = (instr >> 11) & 0x1f;
185 ea = regs->gpr[rb];
186 if (ra)
187 ea += regs->gpr[ra];
188
189 return ea;
190 }
191
192 /*
193 * Calculate effective address for a MLS:D-form / 8LS:D-form
194 * prefixed instruction
195 */
mlsd_8lsd_ea(unsigned int instr,unsigned int suffix,const struct pt_regs * regs)196 static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
197 unsigned int suffix,
198 const struct pt_regs *regs)
199 {
200 int ra, prefix_r;
201 unsigned int dd;
202 unsigned long ea, d0, d1, d;
203
204 prefix_r = GET_PREFIX_R(instr);
205 ra = GET_PREFIX_RA(suffix);
206
207 d0 = instr & 0x3ffff;
208 d1 = suffix & 0xffff;
209 d = (d0 << 16) | d1;
210
211 /*
212 * sign extend a 34 bit number
213 */
214 dd = (unsigned int)(d >> 2);
215 ea = (signed int)dd;
216 ea = (ea << 2) | (d & 0x3);
217
218 if (!prefix_r && ra)
219 ea += regs->gpr[ra];
220 else if (!prefix_r && !ra)
221 ; /* Leave ea as is */
222 else if (prefix_r)
223 ea += regs->nip;
224
225 /*
226 * (prefix_r && ra) is an invalid form. Should already be
227 * checked for by caller!
228 */
229
230 return ea;
231 }
232
233 /*
234 * Return the largest power of 2, not greater than sizeof(unsigned long),
235 * such that x is a multiple of it.
236 */
max_align(unsigned long x)237 static nokprobe_inline unsigned long max_align(unsigned long x)
238 {
239 x |= sizeof(unsigned long);
240 return x & -x; /* isolates rightmost bit */
241 }
242
byterev_2(unsigned long x)243 static nokprobe_inline unsigned long byterev_2(unsigned long x)
244 {
245 return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
246 }
247
byterev_4(unsigned long x)248 static nokprobe_inline unsigned long byterev_4(unsigned long x)
249 {
250 return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
251 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
252 }
253
254 #ifdef __powerpc64__
byterev_8(unsigned long x)255 static nokprobe_inline unsigned long byterev_8(unsigned long x)
256 {
257 return (byterev_4(x) << 32) | byterev_4(x >> 32);
258 }
259 #endif
260
do_byte_reverse(void * ptr,int nb)261 static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
262 {
263 switch (nb) {
264 case 2:
265 *(u16 *)ptr = byterev_2(*(u16 *)ptr);
266 break;
267 case 4:
268 *(u32 *)ptr = byterev_4(*(u32 *)ptr);
269 break;
270 #ifdef __powerpc64__
271 case 8:
272 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
273 break;
274 case 16: {
275 unsigned long *up = (unsigned long *)ptr;
276 unsigned long tmp;
277 tmp = byterev_8(up[0]);
278 up[0] = byterev_8(up[1]);
279 up[1] = tmp;
280 break;
281 }
282 #endif
283 default:
284 WARN_ON_ONCE(1);
285 }
286 }
287
read_mem_aligned(unsigned long * dest,unsigned long ea,int nb,struct pt_regs * regs)288 static nokprobe_inline int read_mem_aligned(unsigned long *dest,
289 unsigned long ea, int nb,
290 struct pt_regs *regs)
291 {
292 int err = 0;
293 unsigned long x = 0;
294
295 switch (nb) {
296 case 1:
297 err = __get_user(x, (unsigned char __user *) ea);
298 break;
299 case 2:
300 err = __get_user(x, (unsigned short __user *) ea);
301 break;
302 case 4:
303 err = __get_user(x, (unsigned int __user *) ea);
304 break;
305 #ifdef __powerpc64__
306 case 8:
307 err = __get_user(x, (unsigned long __user *) ea);
308 break;
309 #endif
310 }
311 if (!err)
312 *dest = x;
313 else
314 regs->dar = ea;
315 return err;
316 }
317
318 /*
319 * Copy from userspace to a buffer, using the largest possible
320 * aligned accesses, up to sizeof(long).
321 */
copy_mem_in(u8 * dest,unsigned long ea,int nb,struct pt_regs * regs)322 static nokprobe_inline int copy_mem_in(u8 *dest, unsigned long ea, int nb,
323 struct pt_regs *regs)
324 {
325 int err = 0;
326 int c;
327
328 for (; nb > 0; nb -= c) {
329 c = max_align(ea);
330 if (c > nb)
331 c = max_align(nb);
332 switch (c) {
333 case 1:
334 err = __get_user(*dest, (unsigned char __user *) ea);
335 break;
336 case 2:
337 err = __get_user(*(u16 *)dest,
338 (unsigned short __user *) ea);
339 break;
340 case 4:
341 err = __get_user(*(u32 *)dest,
342 (unsigned int __user *) ea);
343 break;
344 #ifdef __powerpc64__
345 case 8:
346 err = __get_user(*(unsigned long *)dest,
347 (unsigned long __user *) ea);
348 break;
349 #endif
350 }
351 if (err) {
352 regs->dar = ea;
353 return err;
354 }
355 dest += c;
356 ea += c;
357 }
358 return 0;
359 }
360
read_mem_unaligned(unsigned long * dest,unsigned long ea,int nb,struct pt_regs * regs)361 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
362 unsigned long ea, int nb,
363 struct pt_regs *regs)
364 {
365 union {
366 unsigned long ul;
367 u8 b[sizeof(unsigned long)];
368 } u;
369 int i;
370 int err;
371
372 u.ul = 0;
373 i = IS_BE ? sizeof(unsigned long) - nb : 0;
374 err = copy_mem_in(&u.b[i], ea, nb, regs);
375 if (!err)
376 *dest = u.ul;
377 return err;
378 }
379
380 /*
381 * Read memory at address ea for nb bytes, return 0 for success
382 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
383 * If nb < sizeof(long), the result is right-justified on BE systems.
384 */
read_mem(unsigned long * dest,unsigned long ea,int nb,struct pt_regs * regs)385 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
386 struct pt_regs *regs)
387 {
388 if (!address_ok(regs, ea, nb))
389 return -EFAULT;
390 if ((ea & (nb - 1)) == 0)
391 return read_mem_aligned(dest, ea, nb, regs);
392 return read_mem_unaligned(dest, ea, nb, regs);
393 }
394 NOKPROBE_SYMBOL(read_mem);
395
write_mem_aligned(unsigned long val,unsigned long ea,int nb,struct pt_regs * regs)396 static nokprobe_inline int write_mem_aligned(unsigned long val,
397 unsigned long ea, int nb,
398 struct pt_regs *regs)
399 {
400 int err = 0;
401
402 switch (nb) {
403 case 1:
404 err = __put_user(val, (unsigned char __user *) ea);
405 break;
406 case 2:
407 err = __put_user(val, (unsigned short __user *) ea);
408 break;
409 case 4:
410 err = __put_user(val, (unsigned int __user *) ea);
411 break;
412 #ifdef __powerpc64__
413 case 8:
414 err = __put_user(val, (unsigned long __user *) ea);
415 break;
416 #endif
417 }
418 if (err)
419 regs->dar = ea;
420 return err;
421 }
422
423 /*
424 * Copy from a buffer to userspace, using the largest possible
425 * aligned accesses, up to sizeof(long).
426 */
copy_mem_out(u8 * dest,unsigned long ea,int nb,struct pt_regs * regs)427 static nokprobe_inline int copy_mem_out(u8 *dest, unsigned long ea, int nb,
428 struct pt_regs *regs)
429 {
430 int err = 0;
431 int c;
432
433 for (; nb > 0; nb -= c) {
434 c = max_align(ea);
435 if (c > nb)
436 c = max_align(nb);
437 switch (c) {
438 case 1:
439 err = __put_user(*dest, (unsigned char __user *) ea);
440 break;
441 case 2:
442 err = __put_user(*(u16 *)dest,
443 (unsigned short __user *) ea);
444 break;
445 case 4:
446 err = __put_user(*(u32 *)dest,
447 (unsigned int __user *) ea);
448 break;
449 #ifdef __powerpc64__
450 case 8:
451 err = __put_user(*(unsigned long *)dest,
452 (unsigned long __user *) ea);
453 break;
454 #endif
455 }
456 if (err) {
457 regs->dar = ea;
458 return err;
459 }
460 dest += c;
461 ea += c;
462 }
463 return 0;
464 }
465
write_mem_unaligned(unsigned long val,unsigned long ea,int nb,struct pt_regs * regs)466 static nokprobe_inline int write_mem_unaligned(unsigned long val,
467 unsigned long ea, int nb,
468 struct pt_regs *regs)
469 {
470 union {
471 unsigned long ul;
472 u8 b[sizeof(unsigned long)];
473 } u;
474 int i;
475
476 u.ul = val;
477 i = IS_BE ? sizeof(unsigned long) - nb : 0;
478 return copy_mem_out(&u.b[i], ea, nb, regs);
479 }
480
481 /*
482 * Write memory at address ea for nb bytes, return 0 for success
483 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
484 */
write_mem(unsigned long val,unsigned long ea,int nb,struct pt_regs * regs)485 static int write_mem(unsigned long val, unsigned long ea, int nb,
486 struct pt_regs *regs)
487 {
488 if (!address_ok(regs, ea, nb))
489 return -EFAULT;
490 if ((ea & (nb - 1)) == 0)
491 return write_mem_aligned(val, ea, nb, regs);
492 return write_mem_unaligned(val, ea, nb, regs);
493 }
494 NOKPROBE_SYMBOL(write_mem);
495
496 #ifdef CONFIG_PPC_FPU
497 /*
498 * These access either the real FP register or the image in the
499 * thread_struct, depending on regs->msr & MSR_FP.
500 */
do_fp_load(struct instruction_op * op,unsigned long ea,struct pt_regs * regs,bool cross_endian)501 static int do_fp_load(struct instruction_op *op, unsigned long ea,
502 struct pt_regs *regs, bool cross_endian)
503 {
504 int err, rn, nb;
505 union {
506 int i;
507 unsigned int u;
508 float f;
509 double d[2];
510 unsigned long l[2];
511 u8 b[2 * sizeof(double)];
512 } u;
513
514 nb = GETSIZE(op->type);
515 if (!address_ok(regs, ea, nb))
516 return -EFAULT;
517 rn = op->reg;
518 err = copy_mem_in(u.b, ea, nb, regs);
519 if (err)
520 return err;
521 if (unlikely(cross_endian)) {
522 do_byte_reverse(u.b, min(nb, 8));
523 if (nb == 16)
524 do_byte_reverse(&u.b[8], 8);
525 }
526 preempt_disable();
527 if (nb == 4) {
528 if (op->type & FPCONV)
529 conv_sp_to_dp(&u.f, &u.d[0]);
530 else if (op->type & SIGNEXT)
531 u.l[0] = u.i;
532 else
533 u.l[0] = u.u;
534 }
535 if (regs->msr & MSR_FP)
536 put_fpr(rn, &u.d[0]);
537 else
538 current->thread.TS_FPR(rn) = u.l[0];
539 if (nb == 16) {
540 /* lfdp */
541 rn |= 1;
542 if (regs->msr & MSR_FP)
543 put_fpr(rn, &u.d[1]);
544 else
545 current->thread.TS_FPR(rn) = u.l[1];
546 }
547 preempt_enable();
548 return 0;
549 }
550 NOKPROBE_SYMBOL(do_fp_load);
551
do_fp_store(struct instruction_op * op,unsigned long ea,struct pt_regs * regs,bool cross_endian)552 static int do_fp_store(struct instruction_op *op, unsigned long ea,
553 struct pt_regs *regs, bool cross_endian)
554 {
555 int rn, nb;
556 union {
557 unsigned int u;
558 float f;
559 double d[2];
560 unsigned long l[2];
561 u8 b[2 * sizeof(double)];
562 } u;
563
564 nb = GETSIZE(op->type);
565 if (!address_ok(regs, ea, nb))
566 return -EFAULT;
567 rn = op->reg;
568 preempt_disable();
569 if (regs->msr & MSR_FP)
570 get_fpr(rn, &u.d[0]);
571 else
572 u.l[0] = current->thread.TS_FPR(rn);
573 if (nb == 4) {
574 if (op->type & FPCONV)
575 conv_dp_to_sp(&u.d[0], &u.f);
576 else
577 u.u = u.l[0];
578 }
579 if (nb == 16) {
580 rn |= 1;
581 if (regs->msr & MSR_FP)
582 get_fpr(rn, &u.d[1]);
583 else
584 u.l[1] = current->thread.TS_FPR(rn);
585 }
586 preempt_enable();
587 if (unlikely(cross_endian)) {
588 do_byte_reverse(u.b, min(nb, 8));
589 if (nb == 16)
590 do_byte_reverse(&u.b[8], 8);
591 }
592 return copy_mem_out(u.b, ea, nb, regs);
593 }
594 NOKPROBE_SYMBOL(do_fp_store);
595 #endif
596
597 #ifdef CONFIG_ALTIVEC
598 /* For Altivec/VMX, no need to worry about alignment */
do_vec_load(int rn,unsigned long ea,int size,struct pt_regs * regs,bool cross_endian)599 static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
600 int size, struct pt_regs *regs,
601 bool cross_endian)
602 {
603 int err;
604 union {
605 __vector128 v;
606 u8 b[sizeof(__vector128)];
607 } u = {};
608
609 if (!address_ok(regs, ea & ~0xfUL, 16))
610 return -EFAULT;
611 /* align to multiple of size */
612 ea &= ~(size - 1);
613 err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
614 if (err)
615 return err;
616 if (unlikely(cross_endian))
617 do_byte_reverse(&u.b[ea & 0xf], size);
618 preempt_disable();
619 if (regs->msr & MSR_VEC)
620 put_vr(rn, &u.v);
621 else
622 current->thread.vr_state.vr[rn] = u.v;
623 preempt_enable();
624 return 0;
625 }
626
do_vec_store(int rn,unsigned long ea,int size,struct pt_regs * regs,bool cross_endian)627 static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
628 int size, struct pt_regs *regs,
629 bool cross_endian)
630 {
631 union {
632 __vector128 v;
633 u8 b[sizeof(__vector128)];
634 } u;
635
636 if (!address_ok(regs, ea & ~0xfUL, 16))
637 return -EFAULT;
638 /* align to multiple of size */
639 ea &= ~(size - 1);
640
641 preempt_disable();
642 if (regs->msr & MSR_VEC)
643 get_vr(rn, &u.v);
644 else
645 u.v = current->thread.vr_state.vr[rn];
646 preempt_enable();
647 if (unlikely(cross_endian))
648 do_byte_reverse(&u.b[ea & 0xf], size);
649 return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
650 }
651 #endif /* CONFIG_ALTIVEC */
652
653 #ifdef __powerpc64__
emulate_lq(struct pt_regs * regs,unsigned long ea,int reg,bool cross_endian)654 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
655 int reg, bool cross_endian)
656 {
657 int err;
658
659 if (!address_ok(regs, ea, 16))
660 return -EFAULT;
661 /* if aligned, should be atomic */
662 if ((ea & 0xf) == 0) {
663 err = do_lq(ea, ®s->gpr[reg]);
664 } else {
665 err = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs);
666 if (!err)
667 err = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs);
668 }
669 if (!err && unlikely(cross_endian))
670 do_byte_reverse(®s->gpr[reg], 16);
671 return err;
672 }
673
emulate_stq(struct pt_regs * regs,unsigned long ea,int reg,bool cross_endian)674 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
675 int reg, bool cross_endian)
676 {
677 int err;
678 unsigned long vals[2];
679
680 if (!address_ok(regs, ea, 16))
681 return -EFAULT;
682 vals[0] = regs->gpr[reg];
683 vals[1] = regs->gpr[reg + 1];
684 if (unlikely(cross_endian))
685 do_byte_reverse(vals, 16);
686
687 /* if aligned, should be atomic */
688 if ((ea & 0xf) == 0)
689 return do_stq(ea, vals[0], vals[1]);
690
691 err = write_mem(vals[IS_LE], ea, 8, regs);
692 if (!err)
693 err = write_mem(vals[IS_BE], ea + 8, 8, regs);
694 return err;
695 }
696 #endif /* __powerpc64 */
697
698 #ifdef CONFIG_VSX
emulate_vsx_load(struct instruction_op * op,union vsx_reg * reg,const void * mem,bool rev)699 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
700 const void *mem, bool rev)
701 {
702 int size, read_size;
703 int i, j;
704 const unsigned int *wp;
705 const unsigned short *hp;
706 const unsigned char *bp;
707
708 size = GETSIZE(op->type);
709 reg->d[0] = reg->d[1] = 0;
710
711 switch (op->element_size) {
712 case 16:
713 /* whole vector; lxv[x] or lxvl[l] */
714 if (size == 0)
715 break;
716 memcpy(reg, mem, size);
717 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
718 rev = !rev;
719 if (rev)
720 do_byte_reverse(reg, 16);
721 break;
722 case 8:
723 /* scalar loads, lxvd2x, lxvdsx */
724 read_size = (size >= 8) ? 8 : size;
725 i = IS_LE ? 8 : 8 - read_size;
726 memcpy(®->b[i], mem, read_size);
727 if (rev)
728 do_byte_reverse(®->b[i], 8);
729 if (size < 8) {
730 if (op->type & SIGNEXT) {
731 /* size == 4 is the only case here */
732 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
733 } else if (op->vsx_flags & VSX_FPCONV) {
734 preempt_disable();
735 conv_sp_to_dp(®->fp[1 + IS_LE],
736 ®->dp[IS_LE]);
737 preempt_enable();
738 }
739 } else {
740 if (size == 16) {
741 unsigned long v = *(unsigned long *)(mem + 8);
742 reg->d[IS_BE] = !rev ? v : byterev_8(v);
743 } else if (op->vsx_flags & VSX_SPLAT)
744 reg->d[IS_BE] = reg->d[IS_LE];
745 }
746 break;
747 case 4:
748 /* lxvw4x, lxvwsx */
749 wp = mem;
750 for (j = 0; j < size / 4; ++j) {
751 i = IS_LE ? 3 - j : j;
752 reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
753 }
754 if (op->vsx_flags & VSX_SPLAT) {
755 u32 val = reg->w[IS_LE ? 3 : 0];
756 for (; j < 4; ++j) {
757 i = IS_LE ? 3 - j : j;
758 reg->w[i] = val;
759 }
760 }
761 break;
762 case 2:
763 /* lxvh8x */
764 hp = mem;
765 for (j = 0; j < size / 2; ++j) {
766 i = IS_LE ? 7 - j : j;
767 reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
768 }
769 break;
770 case 1:
771 /* lxvb16x */
772 bp = mem;
773 for (j = 0; j < size; ++j) {
774 i = IS_LE ? 15 - j : j;
775 reg->b[i] = *bp++;
776 }
777 break;
778 }
779 }
780 EXPORT_SYMBOL_GPL(emulate_vsx_load);
781 NOKPROBE_SYMBOL(emulate_vsx_load);
782
emulate_vsx_store(struct instruction_op * op,const union vsx_reg * reg,void * mem,bool rev)783 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
784 void *mem, bool rev)
785 {
786 int size, write_size;
787 int i, j;
788 union vsx_reg buf;
789 unsigned int *wp;
790 unsigned short *hp;
791 unsigned char *bp;
792
793 size = GETSIZE(op->type);
794
795 switch (op->element_size) {
796 case 16:
797 /* stxv, stxvx, stxvl, stxvll */
798 if (size == 0)
799 break;
800 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
801 rev = !rev;
802 if (rev) {
803 /* reverse 16 bytes */
804 buf.d[0] = byterev_8(reg->d[1]);
805 buf.d[1] = byterev_8(reg->d[0]);
806 reg = &buf;
807 }
808 memcpy(mem, reg, size);
809 break;
810 case 8:
811 /* scalar stores, stxvd2x */
812 write_size = (size >= 8) ? 8 : size;
813 i = IS_LE ? 8 : 8 - write_size;
814 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
815 buf.d[0] = buf.d[1] = 0;
816 preempt_disable();
817 conv_dp_to_sp(®->dp[IS_LE], &buf.fp[1 + IS_LE]);
818 preempt_enable();
819 reg = &buf;
820 }
821 memcpy(mem, ®->b[i], write_size);
822 if (size == 16)
823 memcpy(mem + 8, ®->d[IS_BE], 8);
824 if (unlikely(rev)) {
825 do_byte_reverse(mem, write_size);
826 if (size == 16)
827 do_byte_reverse(mem + 8, 8);
828 }
829 break;
830 case 4:
831 /* stxvw4x */
832 wp = mem;
833 for (j = 0; j < size / 4; ++j) {
834 i = IS_LE ? 3 - j : j;
835 *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
836 }
837 break;
838 case 2:
839 /* stxvh8x */
840 hp = mem;
841 for (j = 0; j < size / 2; ++j) {
842 i = IS_LE ? 7 - j : j;
843 *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
844 }
845 break;
846 case 1:
847 /* stvxb16x */
848 bp = mem;
849 for (j = 0; j < size; ++j) {
850 i = IS_LE ? 15 - j : j;
851 *bp++ = reg->b[i];
852 }
853 break;
854 }
855 }
856 EXPORT_SYMBOL_GPL(emulate_vsx_store);
857 NOKPROBE_SYMBOL(emulate_vsx_store);
858
do_vsx_load(struct instruction_op * op,unsigned long ea,struct pt_regs * regs,bool cross_endian)859 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
860 unsigned long ea, struct pt_regs *regs,
861 bool cross_endian)
862 {
863 int reg = op->reg;
864 u8 mem[16];
865 union vsx_reg buf;
866 int size = GETSIZE(op->type);
867
868 if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
869 return -EFAULT;
870
871 emulate_vsx_load(op, &buf, mem, cross_endian);
872 preempt_disable();
873 if (reg < 32) {
874 /* FP regs + extensions */
875 if (regs->msr & MSR_FP) {
876 load_vsrn(reg, &buf);
877 } else {
878 current->thread.fp_state.fpr[reg][0] = buf.d[0];
879 current->thread.fp_state.fpr[reg][1] = buf.d[1];
880 }
881 } else {
882 if (regs->msr & MSR_VEC)
883 load_vsrn(reg, &buf);
884 else
885 current->thread.vr_state.vr[reg - 32] = buf.v;
886 }
887 preempt_enable();
888 return 0;
889 }
890
do_vsx_store(struct instruction_op * op,unsigned long ea,struct pt_regs * regs,bool cross_endian)891 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
892 unsigned long ea, struct pt_regs *regs,
893 bool cross_endian)
894 {
895 int reg = op->reg;
896 u8 mem[16];
897 union vsx_reg buf;
898 int size = GETSIZE(op->type);
899
900 if (!address_ok(regs, ea, size))
901 return -EFAULT;
902
903 preempt_disable();
904 if (reg < 32) {
905 /* FP regs + extensions */
906 if (regs->msr & MSR_FP) {
907 store_vsrn(reg, &buf);
908 } else {
909 buf.d[0] = current->thread.fp_state.fpr[reg][0];
910 buf.d[1] = current->thread.fp_state.fpr[reg][1];
911 }
912 } else {
913 if (regs->msr & MSR_VEC)
914 store_vsrn(reg, &buf);
915 else
916 buf.v = current->thread.vr_state.vr[reg - 32];
917 }
918 preempt_enable();
919 emulate_vsx_store(op, &buf, mem, cross_endian);
920 return copy_mem_out(mem, ea, size, regs);
921 }
922 #endif /* CONFIG_VSX */
923
emulate_dcbz(unsigned long ea,struct pt_regs * regs)924 int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
925 {
926 int err;
927 unsigned long i, size;
928
929 #ifdef __powerpc64__
930 size = ppc64_caches.l1d.block_size;
931 if (!(regs->msr & MSR_64BIT))
932 ea &= 0xffffffffUL;
933 #else
934 size = L1_CACHE_BYTES;
935 #endif
936 ea &= ~(size - 1);
937 if (!address_ok(regs, ea, size))
938 return -EFAULT;
939 for (i = 0; i < size; i += sizeof(long)) {
940 err = __put_user(0, (unsigned long __user *) (ea + i));
941 if (err) {
942 regs->dar = ea;
943 return err;
944 }
945 }
946 return 0;
947 }
948 NOKPROBE_SYMBOL(emulate_dcbz);
949
950 #define __put_user_asmx(x, addr, err, op, cr) \
951 __asm__ __volatile__( \
952 "1: " op " %2,0,%3\n" \
953 " mfcr %1\n" \
954 "2:\n" \
955 ".section .fixup,\"ax\"\n" \
956 "3: li %0,%4\n" \
957 " b 2b\n" \
958 ".previous\n" \
959 EX_TABLE(1b, 3b) \
960 : "=r" (err), "=r" (cr) \
961 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
962
963 #define __get_user_asmx(x, addr, err, op) \
964 __asm__ __volatile__( \
965 "1: "op" %1,0,%2\n" \
966 "2:\n" \
967 ".section .fixup,\"ax\"\n" \
968 "3: li %0,%3\n" \
969 " b 2b\n" \
970 ".previous\n" \
971 EX_TABLE(1b, 3b) \
972 : "=r" (err), "=r" (x) \
973 : "r" (addr), "i" (-EFAULT), "0" (err))
974
975 #define __cacheop_user_asmx(addr, err, op) \
976 __asm__ __volatile__( \
977 "1: "op" 0,%1\n" \
978 "2:\n" \
979 ".section .fixup,\"ax\"\n" \
980 "3: li %0,%3\n" \
981 " b 2b\n" \
982 ".previous\n" \
983 EX_TABLE(1b, 3b) \
984 : "=r" (err) \
985 : "r" (addr), "i" (-EFAULT), "0" (err))
986
set_cr0(const struct pt_regs * regs,struct instruction_op * op)987 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
988 struct instruction_op *op)
989 {
990 long val = op->val;
991
992 op->type |= SETCC;
993 op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
994 #ifdef __powerpc64__
995 if (!(regs->msr & MSR_64BIT))
996 val = (int) val;
997 #endif
998 if (val < 0)
999 op->ccval |= 0x80000000;
1000 else if (val > 0)
1001 op->ccval |= 0x40000000;
1002 else
1003 op->ccval |= 0x20000000;
1004 }
1005
set_ca32(struct instruction_op * op,bool val)1006 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val)
1007 {
1008 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1009 if (val)
1010 op->xerval |= XER_CA32;
1011 else
1012 op->xerval &= ~XER_CA32;
1013 }
1014 }
1015
add_with_carry(const struct pt_regs * regs,struct instruction_op * op,int rd,unsigned long val1,unsigned long val2,unsigned long carry_in)1016 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
1017 struct instruction_op *op, int rd,
1018 unsigned long val1, unsigned long val2,
1019 unsigned long carry_in)
1020 {
1021 unsigned long val = val1 + val2;
1022
1023 if (carry_in)
1024 ++val;
1025 op->type = COMPUTE + SETREG + SETXER;
1026 op->reg = rd;
1027 op->val = val;
1028 #ifdef __powerpc64__
1029 if (!(regs->msr & MSR_64BIT)) {
1030 val = (unsigned int) val;
1031 val1 = (unsigned int) val1;
1032 }
1033 #endif
1034 op->xerval = regs->xer;
1035 if (val < val1 || (carry_in && val == val1))
1036 op->xerval |= XER_CA;
1037 else
1038 op->xerval &= ~XER_CA;
1039
1040 set_ca32(op, (unsigned int)val < (unsigned int)val1 ||
1041 (carry_in && (unsigned int)val == (unsigned int)val1));
1042 }
1043
do_cmp_signed(const struct pt_regs * regs,struct instruction_op * op,long v1,long v2,int crfld)1044 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
1045 struct instruction_op *op,
1046 long v1, long v2, int crfld)
1047 {
1048 unsigned int crval, shift;
1049
1050 op->type = COMPUTE + SETCC;
1051 crval = (regs->xer >> 31) & 1; /* get SO bit */
1052 if (v1 < v2)
1053 crval |= 8;
1054 else if (v1 > v2)
1055 crval |= 4;
1056 else
1057 crval |= 2;
1058 shift = (7 - crfld) * 4;
1059 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1060 }
1061
do_cmp_unsigned(const struct pt_regs * regs,struct instruction_op * op,unsigned long v1,unsigned long v2,int crfld)1062 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
1063 struct instruction_op *op,
1064 unsigned long v1,
1065 unsigned long v2, int crfld)
1066 {
1067 unsigned int crval, shift;
1068
1069 op->type = COMPUTE + SETCC;
1070 crval = (regs->xer >> 31) & 1; /* get SO bit */
1071 if (v1 < v2)
1072 crval |= 8;
1073 else if (v1 > v2)
1074 crval |= 4;
1075 else
1076 crval |= 2;
1077 shift = (7 - crfld) * 4;
1078 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1079 }
1080
do_cmpb(const struct pt_regs * regs,struct instruction_op * op,unsigned long v1,unsigned long v2)1081 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
1082 struct instruction_op *op,
1083 unsigned long v1, unsigned long v2)
1084 {
1085 unsigned long long out_val, mask;
1086 int i;
1087
1088 out_val = 0;
1089 for (i = 0; i < 8; i++) {
1090 mask = 0xffUL << (i * 8);
1091 if ((v1 & mask) == (v2 & mask))
1092 out_val |= mask;
1093 }
1094 op->val = out_val;
1095 }
1096
1097 /*
1098 * The size parameter is used to adjust the equivalent popcnt instruction.
1099 * popcntb = 8, popcntw = 32, popcntd = 64
1100 */
do_popcnt(const struct pt_regs * regs,struct instruction_op * op,unsigned long v1,int size)1101 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
1102 struct instruction_op *op,
1103 unsigned long v1, int size)
1104 {
1105 unsigned long long out = v1;
1106
1107 out -= (out >> 1) & 0x5555555555555555ULL;
1108 out = (0x3333333333333333ULL & out) +
1109 (0x3333333333333333ULL & (out >> 2));
1110 out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1111
1112 if (size == 8) { /* popcntb */
1113 op->val = out;
1114 return;
1115 }
1116 out += out >> 8;
1117 out += out >> 16;
1118 if (size == 32) { /* popcntw */
1119 op->val = out & 0x0000003f0000003fULL;
1120 return;
1121 }
1122
1123 out = (out + (out >> 32)) & 0x7f;
1124 op->val = out; /* popcntd */
1125 }
1126
1127 #ifdef CONFIG_PPC64
do_bpermd(const struct pt_regs * regs,struct instruction_op * op,unsigned long v1,unsigned long v2)1128 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
1129 struct instruction_op *op,
1130 unsigned long v1, unsigned long v2)
1131 {
1132 unsigned char perm, idx;
1133 unsigned int i;
1134
1135 perm = 0;
1136 for (i = 0; i < 8; i++) {
1137 idx = (v1 >> (i * 8)) & 0xff;
1138 if (idx < 64)
1139 if (v2 & PPC_BIT(idx))
1140 perm |= 1 << i;
1141 }
1142 op->val = perm;
1143 }
1144 #endif /* CONFIG_PPC64 */
1145 /*
1146 * The size parameter adjusts the equivalent prty instruction.
1147 * prtyw = 32, prtyd = 64
1148 */
do_prty(const struct pt_regs * regs,struct instruction_op * op,unsigned long v,int size)1149 static nokprobe_inline void do_prty(const struct pt_regs *regs,
1150 struct instruction_op *op,
1151 unsigned long v, int size)
1152 {
1153 unsigned long long res = v ^ (v >> 8);
1154
1155 res ^= res >> 16;
1156 if (size == 32) { /* prtyw */
1157 op->val = res & 0x0000000100000001ULL;
1158 return;
1159 }
1160
1161 res ^= res >> 32;
1162 op->val = res & 1; /*prtyd */
1163 }
1164
trap_compare(long v1,long v2)1165 static nokprobe_inline int trap_compare(long v1, long v2)
1166 {
1167 int ret = 0;
1168
1169 if (v1 < v2)
1170 ret |= 0x10;
1171 else if (v1 > v2)
1172 ret |= 0x08;
1173 else
1174 ret |= 0x04;
1175 if ((unsigned long)v1 < (unsigned long)v2)
1176 ret |= 0x02;
1177 else if ((unsigned long)v1 > (unsigned long)v2)
1178 ret |= 0x01;
1179 return ret;
1180 }
1181
1182 /*
1183 * Elements of 32-bit rotate and mask instructions.
1184 */
1185 #define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \
1186 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1187 #ifdef __powerpc64__
1188 #define MASK64_L(mb) (~0UL >> (mb))
1189 #define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me))
1190 #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
1191 #define DATA32(x) (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
1192 #else
1193 #define DATA32(x) (x)
1194 #endif
1195 #define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1196
1197 /*
1198 * Decode an instruction, and return information about it in *op
1199 * without changing *regs.
1200 * Integer arithmetic and logical instructions, branches, and barrier
1201 * instructions can be emulated just using the information in *op.
1202 *
1203 * Return value is 1 if the instruction can be emulated just by
1204 * updating *regs with the information in *op, -1 if we need the
1205 * GPRs but *regs doesn't contain the full register set, or 0
1206 * otherwise.
1207 */
analyse_instr(struct instruction_op * op,const struct pt_regs * regs,struct ppc_inst instr)1208 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1209 struct ppc_inst instr)
1210 {
1211 #ifdef CONFIG_PPC64
1212 unsigned int suffixopcode, prefixtype, prefix_r;
1213 #endif
1214 unsigned int opcode, ra, rb, rc, rd, spr, u;
1215 unsigned long int imm;
1216 unsigned long int val, val2;
1217 unsigned int mb, me, sh;
1218 unsigned int word, suffix;
1219 long ival;
1220
1221 word = ppc_inst_val(instr);
1222 suffix = ppc_inst_suffix(instr);
1223
1224 op->type = COMPUTE;
1225
1226 opcode = ppc_inst_primary_opcode(instr);
1227 switch (opcode) {
1228 case 16: /* bc */
1229 op->type = BRANCH;
1230 imm = (signed short)(word & 0xfffc);
1231 if ((word & 2) == 0)
1232 imm += regs->nip;
1233 op->val = truncate_if_32bit(regs->msr, imm);
1234 if (word & 1)
1235 op->type |= SETLK;
1236 if (branch_taken(word, regs, op))
1237 op->type |= BRTAKEN;
1238 return 1;
1239 #ifdef CONFIG_PPC64
1240 case 17: /* sc */
1241 if ((word & 0xfe2) == 2)
1242 op->type = SYSCALL;
1243 else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) &&
1244 (word & 0xfe3) == 1) { /* scv */
1245 op->type = SYSCALL_VECTORED_0;
1246 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1247 goto unknown_opcode;
1248 } else
1249 op->type = UNKNOWN;
1250 return 0;
1251 #endif
1252 case 18: /* b */
1253 op->type = BRANCH | BRTAKEN;
1254 imm = word & 0x03fffffc;
1255 if (imm & 0x02000000)
1256 imm -= 0x04000000;
1257 if ((word & 2) == 0)
1258 imm += regs->nip;
1259 op->val = truncate_if_32bit(regs->msr, imm);
1260 if (word & 1)
1261 op->type |= SETLK;
1262 return 1;
1263 case 19:
1264 switch ((word >> 1) & 0x3ff) {
1265 case 0: /* mcrf */
1266 op->type = COMPUTE + SETCC;
1267 rd = 7 - ((word >> 23) & 0x7);
1268 ra = 7 - ((word >> 18) & 0x7);
1269 rd *= 4;
1270 ra *= 4;
1271 val = (regs->ccr >> ra) & 0xf;
1272 op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1273 return 1;
1274
1275 case 16: /* bclr */
1276 case 528: /* bcctr */
1277 op->type = BRANCH;
1278 imm = (word & 0x400)? regs->ctr: regs->link;
1279 op->val = truncate_if_32bit(regs->msr, imm);
1280 if (word & 1)
1281 op->type |= SETLK;
1282 if (branch_taken(word, regs, op))
1283 op->type |= BRTAKEN;
1284 return 1;
1285
1286 case 18: /* rfid, scary */
1287 if (regs->msr & MSR_PR)
1288 goto priv;
1289 op->type = RFI;
1290 return 0;
1291
1292 case 150: /* isync */
1293 op->type = BARRIER | BARRIER_ISYNC;
1294 return 1;
1295
1296 case 33: /* crnor */
1297 case 129: /* crandc */
1298 case 193: /* crxor */
1299 case 225: /* crnand */
1300 case 257: /* crand */
1301 case 289: /* creqv */
1302 case 417: /* crorc */
1303 case 449: /* cror */
1304 op->type = COMPUTE + SETCC;
1305 ra = (word >> 16) & 0x1f;
1306 rb = (word >> 11) & 0x1f;
1307 rd = (word >> 21) & 0x1f;
1308 ra = (regs->ccr >> (31 - ra)) & 1;
1309 rb = (regs->ccr >> (31 - rb)) & 1;
1310 val = (word >> (6 + ra * 2 + rb)) & 1;
1311 op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1312 (val << (31 - rd));
1313 return 1;
1314 }
1315 break;
1316 case 31:
1317 switch ((word >> 1) & 0x3ff) {
1318 case 598: /* sync */
1319 op->type = BARRIER + BARRIER_SYNC;
1320 #ifdef __powerpc64__
1321 switch ((word >> 21) & 3) {
1322 case 1: /* lwsync */
1323 op->type = BARRIER + BARRIER_LWSYNC;
1324 break;
1325 case 2: /* ptesync */
1326 op->type = BARRIER + BARRIER_PTESYNC;
1327 break;
1328 }
1329 #endif
1330 return 1;
1331
1332 case 854: /* eieio */
1333 op->type = BARRIER + BARRIER_EIEIO;
1334 return 1;
1335 }
1336 break;
1337 }
1338
1339 /* Following cases refer to regs->gpr[], so we need all regs */
1340 if (!FULL_REGS(regs))
1341 return -1;
1342
1343 rd = (word >> 21) & 0x1f;
1344 ra = (word >> 16) & 0x1f;
1345 rb = (word >> 11) & 0x1f;
1346 rc = (word >> 6) & 0x1f;
1347
1348 switch (opcode) {
1349 #ifdef __powerpc64__
1350 case 1:
1351 if (!cpu_has_feature(CPU_FTR_ARCH_31))
1352 goto unknown_opcode;
1353
1354 prefix_r = GET_PREFIX_R(word);
1355 ra = GET_PREFIX_RA(suffix);
1356 rd = (suffix >> 21) & 0x1f;
1357 op->reg = rd;
1358 op->val = regs->gpr[rd];
1359 suffixopcode = get_op(suffix);
1360 prefixtype = (word >> 24) & 0x3;
1361 switch (prefixtype) {
1362 case 2:
1363 if (prefix_r && ra)
1364 return 0;
1365 switch (suffixopcode) {
1366 case 14: /* paddi */
1367 op->type = COMPUTE | PREFIXED;
1368 op->val = mlsd_8lsd_ea(word, suffix, regs);
1369 goto compute_done;
1370 }
1371 }
1372 break;
1373 case 2: /* tdi */
1374 if (rd & trap_compare(regs->gpr[ra], (short) word))
1375 goto trap;
1376 return 1;
1377 #endif
1378 case 3: /* twi */
1379 if (rd & trap_compare((int)regs->gpr[ra], (short) word))
1380 goto trap;
1381 return 1;
1382
1383 #ifdef __powerpc64__
1384 case 4:
1385 /*
1386 * There are very many instructions with this primary opcode
1387 * introduced in the ISA as early as v2.03. However, the ones
1388 * we currently emulate were all introduced with ISA 3.0
1389 */
1390 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1391 goto unknown_opcode;
1392
1393 switch (word & 0x3f) {
1394 case 48: /* maddhd */
1395 asm volatile(PPC_MADDHD(%0, %1, %2, %3) :
1396 "=r" (op->val) : "r" (regs->gpr[ra]),
1397 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1398 goto compute_done;
1399
1400 case 49: /* maddhdu */
1401 asm volatile(PPC_MADDHDU(%0, %1, %2, %3) :
1402 "=r" (op->val) : "r" (regs->gpr[ra]),
1403 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1404 goto compute_done;
1405
1406 case 51: /* maddld */
1407 asm volatile(PPC_MADDLD(%0, %1, %2, %3) :
1408 "=r" (op->val) : "r" (regs->gpr[ra]),
1409 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1410 goto compute_done;
1411 }
1412
1413 /*
1414 * There are other instructions from ISA 3.0 with the same
1415 * primary opcode which do not have emulation support yet.
1416 */
1417 goto unknown_opcode;
1418 #endif
1419
1420 case 7: /* mulli */
1421 op->val = regs->gpr[ra] * (short) word;
1422 goto compute_done;
1423
1424 case 8: /* subfic */
1425 imm = (short) word;
1426 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1427 return 1;
1428
1429 case 10: /* cmpli */
1430 imm = (unsigned short) word;
1431 val = regs->gpr[ra];
1432 #ifdef __powerpc64__
1433 if ((rd & 1) == 0)
1434 val = (unsigned int) val;
1435 #endif
1436 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1437 return 1;
1438
1439 case 11: /* cmpi */
1440 imm = (short) word;
1441 val = regs->gpr[ra];
1442 #ifdef __powerpc64__
1443 if ((rd & 1) == 0)
1444 val = (int) val;
1445 #endif
1446 do_cmp_signed(regs, op, val, imm, rd >> 2);
1447 return 1;
1448
1449 case 12: /* addic */
1450 imm = (short) word;
1451 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1452 return 1;
1453
1454 case 13: /* addic. */
1455 imm = (short) word;
1456 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1457 set_cr0(regs, op);
1458 return 1;
1459
1460 case 14: /* addi */
1461 imm = (short) word;
1462 if (ra)
1463 imm += regs->gpr[ra];
1464 op->val = imm;
1465 goto compute_done;
1466
1467 case 15: /* addis */
1468 imm = ((short) word) << 16;
1469 if (ra)
1470 imm += regs->gpr[ra];
1471 op->val = imm;
1472 goto compute_done;
1473
1474 case 19:
1475 if (((word >> 1) & 0x1f) == 2) {
1476 /* addpcis */
1477 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1478 goto unknown_opcode;
1479 imm = (short) (word & 0xffc1); /* d0 + d2 fields */
1480 imm |= (word >> 15) & 0x3e; /* d1 field */
1481 op->val = regs->nip + (imm << 16) + 4;
1482 goto compute_done;
1483 }
1484 op->type = UNKNOWN;
1485 return 0;
1486
1487 case 20: /* rlwimi */
1488 mb = (word >> 6) & 0x1f;
1489 me = (word >> 1) & 0x1f;
1490 val = DATA32(regs->gpr[rd]);
1491 imm = MASK32(mb, me);
1492 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1493 goto logical_done;
1494
1495 case 21: /* rlwinm */
1496 mb = (word >> 6) & 0x1f;
1497 me = (word >> 1) & 0x1f;
1498 val = DATA32(regs->gpr[rd]);
1499 op->val = ROTATE(val, rb) & MASK32(mb, me);
1500 goto logical_done;
1501
1502 case 23: /* rlwnm */
1503 mb = (word >> 6) & 0x1f;
1504 me = (word >> 1) & 0x1f;
1505 rb = regs->gpr[rb] & 0x1f;
1506 val = DATA32(regs->gpr[rd]);
1507 op->val = ROTATE(val, rb) & MASK32(mb, me);
1508 goto logical_done;
1509
1510 case 24: /* ori */
1511 op->val = regs->gpr[rd] | (unsigned short) word;
1512 goto logical_done_nocc;
1513
1514 case 25: /* oris */
1515 imm = (unsigned short) word;
1516 op->val = regs->gpr[rd] | (imm << 16);
1517 goto logical_done_nocc;
1518
1519 case 26: /* xori */
1520 op->val = regs->gpr[rd] ^ (unsigned short) word;
1521 goto logical_done_nocc;
1522
1523 case 27: /* xoris */
1524 imm = (unsigned short) word;
1525 op->val = regs->gpr[rd] ^ (imm << 16);
1526 goto logical_done_nocc;
1527
1528 case 28: /* andi. */
1529 op->val = regs->gpr[rd] & (unsigned short) word;
1530 set_cr0(regs, op);
1531 goto logical_done_nocc;
1532
1533 case 29: /* andis. */
1534 imm = (unsigned short) word;
1535 op->val = regs->gpr[rd] & (imm << 16);
1536 set_cr0(regs, op);
1537 goto logical_done_nocc;
1538
1539 #ifdef __powerpc64__
1540 case 30: /* rld* */
1541 mb = ((word >> 6) & 0x1f) | (word & 0x20);
1542 val = regs->gpr[rd];
1543 if ((word & 0x10) == 0) {
1544 sh = rb | ((word & 2) << 4);
1545 val = ROTATE(val, sh);
1546 switch ((word >> 2) & 3) {
1547 case 0: /* rldicl */
1548 val &= MASK64_L(mb);
1549 break;
1550 case 1: /* rldicr */
1551 val &= MASK64_R(mb);
1552 break;
1553 case 2: /* rldic */
1554 val &= MASK64(mb, 63 - sh);
1555 break;
1556 case 3: /* rldimi */
1557 imm = MASK64(mb, 63 - sh);
1558 val = (regs->gpr[ra] & ~imm) |
1559 (val & imm);
1560 }
1561 op->val = val;
1562 goto logical_done;
1563 } else {
1564 sh = regs->gpr[rb] & 0x3f;
1565 val = ROTATE(val, sh);
1566 switch ((word >> 1) & 7) {
1567 case 0: /* rldcl */
1568 op->val = val & MASK64_L(mb);
1569 goto logical_done;
1570 case 1: /* rldcr */
1571 op->val = val & MASK64_R(mb);
1572 goto logical_done;
1573 }
1574 }
1575 #endif
1576 op->type = UNKNOWN; /* illegal instruction */
1577 return 0;
1578
1579 case 31:
1580 /* isel occupies 32 minor opcodes */
1581 if (((word >> 1) & 0x1f) == 15) {
1582 mb = (word >> 6) & 0x1f; /* bc field */
1583 val = (regs->ccr >> (31 - mb)) & 1;
1584 val2 = (ra) ? regs->gpr[ra] : 0;
1585
1586 op->val = (val) ? val2 : regs->gpr[rb];
1587 goto compute_done;
1588 }
1589
1590 switch ((word >> 1) & 0x3ff) {
1591 case 4: /* tw */
1592 if (rd == 0x1f ||
1593 (rd & trap_compare((int)regs->gpr[ra],
1594 (int)regs->gpr[rb])))
1595 goto trap;
1596 return 1;
1597 #ifdef __powerpc64__
1598 case 68: /* td */
1599 if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1600 goto trap;
1601 return 1;
1602 #endif
1603 case 83: /* mfmsr */
1604 if (regs->msr & MSR_PR)
1605 goto priv;
1606 op->type = MFMSR;
1607 op->reg = rd;
1608 return 0;
1609 case 146: /* mtmsr */
1610 if (regs->msr & MSR_PR)
1611 goto priv;
1612 op->type = MTMSR;
1613 op->reg = rd;
1614 op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1615 return 0;
1616 #ifdef CONFIG_PPC64
1617 case 178: /* mtmsrd */
1618 if (regs->msr & MSR_PR)
1619 goto priv;
1620 op->type = MTMSR;
1621 op->reg = rd;
1622 /* only MSR_EE and MSR_RI get changed if bit 15 set */
1623 /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1624 imm = (word & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1625 op->val = imm;
1626 return 0;
1627 #endif
1628
1629 case 19: /* mfcr */
1630 imm = 0xffffffffUL;
1631 if ((word >> 20) & 1) {
1632 imm = 0xf0000000UL;
1633 for (sh = 0; sh < 8; ++sh) {
1634 if (word & (0x80000 >> sh))
1635 break;
1636 imm >>= 4;
1637 }
1638 }
1639 op->val = regs->ccr & imm;
1640 goto compute_done;
1641
1642 case 144: /* mtcrf */
1643 op->type = COMPUTE + SETCC;
1644 imm = 0xf0000000UL;
1645 val = regs->gpr[rd];
1646 op->ccval = regs->ccr;
1647 for (sh = 0; sh < 8; ++sh) {
1648 if (word & (0x80000 >> sh))
1649 op->ccval = (op->ccval & ~imm) |
1650 (val & imm);
1651 imm >>= 4;
1652 }
1653 return 1;
1654
1655 case 339: /* mfspr */
1656 spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1657 op->type = MFSPR;
1658 op->reg = rd;
1659 op->spr = spr;
1660 if (spr == SPRN_XER || spr == SPRN_LR ||
1661 spr == SPRN_CTR)
1662 return 1;
1663 return 0;
1664
1665 case 467: /* mtspr */
1666 spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1667 op->type = MTSPR;
1668 op->val = regs->gpr[rd];
1669 op->spr = spr;
1670 if (spr == SPRN_XER || spr == SPRN_LR ||
1671 spr == SPRN_CTR)
1672 return 1;
1673 return 0;
1674
1675 /*
1676 * Compare instructions
1677 */
1678 case 0: /* cmp */
1679 val = regs->gpr[ra];
1680 val2 = regs->gpr[rb];
1681 #ifdef __powerpc64__
1682 if ((rd & 1) == 0) {
1683 /* word (32-bit) compare */
1684 val = (int) val;
1685 val2 = (int) val2;
1686 }
1687 #endif
1688 do_cmp_signed(regs, op, val, val2, rd >> 2);
1689 return 1;
1690
1691 case 32: /* cmpl */
1692 val = regs->gpr[ra];
1693 val2 = regs->gpr[rb];
1694 #ifdef __powerpc64__
1695 if ((rd & 1) == 0) {
1696 /* word (32-bit) compare */
1697 val = (unsigned int) val;
1698 val2 = (unsigned int) val2;
1699 }
1700 #endif
1701 do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1702 return 1;
1703
1704 case 508: /* cmpb */
1705 do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1706 goto logical_done_nocc;
1707
1708 /*
1709 * Arithmetic instructions
1710 */
1711 case 8: /* subfc */
1712 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1713 regs->gpr[rb], 1);
1714 goto arith_done;
1715 #ifdef __powerpc64__
1716 case 9: /* mulhdu */
1717 asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1718 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1719 goto arith_done;
1720 #endif
1721 case 10: /* addc */
1722 add_with_carry(regs, op, rd, regs->gpr[ra],
1723 regs->gpr[rb], 0);
1724 goto arith_done;
1725
1726 case 11: /* mulhwu */
1727 asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1728 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1729 goto arith_done;
1730
1731 case 40: /* subf */
1732 op->val = regs->gpr[rb] - regs->gpr[ra];
1733 goto arith_done;
1734 #ifdef __powerpc64__
1735 case 73: /* mulhd */
1736 asm("mulhd %0,%1,%2" : "=r" (op->val) :
1737 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1738 goto arith_done;
1739 #endif
1740 case 75: /* mulhw */
1741 asm("mulhw %0,%1,%2" : "=r" (op->val) :
1742 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1743 goto arith_done;
1744
1745 case 104: /* neg */
1746 op->val = -regs->gpr[ra];
1747 goto arith_done;
1748
1749 case 136: /* subfe */
1750 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1751 regs->gpr[rb], regs->xer & XER_CA);
1752 goto arith_done;
1753
1754 case 138: /* adde */
1755 add_with_carry(regs, op, rd, regs->gpr[ra],
1756 regs->gpr[rb], regs->xer & XER_CA);
1757 goto arith_done;
1758
1759 case 200: /* subfze */
1760 add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1761 regs->xer & XER_CA);
1762 goto arith_done;
1763
1764 case 202: /* addze */
1765 add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1766 regs->xer & XER_CA);
1767 goto arith_done;
1768
1769 case 232: /* subfme */
1770 add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1771 regs->xer & XER_CA);
1772 goto arith_done;
1773 #ifdef __powerpc64__
1774 case 233: /* mulld */
1775 op->val = regs->gpr[ra] * regs->gpr[rb];
1776 goto arith_done;
1777 #endif
1778 case 234: /* addme */
1779 add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1780 regs->xer & XER_CA);
1781 goto arith_done;
1782
1783 case 235: /* mullw */
1784 op->val = (long)(int) regs->gpr[ra] *
1785 (int) regs->gpr[rb];
1786
1787 goto arith_done;
1788 #ifdef __powerpc64__
1789 case 265: /* modud */
1790 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1791 goto unknown_opcode;
1792 op->val = regs->gpr[ra] % regs->gpr[rb];
1793 goto compute_done;
1794 #endif
1795 case 266: /* add */
1796 op->val = regs->gpr[ra] + regs->gpr[rb];
1797 goto arith_done;
1798
1799 case 267: /* moduw */
1800 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1801 goto unknown_opcode;
1802 op->val = (unsigned int) regs->gpr[ra] %
1803 (unsigned int) regs->gpr[rb];
1804 goto compute_done;
1805 #ifdef __powerpc64__
1806 case 457: /* divdu */
1807 op->val = regs->gpr[ra] / regs->gpr[rb];
1808 goto arith_done;
1809 #endif
1810 case 459: /* divwu */
1811 op->val = (unsigned int) regs->gpr[ra] /
1812 (unsigned int) regs->gpr[rb];
1813 goto arith_done;
1814 #ifdef __powerpc64__
1815 case 489: /* divd */
1816 op->val = (long int) regs->gpr[ra] /
1817 (long int) regs->gpr[rb];
1818 goto arith_done;
1819 #endif
1820 case 491: /* divw */
1821 op->val = (int) regs->gpr[ra] /
1822 (int) regs->gpr[rb];
1823 goto arith_done;
1824 #ifdef __powerpc64__
1825 case 425: /* divde[.] */
1826 asm volatile(PPC_DIVDE(%0, %1, %2) :
1827 "=r" (op->val) : "r" (regs->gpr[ra]),
1828 "r" (regs->gpr[rb]));
1829 goto arith_done;
1830 case 393: /* divdeu[.] */
1831 asm volatile(PPC_DIVDEU(%0, %1, %2) :
1832 "=r" (op->val) : "r" (regs->gpr[ra]),
1833 "r" (regs->gpr[rb]));
1834 goto arith_done;
1835 #endif
1836 case 755: /* darn */
1837 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1838 goto unknown_opcode;
1839 switch (ra & 0x3) {
1840 case 0:
1841 /* 32-bit conditioned */
1842 asm volatile(PPC_DARN(%0, 0) : "=r" (op->val));
1843 goto compute_done;
1844
1845 case 1:
1846 /* 64-bit conditioned */
1847 asm volatile(PPC_DARN(%0, 1) : "=r" (op->val));
1848 goto compute_done;
1849
1850 case 2:
1851 /* 64-bit raw */
1852 asm volatile(PPC_DARN(%0, 2) : "=r" (op->val));
1853 goto compute_done;
1854 }
1855
1856 goto unknown_opcode;
1857 #ifdef __powerpc64__
1858 case 777: /* modsd */
1859 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1860 goto unknown_opcode;
1861 op->val = (long int) regs->gpr[ra] %
1862 (long int) regs->gpr[rb];
1863 goto compute_done;
1864 #endif
1865 case 779: /* modsw */
1866 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1867 goto unknown_opcode;
1868 op->val = (int) regs->gpr[ra] %
1869 (int) regs->gpr[rb];
1870 goto compute_done;
1871
1872
1873 /*
1874 * Logical instructions
1875 */
1876 case 26: /* cntlzw */
1877 val = (unsigned int) regs->gpr[rd];
1878 op->val = ( val ? __builtin_clz(val) : 32 );
1879 goto logical_done;
1880 #ifdef __powerpc64__
1881 case 58: /* cntlzd */
1882 val = regs->gpr[rd];
1883 op->val = ( val ? __builtin_clzl(val) : 64 );
1884 goto logical_done;
1885 #endif
1886 case 28: /* and */
1887 op->val = regs->gpr[rd] & regs->gpr[rb];
1888 goto logical_done;
1889
1890 case 60: /* andc */
1891 op->val = regs->gpr[rd] & ~regs->gpr[rb];
1892 goto logical_done;
1893
1894 case 122: /* popcntb */
1895 do_popcnt(regs, op, regs->gpr[rd], 8);
1896 goto logical_done_nocc;
1897
1898 case 124: /* nor */
1899 op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
1900 goto logical_done;
1901
1902 case 154: /* prtyw */
1903 do_prty(regs, op, regs->gpr[rd], 32);
1904 goto logical_done_nocc;
1905
1906 case 186: /* prtyd */
1907 do_prty(regs, op, regs->gpr[rd], 64);
1908 goto logical_done_nocc;
1909 #ifdef CONFIG_PPC64
1910 case 252: /* bpermd */
1911 do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
1912 goto logical_done_nocc;
1913 #endif
1914 case 284: /* xor */
1915 op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
1916 goto logical_done;
1917
1918 case 316: /* xor */
1919 op->val = regs->gpr[rd] ^ regs->gpr[rb];
1920 goto logical_done;
1921
1922 case 378: /* popcntw */
1923 do_popcnt(regs, op, regs->gpr[rd], 32);
1924 goto logical_done_nocc;
1925
1926 case 412: /* orc */
1927 op->val = regs->gpr[rd] | ~regs->gpr[rb];
1928 goto logical_done;
1929
1930 case 444: /* or */
1931 op->val = regs->gpr[rd] | regs->gpr[rb];
1932 goto logical_done;
1933
1934 case 476: /* nand */
1935 op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
1936 goto logical_done;
1937 #ifdef CONFIG_PPC64
1938 case 506: /* popcntd */
1939 do_popcnt(regs, op, regs->gpr[rd], 64);
1940 goto logical_done_nocc;
1941 #endif
1942 case 538: /* cnttzw */
1943 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1944 goto unknown_opcode;
1945 val = (unsigned int) regs->gpr[rd];
1946 op->val = (val ? __builtin_ctz(val) : 32);
1947 goto logical_done;
1948 #ifdef __powerpc64__
1949 case 570: /* cnttzd */
1950 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1951 goto unknown_opcode;
1952 val = regs->gpr[rd];
1953 op->val = (val ? __builtin_ctzl(val) : 64);
1954 goto logical_done;
1955 #endif
1956 case 922: /* extsh */
1957 op->val = (signed short) regs->gpr[rd];
1958 goto logical_done;
1959
1960 case 954: /* extsb */
1961 op->val = (signed char) regs->gpr[rd];
1962 goto logical_done;
1963 #ifdef __powerpc64__
1964 case 986: /* extsw */
1965 op->val = (signed int) regs->gpr[rd];
1966 goto logical_done;
1967 #endif
1968
1969 /*
1970 * Shift instructions
1971 */
1972 case 24: /* slw */
1973 sh = regs->gpr[rb] & 0x3f;
1974 if (sh < 32)
1975 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
1976 else
1977 op->val = 0;
1978 goto logical_done;
1979
1980 case 536: /* srw */
1981 sh = regs->gpr[rb] & 0x3f;
1982 if (sh < 32)
1983 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
1984 else
1985 op->val = 0;
1986 goto logical_done;
1987
1988 case 792: /* sraw */
1989 op->type = COMPUTE + SETREG + SETXER;
1990 sh = regs->gpr[rb] & 0x3f;
1991 ival = (signed int) regs->gpr[rd];
1992 op->val = ival >> (sh < 32 ? sh : 31);
1993 op->xerval = regs->xer;
1994 if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
1995 op->xerval |= XER_CA;
1996 else
1997 op->xerval &= ~XER_CA;
1998 set_ca32(op, op->xerval & XER_CA);
1999 goto logical_done;
2000
2001 case 824: /* srawi */
2002 op->type = COMPUTE + SETREG + SETXER;
2003 sh = rb;
2004 ival = (signed int) regs->gpr[rd];
2005 op->val = ival >> sh;
2006 op->xerval = regs->xer;
2007 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2008 op->xerval |= XER_CA;
2009 else
2010 op->xerval &= ~XER_CA;
2011 set_ca32(op, op->xerval & XER_CA);
2012 goto logical_done;
2013
2014 #ifdef __powerpc64__
2015 case 27: /* sld */
2016 sh = regs->gpr[rb] & 0x7f;
2017 if (sh < 64)
2018 op->val = regs->gpr[rd] << sh;
2019 else
2020 op->val = 0;
2021 goto logical_done;
2022
2023 case 539: /* srd */
2024 sh = regs->gpr[rb] & 0x7f;
2025 if (sh < 64)
2026 op->val = regs->gpr[rd] >> sh;
2027 else
2028 op->val = 0;
2029 goto logical_done;
2030
2031 case 794: /* srad */
2032 op->type = COMPUTE + SETREG + SETXER;
2033 sh = regs->gpr[rb] & 0x7f;
2034 ival = (signed long int) regs->gpr[rd];
2035 op->val = ival >> (sh < 64 ? sh : 63);
2036 op->xerval = regs->xer;
2037 if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
2038 op->xerval |= XER_CA;
2039 else
2040 op->xerval &= ~XER_CA;
2041 set_ca32(op, op->xerval & XER_CA);
2042 goto logical_done;
2043
2044 case 826: /* sradi with sh_5 = 0 */
2045 case 827: /* sradi with sh_5 = 1 */
2046 op->type = COMPUTE + SETREG + SETXER;
2047 sh = rb | ((word & 2) << 4);
2048 ival = (signed long int) regs->gpr[rd];
2049 op->val = ival >> sh;
2050 op->xerval = regs->xer;
2051 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2052 op->xerval |= XER_CA;
2053 else
2054 op->xerval &= ~XER_CA;
2055 set_ca32(op, op->xerval & XER_CA);
2056 goto logical_done;
2057
2058 case 890: /* extswsli with sh_5 = 0 */
2059 case 891: /* extswsli with sh_5 = 1 */
2060 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2061 goto unknown_opcode;
2062 op->type = COMPUTE + SETREG;
2063 sh = rb | ((word & 2) << 4);
2064 val = (signed int) regs->gpr[rd];
2065 if (sh)
2066 op->val = ROTATE(val, sh) & MASK64(0, 63 - sh);
2067 else
2068 op->val = val;
2069 goto logical_done;
2070
2071 #endif /* __powerpc64__ */
2072
2073 /*
2074 * Cache instructions
2075 */
2076 case 54: /* dcbst */
2077 op->type = MKOP(CACHEOP, DCBST, 0);
2078 op->ea = xform_ea(word, regs);
2079 return 0;
2080
2081 case 86: /* dcbf */
2082 op->type = MKOP(CACHEOP, DCBF, 0);
2083 op->ea = xform_ea(word, regs);
2084 return 0;
2085
2086 case 246: /* dcbtst */
2087 op->type = MKOP(CACHEOP, DCBTST, 0);
2088 op->ea = xform_ea(word, regs);
2089 op->reg = rd;
2090 return 0;
2091
2092 case 278: /* dcbt */
2093 op->type = MKOP(CACHEOP, DCBTST, 0);
2094 op->ea = xform_ea(word, regs);
2095 op->reg = rd;
2096 return 0;
2097
2098 case 982: /* icbi */
2099 op->type = MKOP(CACHEOP, ICBI, 0);
2100 op->ea = xform_ea(word, regs);
2101 return 0;
2102
2103 case 1014: /* dcbz */
2104 op->type = MKOP(CACHEOP, DCBZ, 0);
2105 op->ea = xform_ea(word, regs);
2106 return 0;
2107 }
2108 break;
2109 }
2110
2111 /*
2112 * Loads and stores.
2113 */
2114 op->type = UNKNOWN;
2115 op->update_reg = ra;
2116 op->reg = rd;
2117 op->val = regs->gpr[rd];
2118 u = (word >> 20) & UPDATE;
2119 op->vsx_flags = 0;
2120
2121 switch (opcode) {
2122 case 31:
2123 u = word & UPDATE;
2124 op->ea = xform_ea(word, regs);
2125 switch ((word >> 1) & 0x3ff) {
2126 case 20: /* lwarx */
2127 op->type = MKOP(LARX, 0, 4);
2128 break;
2129
2130 case 150: /* stwcx. */
2131 op->type = MKOP(STCX, 0, 4);
2132 break;
2133
2134 #ifdef __powerpc64__
2135 case 84: /* ldarx */
2136 op->type = MKOP(LARX, 0, 8);
2137 break;
2138
2139 case 214: /* stdcx. */
2140 op->type = MKOP(STCX, 0, 8);
2141 break;
2142
2143 case 52: /* lbarx */
2144 op->type = MKOP(LARX, 0, 1);
2145 break;
2146
2147 case 694: /* stbcx. */
2148 op->type = MKOP(STCX, 0, 1);
2149 break;
2150
2151 case 116: /* lharx */
2152 op->type = MKOP(LARX, 0, 2);
2153 break;
2154
2155 case 726: /* sthcx. */
2156 op->type = MKOP(STCX, 0, 2);
2157 break;
2158
2159 case 276: /* lqarx */
2160 if (!((rd & 1) || rd == ra || rd == rb))
2161 op->type = MKOP(LARX, 0, 16);
2162 break;
2163
2164 case 182: /* stqcx. */
2165 if (!(rd & 1))
2166 op->type = MKOP(STCX, 0, 16);
2167 break;
2168 #endif
2169
2170 case 23: /* lwzx */
2171 case 55: /* lwzux */
2172 op->type = MKOP(LOAD, u, 4);
2173 break;
2174
2175 case 87: /* lbzx */
2176 case 119: /* lbzux */
2177 op->type = MKOP(LOAD, u, 1);
2178 break;
2179
2180 #ifdef CONFIG_ALTIVEC
2181 /*
2182 * Note: for the load/store vector element instructions,
2183 * bits of the EA say which field of the VMX register to use.
2184 */
2185 case 7: /* lvebx */
2186 op->type = MKOP(LOAD_VMX, 0, 1);
2187 op->element_size = 1;
2188 break;
2189
2190 case 39: /* lvehx */
2191 op->type = MKOP(LOAD_VMX, 0, 2);
2192 op->element_size = 2;
2193 break;
2194
2195 case 71: /* lvewx */
2196 op->type = MKOP(LOAD_VMX, 0, 4);
2197 op->element_size = 4;
2198 break;
2199
2200 case 103: /* lvx */
2201 case 359: /* lvxl */
2202 op->type = MKOP(LOAD_VMX, 0, 16);
2203 op->element_size = 16;
2204 break;
2205
2206 case 135: /* stvebx */
2207 op->type = MKOP(STORE_VMX, 0, 1);
2208 op->element_size = 1;
2209 break;
2210
2211 case 167: /* stvehx */
2212 op->type = MKOP(STORE_VMX, 0, 2);
2213 op->element_size = 2;
2214 break;
2215
2216 case 199: /* stvewx */
2217 op->type = MKOP(STORE_VMX, 0, 4);
2218 op->element_size = 4;
2219 break;
2220
2221 case 231: /* stvx */
2222 case 487: /* stvxl */
2223 op->type = MKOP(STORE_VMX, 0, 16);
2224 break;
2225 #endif /* CONFIG_ALTIVEC */
2226
2227 #ifdef __powerpc64__
2228 case 21: /* ldx */
2229 case 53: /* ldux */
2230 op->type = MKOP(LOAD, u, 8);
2231 break;
2232
2233 case 149: /* stdx */
2234 case 181: /* stdux */
2235 op->type = MKOP(STORE, u, 8);
2236 break;
2237 #endif
2238
2239 case 151: /* stwx */
2240 case 183: /* stwux */
2241 op->type = MKOP(STORE, u, 4);
2242 break;
2243
2244 case 215: /* stbx */
2245 case 247: /* stbux */
2246 op->type = MKOP(STORE, u, 1);
2247 break;
2248
2249 case 279: /* lhzx */
2250 case 311: /* lhzux */
2251 op->type = MKOP(LOAD, u, 2);
2252 break;
2253
2254 #ifdef __powerpc64__
2255 case 341: /* lwax */
2256 case 373: /* lwaux */
2257 op->type = MKOP(LOAD, SIGNEXT | u, 4);
2258 break;
2259 #endif
2260
2261 case 343: /* lhax */
2262 case 375: /* lhaux */
2263 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2264 break;
2265
2266 case 407: /* sthx */
2267 case 439: /* sthux */
2268 op->type = MKOP(STORE, u, 2);
2269 break;
2270
2271 #ifdef __powerpc64__
2272 case 532: /* ldbrx */
2273 op->type = MKOP(LOAD, BYTEREV, 8);
2274 break;
2275
2276 #endif
2277 case 533: /* lswx */
2278 op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2279 break;
2280
2281 case 534: /* lwbrx */
2282 op->type = MKOP(LOAD, BYTEREV, 4);
2283 break;
2284
2285 case 597: /* lswi */
2286 if (rb == 0)
2287 rb = 32; /* # bytes to load */
2288 op->type = MKOP(LOAD_MULTI, 0, rb);
2289 op->ea = ra ? regs->gpr[ra] : 0;
2290 break;
2291
2292 #ifdef CONFIG_PPC_FPU
2293 case 535: /* lfsx */
2294 case 567: /* lfsux */
2295 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2296 break;
2297
2298 case 599: /* lfdx */
2299 case 631: /* lfdux */
2300 op->type = MKOP(LOAD_FP, u, 8);
2301 break;
2302
2303 case 663: /* stfsx */
2304 case 695: /* stfsux */
2305 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2306 break;
2307
2308 case 727: /* stfdx */
2309 case 759: /* stfdux */
2310 op->type = MKOP(STORE_FP, u, 8);
2311 break;
2312
2313 #ifdef __powerpc64__
2314 case 791: /* lfdpx */
2315 op->type = MKOP(LOAD_FP, 0, 16);
2316 break;
2317
2318 case 855: /* lfiwax */
2319 op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2320 break;
2321
2322 case 887: /* lfiwzx */
2323 op->type = MKOP(LOAD_FP, 0, 4);
2324 break;
2325
2326 case 919: /* stfdpx */
2327 op->type = MKOP(STORE_FP, 0, 16);
2328 break;
2329
2330 case 983: /* stfiwx */
2331 op->type = MKOP(STORE_FP, 0, 4);
2332 break;
2333 #endif /* __powerpc64 */
2334 #endif /* CONFIG_PPC_FPU */
2335
2336 #ifdef __powerpc64__
2337 case 660: /* stdbrx */
2338 op->type = MKOP(STORE, BYTEREV, 8);
2339 op->val = byterev_8(regs->gpr[rd]);
2340 break;
2341
2342 #endif
2343 case 661: /* stswx */
2344 op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2345 break;
2346
2347 case 662: /* stwbrx */
2348 op->type = MKOP(STORE, BYTEREV, 4);
2349 op->val = byterev_4(regs->gpr[rd]);
2350 break;
2351
2352 case 725: /* stswi */
2353 if (rb == 0)
2354 rb = 32; /* # bytes to store */
2355 op->type = MKOP(STORE_MULTI, 0, rb);
2356 op->ea = ra ? regs->gpr[ra] : 0;
2357 break;
2358
2359 case 790: /* lhbrx */
2360 op->type = MKOP(LOAD, BYTEREV, 2);
2361 break;
2362
2363 case 918: /* sthbrx */
2364 op->type = MKOP(STORE, BYTEREV, 2);
2365 op->val = byterev_2(regs->gpr[rd]);
2366 break;
2367
2368 #ifdef CONFIG_VSX
2369 case 12: /* lxsiwzx */
2370 op->reg = rd | ((word & 1) << 5);
2371 op->type = MKOP(LOAD_VSX, 0, 4);
2372 op->element_size = 8;
2373 break;
2374
2375 case 76: /* lxsiwax */
2376 op->reg = rd | ((word & 1) << 5);
2377 op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2378 op->element_size = 8;
2379 break;
2380
2381 case 140: /* stxsiwx */
2382 op->reg = rd | ((word & 1) << 5);
2383 op->type = MKOP(STORE_VSX, 0, 4);
2384 op->element_size = 8;
2385 break;
2386
2387 case 268: /* lxvx */
2388 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2389 goto unknown_opcode;
2390 op->reg = rd | ((word & 1) << 5);
2391 op->type = MKOP(LOAD_VSX, 0, 16);
2392 op->element_size = 16;
2393 op->vsx_flags = VSX_CHECK_VEC;
2394 break;
2395
2396 case 269: /* lxvl */
2397 case 301: { /* lxvll */
2398 int nb;
2399 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2400 goto unknown_opcode;
2401 op->reg = rd | ((word & 1) << 5);
2402 op->ea = ra ? regs->gpr[ra] : 0;
2403 nb = regs->gpr[rb] & 0xff;
2404 if (nb > 16)
2405 nb = 16;
2406 op->type = MKOP(LOAD_VSX, 0, nb);
2407 op->element_size = 16;
2408 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2409 VSX_CHECK_VEC;
2410 break;
2411 }
2412 case 332: /* lxvdsx */
2413 op->reg = rd | ((word & 1) << 5);
2414 op->type = MKOP(LOAD_VSX, 0, 8);
2415 op->element_size = 8;
2416 op->vsx_flags = VSX_SPLAT;
2417 break;
2418
2419 case 364: /* lxvwsx */
2420 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2421 goto unknown_opcode;
2422 op->reg = rd | ((word & 1) << 5);
2423 op->type = MKOP(LOAD_VSX, 0, 4);
2424 op->element_size = 4;
2425 op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2426 break;
2427
2428 case 396: /* stxvx */
2429 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2430 goto unknown_opcode;
2431 op->reg = rd | ((word & 1) << 5);
2432 op->type = MKOP(STORE_VSX, 0, 16);
2433 op->element_size = 16;
2434 op->vsx_flags = VSX_CHECK_VEC;
2435 break;
2436
2437 case 397: /* stxvl */
2438 case 429: { /* stxvll */
2439 int nb;
2440 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2441 goto unknown_opcode;
2442 op->reg = rd | ((word & 1) << 5);
2443 op->ea = ra ? regs->gpr[ra] : 0;
2444 nb = regs->gpr[rb] & 0xff;
2445 if (nb > 16)
2446 nb = 16;
2447 op->type = MKOP(STORE_VSX, 0, nb);
2448 op->element_size = 16;
2449 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2450 VSX_CHECK_VEC;
2451 break;
2452 }
2453 case 524: /* lxsspx */
2454 op->reg = rd | ((word & 1) << 5);
2455 op->type = MKOP(LOAD_VSX, 0, 4);
2456 op->element_size = 8;
2457 op->vsx_flags = VSX_FPCONV;
2458 break;
2459
2460 case 588: /* lxsdx */
2461 op->reg = rd | ((word & 1) << 5);
2462 op->type = MKOP(LOAD_VSX, 0, 8);
2463 op->element_size = 8;
2464 break;
2465
2466 case 652: /* stxsspx */
2467 op->reg = rd | ((word & 1) << 5);
2468 op->type = MKOP(STORE_VSX, 0, 4);
2469 op->element_size = 8;
2470 op->vsx_flags = VSX_FPCONV;
2471 break;
2472
2473 case 716: /* stxsdx */
2474 op->reg = rd | ((word & 1) << 5);
2475 op->type = MKOP(STORE_VSX, 0, 8);
2476 op->element_size = 8;
2477 break;
2478
2479 case 780: /* lxvw4x */
2480 op->reg = rd | ((word & 1) << 5);
2481 op->type = MKOP(LOAD_VSX, 0, 16);
2482 op->element_size = 4;
2483 break;
2484
2485 case 781: /* lxsibzx */
2486 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2487 goto unknown_opcode;
2488 op->reg = rd | ((word & 1) << 5);
2489 op->type = MKOP(LOAD_VSX, 0, 1);
2490 op->element_size = 8;
2491 op->vsx_flags = VSX_CHECK_VEC;
2492 break;
2493
2494 case 812: /* lxvh8x */
2495 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2496 goto unknown_opcode;
2497 op->reg = rd | ((word & 1) << 5);
2498 op->type = MKOP(LOAD_VSX, 0, 16);
2499 op->element_size = 2;
2500 op->vsx_flags = VSX_CHECK_VEC;
2501 break;
2502
2503 case 813: /* lxsihzx */
2504 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2505 goto unknown_opcode;
2506 op->reg = rd | ((word & 1) << 5);
2507 op->type = MKOP(LOAD_VSX, 0, 2);
2508 op->element_size = 8;
2509 op->vsx_flags = VSX_CHECK_VEC;
2510 break;
2511
2512 case 844: /* lxvd2x */
2513 op->reg = rd | ((word & 1) << 5);
2514 op->type = MKOP(LOAD_VSX, 0, 16);
2515 op->element_size = 8;
2516 break;
2517
2518 case 876: /* lxvb16x */
2519 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2520 goto unknown_opcode;
2521 op->reg = rd | ((word & 1) << 5);
2522 op->type = MKOP(LOAD_VSX, 0, 16);
2523 op->element_size = 1;
2524 op->vsx_flags = VSX_CHECK_VEC;
2525 break;
2526
2527 case 908: /* stxvw4x */
2528 op->reg = rd | ((word & 1) << 5);
2529 op->type = MKOP(STORE_VSX, 0, 16);
2530 op->element_size = 4;
2531 break;
2532
2533 case 909: /* stxsibx */
2534 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2535 goto unknown_opcode;
2536 op->reg = rd | ((word & 1) << 5);
2537 op->type = MKOP(STORE_VSX, 0, 1);
2538 op->element_size = 8;
2539 op->vsx_flags = VSX_CHECK_VEC;
2540 break;
2541
2542 case 940: /* stxvh8x */
2543 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2544 goto unknown_opcode;
2545 op->reg = rd | ((word & 1) << 5);
2546 op->type = MKOP(STORE_VSX, 0, 16);
2547 op->element_size = 2;
2548 op->vsx_flags = VSX_CHECK_VEC;
2549 break;
2550
2551 case 941: /* stxsihx */
2552 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2553 goto unknown_opcode;
2554 op->reg = rd | ((word & 1) << 5);
2555 op->type = MKOP(STORE_VSX, 0, 2);
2556 op->element_size = 8;
2557 op->vsx_flags = VSX_CHECK_VEC;
2558 break;
2559
2560 case 972: /* stxvd2x */
2561 op->reg = rd | ((word & 1) << 5);
2562 op->type = MKOP(STORE_VSX, 0, 16);
2563 op->element_size = 8;
2564 break;
2565
2566 case 1004: /* stxvb16x */
2567 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2568 goto unknown_opcode;
2569 op->reg = rd | ((word & 1) << 5);
2570 op->type = MKOP(STORE_VSX, 0, 16);
2571 op->element_size = 1;
2572 op->vsx_flags = VSX_CHECK_VEC;
2573 break;
2574
2575 #endif /* CONFIG_VSX */
2576 }
2577 break;
2578
2579 case 32: /* lwz */
2580 case 33: /* lwzu */
2581 op->type = MKOP(LOAD, u, 4);
2582 op->ea = dform_ea(word, regs);
2583 break;
2584
2585 case 34: /* lbz */
2586 case 35: /* lbzu */
2587 op->type = MKOP(LOAD, u, 1);
2588 op->ea = dform_ea(word, regs);
2589 break;
2590
2591 case 36: /* stw */
2592 case 37: /* stwu */
2593 op->type = MKOP(STORE, u, 4);
2594 op->ea = dform_ea(word, regs);
2595 break;
2596
2597 case 38: /* stb */
2598 case 39: /* stbu */
2599 op->type = MKOP(STORE, u, 1);
2600 op->ea = dform_ea(word, regs);
2601 break;
2602
2603 case 40: /* lhz */
2604 case 41: /* lhzu */
2605 op->type = MKOP(LOAD, u, 2);
2606 op->ea = dform_ea(word, regs);
2607 break;
2608
2609 case 42: /* lha */
2610 case 43: /* lhau */
2611 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2612 op->ea = dform_ea(word, regs);
2613 break;
2614
2615 case 44: /* sth */
2616 case 45: /* sthu */
2617 op->type = MKOP(STORE, u, 2);
2618 op->ea = dform_ea(word, regs);
2619 break;
2620
2621 case 46: /* lmw */
2622 if (ra >= rd)
2623 break; /* invalid form, ra in range to load */
2624 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2625 op->ea = dform_ea(word, regs);
2626 break;
2627
2628 case 47: /* stmw */
2629 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2630 op->ea = dform_ea(word, regs);
2631 break;
2632
2633 #ifdef CONFIG_PPC_FPU
2634 case 48: /* lfs */
2635 case 49: /* lfsu */
2636 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2637 op->ea = dform_ea(word, regs);
2638 break;
2639
2640 case 50: /* lfd */
2641 case 51: /* lfdu */
2642 op->type = MKOP(LOAD_FP, u, 8);
2643 op->ea = dform_ea(word, regs);
2644 break;
2645
2646 case 52: /* stfs */
2647 case 53: /* stfsu */
2648 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2649 op->ea = dform_ea(word, regs);
2650 break;
2651
2652 case 54: /* stfd */
2653 case 55: /* stfdu */
2654 op->type = MKOP(STORE_FP, u, 8);
2655 op->ea = dform_ea(word, regs);
2656 break;
2657 #endif
2658
2659 #ifdef __powerpc64__
2660 case 56: /* lq */
2661 if (!((rd & 1) || (rd == ra)))
2662 op->type = MKOP(LOAD, 0, 16);
2663 op->ea = dqform_ea(word, regs);
2664 break;
2665 #endif
2666
2667 #ifdef CONFIG_VSX
2668 case 57: /* lfdp, lxsd, lxssp */
2669 op->ea = dsform_ea(word, regs);
2670 switch (word & 3) {
2671 case 0: /* lfdp */
2672 if (rd & 1)
2673 break; /* reg must be even */
2674 op->type = MKOP(LOAD_FP, 0, 16);
2675 break;
2676 case 2: /* lxsd */
2677 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2678 goto unknown_opcode;
2679 op->reg = rd + 32;
2680 op->type = MKOP(LOAD_VSX, 0, 8);
2681 op->element_size = 8;
2682 op->vsx_flags = VSX_CHECK_VEC;
2683 break;
2684 case 3: /* lxssp */
2685 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2686 goto unknown_opcode;
2687 op->reg = rd + 32;
2688 op->type = MKOP(LOAD_VSX, 0, 4);
2689 op->element_size = 8;
2690 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2691 break;
2692 }
2693 break;
2694 #endif /* CONFIG_VSX */
2695
2696 #ifdef __powerpc64__
2697 case 58: /* ld[u], lwa */
2698 op->ea = dsform_ea(word, regs);
2699 switch (word & 3) {
2700 case 0: /* ld */
2701 op->type = MKOP(LOAD, 0, 8);
2702 break;
2703 case 1: /* ldu */
2704 op->type = MKOP(LOAD, UPDATE, 8);
2705 break;
2706 case 2: /* lwa */
2707 op->type = MKOP(LOAD, SIGNEXT, 4);
2708 break;
2709 }
2710 break;
2711 #endif
2712
2713 #ifdef CONFIG_VSX
2714 case 61: /* stfdp, lxv, stxsd, stxssp, stxv */
2715 switch (word & 7) {
2716 case 0: /* stfdp with LSB of DS field = 0 */
2717 case 4: /* stfdp with LSB of DS field = 1 */
2718 op->ea = dsform_ea(word, regs);
2719 op->type = MKOP(STORE_FP, 0, 16);
2720 break;
2721
2722 case 1: /* lxv */
2723 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2724 goto unknown_opcode;
2725 op->ea = dqform_ea(word, regs);
2726 if (word & 8)
2727 op->reg = rd + 32;
2728 op->type = MKOP(LOAD_VSX, 0, 16);
2729 op->element_size = 16;
2730 op->vsx_flags = VSX_CHECK_VEC;
2731 break;
2732
2733 case 2: /* stxsd with LSB of DS field = 0 */
2734 case 6: /* stxsd with LSB of DS field = 1 */
2735 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2736 goto unknown_opcode;
2737 op->ea = dsform_ea(word, regs);
2738 op->reg = rd + 32;
2739 op->type = MKOP(STORE_VSX, 0, 8);
2740 op->element_size = 8;
2741 op->vsx_flags = VSX_CHECK_VEC;
2742 break;
2743
2744 case 3: /* stxssp with LSB of DS field = 0 */
2745 case 7: /* stxssp with LSB of DS field = 1 */
2746 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2747 goto unknown_opcode;
2748 op->ea = dsform_ea(word, regs);
2749 op->reg = rd + 32;
2750 op->type = MKOP(STORE_VSX, 0, 4);
2751 op->element_size = 8;
2752 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2753 break;
2754
2755 case 5: /* stxv */
2756 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2757 goto unknown_opcode;
2758 op->ea = dqform_ea(word, regs);
2759 if (word & 8)
2760 op->reg = rd + 32;
2761 op->type = MKOP(STORE_VSX, 0, 16);
2762 op->element_size = 16;
2763 op->vsx_flags = VSX_CHECK_VEC;
2764 break;
2765 }
2766 break;
2767 #endif /* CONFIG_VSX */
2768
2769 #ifdef __powerpc64__
2770 case 62: /* std[u] */
2771 op->ea = dsform_ea(word, regs);
2772 switch (word & 3) {
2773 case 0: /* std */
2774 op->type = MKOP(STORE, 0, 8);
2775 break;
2776 case 1: /* stdu */
2777 op->type = MKOP(STORE, UPDATE, 8);
2778 break;
2779 case 2: /* stq */
2780 if (!(rd & 1))
2781 op->type = MKOP(STORE, 0, 16);
2782 break;
2783 }
2784 break;
2785 case 1: /* Prefixed instructions */
2786 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2787 goto unknown_opcode;
2788
2789 prefix_r = GET_PREFIX_R(word);
2790 ra = GET_PREFIX_RA(suffix);
2791 op->update_reg = ra;
2792 rd = (suffix >> 21) & 0x1f;
2793 op->reg = rd;
2794 op->val = regs->gpr[rd];
2795
2796 suffixopcode = get_op(suffix);
2797 prefixtype = (word >> 24) & 0x3;
2798 switch (prefixtype) {
2799 case 0: /* Type 00 Eight-Byte Load/Store */
2800 if (prefix_r && ra)
2801 break;
2802 op->ea = mlsd_8lsd_ea(word, suffix, regs);
2803 switch (suffixopcode) {
2804 case 41: /* plwa */
2805 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
2806 break;
2807 #ifdef CONFIG_VSX
2808 case 42: /* plxsd */
2809 op->reg = rd + 32;
2810 op->type = MKOP(LOAD_VSX, PREFIXED, 8);
2811 op->element_size = 8;
2812 op->vsx_flags = VSX_CHECK_VEC;
2813 break;
2814 case 43: /* plxssp */
2815 op->reg = rd + 32;
2816 op->type = MKOP(LOAD_VSX, PREFIXED, 4);
2817 op->element_size = 8;
2818 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2819 break;
2820 case 46: /* pstxsd */
2821 op->reg = rd + 32;
2822 op->type = MKOP(STORE_VSX, PREFIXED, 8);
2823 op->element_size = 8;
2824 op->vsx_flags = VSX_CHECK_VEC;
2825 break;
2826 case 47: /* pstxssp */
2827 op->reg = rd + 32;
2828 op->type = MKOP(STORE_VSX, PREFIXED, 4);
2829 op->element_size = 8;
2830 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2831 break;
2832 case 51: /* plxv1 */
2833 op->reg += 32;
2834 fallthrough;
2835 case 50: /* plxv0 */
2836 op->type = MKOP(LOAD_VSX, PREFIXED, 16);
2837 op->element_size = 16;
2838 op->vsx_flags = VSX_CHECK_VEC;
2839 break;
2840 case 55: /* pstxv1 */
2841 op->reg = rd + 32;
2842 fallthrough;
2843 case 54: /* pstxv0 */
2844 op->type = MKOP(STORE_VSX, PREFIXED, 16);
2845 op->element_size = 16;
2846 op->vsx_flags = VSX_CHECK_VEC;
2847 break;
2848 #endif /* CONFIG_VSX */
2849 case 56: /* plq */
2850 op->type = MKOP(LOAD, PREFIXED, 16);
2851 break;
2852 case 57: /* pld */
2853 op->type = MKOP(LOAD, PREFIXED, 8);
2854 break;
2855 case 60: /* pstq */
2856 op->type = MKOP(STORE, PREFIXED, 16);
2857 break;
2858 case 61: /* pstd */
2859 op->type = MKOP(STORE, PREFIXED, 8);
2860 break;
2861 }
2862 break;
2863 case 1: /* Type 01 Eight-Byte Register-to-Register */
2864 break;
2865 case 2: /* Type 10 Modified Load/Store */
2866 if (prefix_r && ra)
2867 break;
2868 op->ea = mlsd_8lsd_ea(word, suffix, regs);
2869 switch (suffixopcode) {
2870 case 32: /* plwz */
2871 op->type = MKOP(LOAD, PREFIXED, 4);
2872 break;
2873 case 34: /* plbz */
2874 op->type = MKOP(LOAD, PREFIXED, 1);
2875 break;
2876 case 36: /* pstw */
2877 op->type = MKOP(STORE, PREFIXED, 4);
2878 break;
2879 case 38: /* pstb */
2880 op->type = MKOP(STORE, PREFIXED, 1);
2881 break;
2882 case 40: /* plhz */
2883 op->type = MKOP(LOAD, PREFIXED, 2);
2884 break;
2885 case 42: /* plha */
2886 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2);
2887 break;
2888 case 44: /* psth */
2889 op->type = MKOP(STORE, PREFIXED, 2);
2890 break;
2891 case 48: /* plfs */
2892 op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4);
2893 break;
2894 case 50: /* plfd */
2895 op->type = MKOP(LOAD_FP, PREFIXED, 8);
2896 break;
2897 case 52: /* pstfs */
2898 op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4);
2899 break;
2900 case 54: /* pstfd */
2901 op->type = MKOP(STORE_FP, PREFIXED, 8);
2902 break;
2903 }
2904 break;
2905 case 3: /* Type 11 Modified Register-to-Register */
2906 break;
2907 }
2908 #endif /* __powerpc64__ */
2909
2910 }
2911
2912 if (OP_IS_LOAD_STORE(op->type) && (op->type & UPDATE)) {
2913 switch (GETTYPE(op->type)) {
2914 case LOAD:
2915 if (ra == rd)
2916 goto unknown_opcode;
2917 fallthrough;
2918 case STORE:
2919 case LOAD_FP:
2920 case STORE_FP:
2921 if (ra == 0)
2922 goto unknown_opcode;
2923 }
2924 }
2925
2926 #ifdef CONFIG_VSX
2927 if ((GETTYPE(op->type) == LOAD_VSX ||
2928 GETTYPE(op->type) == STORE_VSX) &&
2929 !cpu_has_feature(CPU_FTR_VSX)) {
2930 return -1;
2931 }
2932 #endif /* CONFIG_VSX */
2933
2934 return 0;
2935
2936 unknown_opcode:
2937 op->type = UNKNOWN;
2938 return 0;
2939
2940 logical_done:
2941 if (word & 1)
2942 set_cr0(regs, op);
2943 logical_done_nocc:
2944 op->reg = ra;
2945 op->type |= SETREG;
2946 return 1;
2947
2948 arith_done:
2949 if (word & 1)
2950 set_cr0(regs, op);
2951 compute_done:
2952 op->reg = rd;
2953 op->type |= SETREG;
2954 return 1;
2955
2956 priv:
2957 op->type = INTERRUPT | 0x700;
2958 op->val = SRR1_PROGPRIV;
2959 return 0;
2960
2961 trap:
2962 op->type = INTERRUPT | 0x700;
2963 op->val = SRR1_PROGTRAP;
2964 return 0;
2965 }
2966 EXPORT_SYMBOL_GPL(analyse_instr);
2967 NOKPROBE_SYMBOL(analyse_instr);
2968
2969 /*
2970 * For PPC32 we always use stwu with r1 to change the stack pointer.
2971 * So this emulated store may corrupt the exception frame, now we
2972 * have to provide the exception frame trampoline, which is pushed
2973 * below the kprobed function stack. So we only update gpr[1] but
2974 * don't emulate the real store operation. We will do real store
2975 * operation safely in exception return code by checking this flag.
2976 */
handle_stack_update(unsigned long ea,struct pt_regs * regs)2977 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
2978 {
2979 #ifdef CONFIG_PPC32
2980 /*
2981 * Check if we will touch kernel stack overflow
2982 */
2983 if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) {
2984 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n");
2985 return -EINVAL;
2986 }
2987 #endif /* CONFIG_PPC32 */
2988 /*
2989 * Check if we already set since that means we'll
2990 * lose the previous value.
2991 */
2992 WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
2993 set_thread_flag(TIF_EMULATE_STACK_STORE);
2994 return 0;
2995 }
2996
do_signext(unsigned long * valp,int size)2997 static nokprobe_inline void do_signext(unsigned long *valp, int size)
2998 {
2999 switch (size) {
3000 case 2:
3001 *valp = (signed short) *valp;
3002 break;
3003 case 4:
3004 *valp = (signed int) *valp;
3005 break;
3006 }
3007 }
3008
do_byterev(unsigned long * valp,int size)3009 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
3010 {
3011 switch (size) {
3012 case 2:
3013 *valp = byterev_2(*valp);
3014 break;
3015 case 4:
3016 *valp = byterev_4(*valp);
3017 break;
3018 #ifdef __powerpc64__
3019 case 8:
3020 *valp = byterev_8(*valp);
3021 break;
3022 #endif
3023 }
3024 }
3025
3026 /*
3027 * Emulate an instruction that can be executed just by updating
3028 * fields in *regs.
3029 */
emulate_update_regs(struct pt_regs * regs,struct instruction_op * op)3030 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
3031 {
3032 unsigned long next_pc;
3033
3034 next_pc = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op->type));
3035 switch (GETTYPE(op->type)) {
3036 case COMPUTE:
3037 if (op->type & SETREG)
3038 regs->gpr[op->reg] = op->val;
3039 if (op->type & SETCC)
3040 regs->ccr = op->ccval;
3041 if (op->type & SETXER)
3042 regs->xer = op->xerval;
3043 break;
3044
3045 case BRANCH:
3046 if (op->type & SETLK)
3047 regs->link = next_pc;
3048 if (op->type & BRTAKEN)
3049 next_pc = op->val;
3050 if (op->type & DECCTR)
3051 --regs->ctr;
3052 break;
3053
3054 case BARRIER:
3055 switch (op->type & BARRIER_MASK) {
3056 case BARRIER_SYNC:
3057 mb();
3058 break;
3059 case BARRIER_ISYNC:
3060 isync();
3061 break;
3062 case BARRIER_EIEIO:
3063 eieio();
3064 break;
3065 case BARRIER_LWSYNC:
3066 asm volatile("lwsync" : : : "memory");
3067 break;
3068 case BARRIER_PTESYNC:
3069 asm volatile("ptesync" : : : "memory");
3070 break;
3071 }
3072 break;
3073
3074 case MFSPR:
3075 switch (op->spr) {
3076 case SPRN_XER:
3077 regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
3078 break;
3079 case SPRN_LR:
3080 regs->gpr[op->reg] = regs->link;
3081 break;
3082 case SPRN_CTR:
3083 regs->gpr[op->reg] = regs->ctr;
3084 break;
3085 default:
3086 WARN_ON_ONCE(1);
3087 }
3088 break;
3089
3090 case MTSPR:
3091 switch (op->spr) {
3092 case SPRN_XER:
3093 regs->xer = op->val & 0xffffffffUL;
3094 break;
3095 case SPRN_LR:
3096 regs->link = op->val;
3097 break;
3098 case SPRN_CTR:
3099 regs->ctr = op->val;
3100 break;
3101 default:
3102 WARN_ON_ONCE(1);
3103 }
3104 break;
3105
3106 default:
3107 WARN_ON_ONCE(1);
3108 }
3109 regs->nip = next_pc;
3110 }
3111 NOKPROBE_SYMBOL(emulate_update_regs);
3112
3113 /*
3114 * Emulate a previously-analysed load or store instruction.
3115 * Return values are:
3116 * 0 = instruction emulated successfully
3117 * -EFAULT = address out of range or access faulted (regs->dar
3118 * contains the faulting address)
3119 * -EACCES = misaligned access, instruction requires alignment
3120 * -EINVAL = unknown operation in *op
3121 */
emulate_loadstore(struct pt_regs * regs,struct instruction_op * op)3122 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
3123 {
3124 int err, size, type;
3125 int i, rd, nb;
3126 unsigned int cr;
3127 unsigned long val;
3128 unsigned long ea;
3129 bool cross_endian;
3130
3131 err = 0;
3132 size = GETSIZE(op->type);
3133 type = GETTYPE(op->type);
3134 cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
3135 ea = truncate_if_32bit(regs->msr, op->ea);
3136
3137 switch (type) {
3138 case LARX:
3139 if (ea & (size - 1))
3140 return -EACCES; /* can't handle misaligned */
3141 if (!address_ok(regs, ea, size))
3142 return -EFAULT;
3143 err = 0;
3144 val = 0;
3145 switch (size) {
3146 #ifdef __powerpc64__
3147 case 1:
3148 __get_user_asmx(val, ea, err, "lbarx");
3149 break;
3150 case 2:
3151 __get_user_asmx(val, ea, err, "lharx");
3152 break;
3153 #endif
3154 case 4:
3155 __get_user_asmx(val, ea, err, "lwarx");
3156 break;
3157 #ifdef __powerpc64__
3158 case 8:
3159 __get_user_asmx(val, ea, err, "ldarx");
3160 break;
3161 case 16:
3162 err = do_lqarx(ea, ®s->gpr[op->reg]);
3163 break;
3164 #endif
3165 default:
3166 return -EINVAL;
3167 }
3168 if (err) {
3169 regs->dar = ea;
3170 break;
3171 }
3172 if (size < 16)
3173 regs->gpr[op->reg] = val;
3174 break;
3175
3176 case STCX:
3177 if (ea & (size - 1))
3178 return -EACCES; /* can't handle misaligned */
3179 if (!address_ok(regs, ea, size))
3180 return -EFAULT;
3181 err = 0;
3182 switch (size) {
3183 #ifdef __powerpc64__
3184 case 1:
3185 __put_user_asmx(op->val, ea, err, "stbcx.", cr);
3186 break;
3187 case 2:
3188 __put_user_asmx(op->val, ea, err, "stbcx.", cr);
3189 break;
3190 #endif
3191 case 4:
3192 __put_user_asmx(op->val, ea, err, "stwcx.", cr);
3193 break;
3194 #ifdef __powerpc64__
3195 case 8:
3196 __put_user_asmx(op->val, ea, err, "stdcx.", cr);
3197 break;
3198 case 16:
3199 err = do_stqcx(ea, regs->gpr[op->reg],
3200 regs->gpr[op->reg + 1], &cr);
3201 break;
3202 #endif
3203 default:
3204 return -EINVAL;
3205 }
3206 if (!err)
3207 regs->ccr = (regs->ccr & 0x0fffffff) |
3208 (cr & 0xe0000000) |
3209 ((regs->xer >> 3) & 0x10000000);
3210 else
3211 regs->dar = ea;
3212 break;
3213
3214 case LOAD:
3215 #ifdef __powerpc64__
3216 if (size == 16) {
3217 err = emulate_lq(regs, ea, op->reg, cross_endian);
3218 break;
3219 }
3220 #endif
3221 err = read_mem(®s->gpr[op->reg], ea, size, regs);
3222 if (!err) {
3223 if (op->type & SIGNEXT)
3224 do_signext(®s->gpr[op->reg], size);
3225 if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
3226 do_byterev(®s->gpr[op->reg], size);
3227 }
3228 break;
3229
3230 #ifdef CONFIG_PPC_FPU
3231 case LOAD_FP:
3232 /*
3233 * If the instruction is in userspace, we can emulate it even
3234 * if the VMX state is not live, because we have the state
3235 * stored in the thread_struct. If the instruction is in
3236 * the kernel, we must not touch the state in the thread_struct.
3237 */
3238 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3239 return 0;
3240 err = do_fp_load(op, ea, regs, cross_endian);
3241 break;
3242 #endif
3243 #ifdef CONFIG_ALTIVEC
3244 case LOAD_VMX:
3245 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3246 return 0;
3247 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
3248 break;
3249 #endif
3250 #ifdef CONFIG_VSX
3251 case LOAD_VSX: {
3252 unsigned long msrbit = MSR_VSX;
3253
3254 /*
3255 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3256 * when the target of the instruction is a vector register.
3257 */
3258 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3259 msrbit = MSR_VEC;
3260 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3261 return 0;
3262 err = do_vsx_load(op, ea, regs, cross_endian);
3263 break;
3264 }
3265 #endif
3266 case LOAD_MULTI:
3267 if (!address_ok(regs, ea, size))
3268 return -EFAULT;
3269 rd = op->reg;
3270 for (i = 0; i < size; i += 4) {
3271 unsigned int v32 = 0;
3272
3273 nb = size - i;
3274 if (nb > 4)
3275 nb = 4;
3276 err = copy_mem_in((u8 *) &v32, ea, nb, regs);
3277 if (err)
3278 break;
3279 if (unlikely(cross_endian))
3280 v32 = byterev_4(v32);
3281 regs->gpr[rd] = v32;
3282 ea += 4;
3283 /* reg number wraps from 31 to 0 for lsw[ix] */
3284 rd = (rd + 1) & 0x1f;
3285 }
3286 break;
3287
3288 case STORE:
3289 #ifdef __powerpc64__
3290 if (size == 16) {
3291 err = emulate_stq(regs, ea, op->reg, cross_endian);
3292 break;
3293 }
3294 #endif
3295 if ((op->type & UPDATE) && size == sizeof(long) &&
3296 op->reg == 1 && op->update_reg == 1 &&
3297 !(regs->msr & MSR_PR) &&
3298 ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
3299 err = handle_stack_update(ea, regs);
3300 break;
3301 }
3302 if (unlikely(cross_endian))
3303 do_byterev(&op->val, size);
3304 err = write_mem(op->val, ea, size, regs);
3305 break;
3306
3307 #ifdef CONFIG_PPC_FPU
3308 case STORE_FP:
3309 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3310 return 0;
3311 err = do_fp_store(op, ea, regs, cross_endian);
3312 break;
3313 #endif
3314 #ifdef CONFIG_ALTIVEC
3315 case STORE_VMX:
3316 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3317 return 0;
3318 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
3319 break;
3320 #endif
3321 #ifdef CONFIG_VSX
3322 case STORE_VSX: {
3323 unsigned long msrbit = MSR_VSX;
3324
3325 /*
3326 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3327 * when the target of the instruction is a vector register.
3328 */
3329 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3330 msrbit = MSR_VEC;
3331 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3332 return 0;
3333 err = do_vsx_store(op, ea, regs, cross_endian);
3334 break;
3335 }
3336 #endif
3337 case STORE_MULTI:
3338 if (!address_ok(regs, ea, size))
3339 return -EFAULT;
3340 rd = op->reg;
3341 for (i = 0; i < size; i += 4) {
3342 unsigned int v32 = regs->gpr[rd];
3343
3344 nb = size - i;
3345 if (nb > 4)
3346 nb = 4;
3347 if (unlikely(cross_endian))
3348 v32 = byterev_4(v32);
3349 err = copy_mem_out((u8 *) &v32, ea, nb, regs);
3350 if (err)
3351 break;
3352 ea += 4;
3353 /* reg number wraps from 31 to 0 for stsw[ix] */
3354 rd = (rd + 1) & 0x1f;
3355 }
3356 break;
3357
3358 default:
3359 return -EINVAL;
3360 }
3361
3362 if (err)
3363 return err;
3364
3365 if (op->type & UPDATE)
3366 regs->gpr[op->update_reg] = op->ea;
3367
3368 return 0;
3369 }
3370 NOKPROBE_SYMBOL(emulate_loadstore);
3371
3372 /*
3373 * Emulate instructions that cause a transfer of control,
3374 * loads and stores, and a few other instructions.
3375 * Returns 1 if the step was emulated, 0 if not,
3376 * or -1 if the instruction is one that should not be stepped,
3377 * such as an rfid, or a mtmsrd that would clear MSR_RI.
3378 */
emulate_step(struct pt_regs * regs,struct ppc_inst instr)3379 int emulate_step(struct pt_regs *regs, struct ppc_inst instr)
3380 {
3381 struct instruction_op op;
3382 int r, err, type;
3383 unsigned long val;
3384 unsigned long ea;
3385
3386 r = analyse_instr(&op, regs, instr);
3387 if (r < 0)
3388 return r;
3389 if (r > 0) {
3390 emulate_update_regs(regs, &op);
3391 return 1;
3392 }
3393
3394 err = 0;
3395 type = GETTYPE(op.type);
3396
3397 if (OP_IS_LOAD_STORE(type)) {
3398 err = emulate_loadstore(regs, &op);
3399 if (err)
3400 return 0;
3401 goto instr_done;
3402 }
3403
3404 switch (type) {
3405 case CACHEOP:
3406 ea = truncate_if_32bit(regs->msr, op.ea);
3407 if (!address_ok(regs, ea, 8))
3408 return 0;
3409 switch (op.type & CACHEOP_MASK) {
3410 case DCBST:
3411 __cacheop_user_asmx(ea, err, "dcbst");
3412 break;
3413 case DCBF:
3414 __cacheop_user_asmx(ea, err, "dcbf");
3415 break;
3416 case DCBTST:
3417 if (op.reg == 0)
3418 prefetchw((void *) ea);
3419 break;
3420 case DCBT:
3421 if (op.reg == 0)
3422 prefetch((void *) ea);
3423 break;
3424 case ICBI:
3425 __cacheop_user_asmx(ea, err, "icbi");
3426 break;
3427 case DCBZ:
3428 err = emulate_dcbz(ea, regs);
3429 break;
3430 }
3431 if (err) {
3432 regs->dar = ea;
3433 return 0;
3434 }
3435 goto instr_done;
3436
3437 case MFMSR:
3438 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3439 goto instr_done;
3440
3441 case MTMSR:
3442 val = regs->gpr[op.reg];
3443 if ((val & MSR_RI) == 0)
3444 /* can't step mtmsr[d] that would clear MSR_RI */
3445 return -1;
3446 /* here op.val is the mask of bits to change */
3447 regs->msr = (regs->msr & ~op.val) | (val & op.val);
3448 goto instr_done;
3449
3450 #ifdef CONFIG_PPC64
3451 case SYSCALL: /* sc */
3452 /*
3453 * N.B. this uses knowledge about how the syscall
3454 * entry code works. If that is changed, this will
3455 * need to be changed also.
3456 */
3457 if (IS_ENABLED(CONFIG_PPC_FAST_ENDIAN_SWITCH) &&
3458 cpu_has_feature(CPU_FTR_REAL_LE) &&
3459 regs->gpr[0] == 0x1ebe) {
3460 regs->msr ^= MSR_LE;
3461 goto instr_done;
3462 }
3463 regs->gpr[9] = regs->gpr[13];
3464 regs->gpr[10] = MSR_KERNEL;
3465 regs->gpr[11] = regs->nip + 4;
3466 regs->gpr[12] = regs->msr & MSR_MASK;
3467 regs->gpr[13] = (unsigned long) get_paca();
3468 regs->nip = (unsigned long) &system_call_common;
3469 regs->msr = MSR_KERNEL;
3470 return 1;
3471
3472 #ifdef CONFIG_PPC_BOOK3S_64
3473 case SYSCALL_VECTORED_0: /* scv 0 */
3474 regs->gpr[9] = regs->gpr[13];
3475 regs->gpr[10] = MSR_KERNEL;
3476 regs->gpr[11] = regs->nip + 4;
3477 regs->gpr[12] = regs->msr & MSR_MASK;
3478 regs->gpr[13] = (unsigned long) get_paca();
3479 regs->nip = (unsigned long) &system_call_vectored_emulate;
3480 regs->msr = MSR_KERNEL;
3481 return 1;
3482 #endif
3483
3484 case RFI:
3485 return -1;
3486 #endif
3487 }
3488 return 0;
3489
3490 instr_done:
3491 regs->nip = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type));
3492 return 1;
3493 }
3494 NOKPROBE_SYMBOL(emulate_step);
3495