1 /* 2 * This header was generated from the Linux kernel headers by update_headers.py, 3 * to provide necessary information from kernel to userspace, such as constants, 4 * structures, and macros, and thus, contains no copyrightable information. 5 */ 6 #ifndef _V4L2_DV_TIMINGS_H 7 #define _V4L2_DV_TIMINGS_H 8 #if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6)) 9 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ 10 { .bt = { _width , ## args } } 11 #else 12 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ 13 .bt = { _width , ## args } 14 #endif 15 #define V4L2_DV_BT_CEA_640X480P59_94 { \ 16 .type = V4L2_DV_BT_656_1120, \ 17 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 18 25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \ 19 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \ 20 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 1) \ 21 } 22 #define V4L2_DV_BT_CEA_720X480I59_94 { \ 23 .type = V4L2_DV_BT_656_1120, \ 24 V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \ 25 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \ 26 V4L2_DV_BT_STD_CEA861, \ 27 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \ 28 V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ 29 { 4, 3 }, 6) \ 30 } 31 #define V4L2_DV_BT_CEA_720X480P59_94 { \ 32 .type = V4L2_DV_BT_656_1120, \ 33 V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \ 34 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \ 35 V4L2_DV_BT_STD_CEA861, \ 36 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ 37 V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 2) \ 38 } 39 #define V4L2_DV_BT_CEA_720X576I50 { \ 40 .type = V4L2_DV_BT_656_1120, \ 41 V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \ 42 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \ 43 V4L2_DV_BT_STD_CEA861, \ 44 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \ 45 V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ 46 { 4, 3 }, 21) \ 47 } 48 #define V4L2_DV_BT_CEA_720X576P50 { \ 49 .type = V4L2_DV_BT_656_1120, \ 50 V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \ 51 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \ 52 V4L2_DV_BT_STD_CEA861, \ 53 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ 54 V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 17) \ 55 } 56 #define V4L2_DV_BT_CEA_1280X720P24 { \ 57 .type = V4L2_DV_BT_656_1120, \ 58 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ 59 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 60 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \ 61 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \ 62 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 60) \ 63 } 64 #define V4L2_DV_BT_CEA_1280X720P25 { \ 65 .type = V4L2_DV_BT_656_1120, \ 66 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ 67 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 68 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \ 69 V4L2_DV_BT_STD_CEA861, \ 70 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 61) \ 71 } 72 #define V4L2_DV_BT_CEA_1280X720P30 { \ 73 .type = V4L2_DV_BT_656_1120, \ 74 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ 75 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 76 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \ 77 V4L2_DV_BT_STD_CEA861, \ 78 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ 79 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 62) \ 80 } 81 #define V4L2_DV_BT_CEA_1280X720P50 { \ 82 .type = V4L2_DV_BT_656_1120, \ 83 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ 84 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 85 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \ 86 V4L2_DV_BT_STD_CEA861, \ 87 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 19) \ 88 } 89 #define V4L2_DV_BT_CEA_1280X720P60 { \ 90 .type = V4L2_DV_BT_656_1120, \ 91 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ 92 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 93 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \ 94 V4L2_DV_BT_STD_CEA861, \ 95 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ 96 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 4) \ 97 } 98 #define V4L2_DV_BT_CEA_1920X1080P24 { \ 99 .type = V4L2_DV_BT_656_1120, \ 100 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ 101 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 102 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \ 103 V4L2_DV_BT_STD_CEA861, \ 104 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ 105 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 32) \ 106 } 107 #define V4L2_DV_BT_CEA_1920X1080P25 { \ 108 .type = V4L2_DV_BT_656_1120, \ 109 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ 110 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 111 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \ 112 V4L2_DV_BT_STD_CEA861, \ 113 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 33) \ 114 } 115 #define V4L2_DV_BT_CEA_1920X1080P30 { \ 116 .type = V4L2_DV_BT_656_1120, \ 117 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ 118 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 119 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \ 120 V4L2_DV_BT_STD_CEA861, \ 121 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ 122 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 34) \ 123 } 124 #define V4L2_DV_BT_CEA_1920X1080I50 { \ 125 .type = V4L2_DV_BT_656_1120, \ 126 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \ 127 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 128 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \ 129 V4L2_DV_BT_STD_CEA861, \ 130 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \ 131 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 20) \ 132 } 133 #define V4L2_DV_BT_CEA_1920X1080P50 { \ 134 .type = V4L2_DV_BT_656_1120, \ 135 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ 136 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 137 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \ 138 V4L2_DV_BT_STD_CEA861, \ 139 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 31) \ 140 } 141 #define V4L2_DV_BT_CEA_1920X1080I60 { \ 142 .type = V4L2_DV_BT_656_1120, \ 143 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \ 144 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 145 74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \ 146 V4L2_DV_BT_STD_CEA861, \ 147 V4L2_DV_FL_CAN_REDUCE_FPS | \ 148 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \ 149 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 5) \ 150 } 151 #define V4L2_DV_BT_CEA_1920X1080P60 { \ 152 .type = V4L2_DV_BT_656_1120, \ 153 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ 154 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 155 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \ 156 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \ 157 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ 158 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 16) \ 159 } 160 #define V4L2_DV_BT_CEA_3840X2160P24 { \ 161 .type = V4L2_DV_BT_656_1120, \ 162 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ 163 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 164 297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \ 165 V4L2_DV_BT_STD_CEA861, \ 166 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ 167 V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \ 168 { 0, 0 }, 93, 3) \ 169 } 170 #define V4L2_DV_BT_CEA_3840X2160P25 { \ 171 .type = V4L2_DV_BT_656_1120, \ 172 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ 173 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 174 297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \ 175 V4L2_DV_BT_STD_CEA861, \ 176 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC | \ 177 V4L2_DV_FL_HAS_HDMI_VIC, { 0, 0 }, 94, 2) \ 178 } 179 #define V4L2_DV_BT_CEA_3840X2160P30 { \ 180 .type = V4L2_DV_BT_656_1120, \ 181 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ 182 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 183 297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \ 184 V4L2_DV_BT_STD_CEA861, \ 185 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ 186 V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \ 187 { 0, 0 }, 95, 1) \ 188 } 189 #define V4L2_DV_BT_CEA_3840X2160P50 { \ 190 .type = V4L2_DV_BT_656_1120, \ 191 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ 192 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 193 594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \ 194 V4L2_DV_BT_STD_CEA861, \ 195 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 96) \ 196 } 197 #define V4L2_DV_BT_CEA_3840X2160P60 { \ 198 .type = V4L2_DV_BT_656_1120, \ 199 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ 200 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 201 594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \ 202 V4L2_DV_BT_STD_CEA861, \ 203 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ 204 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 97) \ 205 } 206 #define V4L2_DV_BT_CEA_4096X2160P24 { \ 207 .type = V4L2_DV_BT_656_1120, \ 208 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ 209 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 210 297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \ 211 V4L2_DV_BT_STD_CEA861, \ 212 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ 213 V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \ 214 { 0, 0 }, 98, 4) \ 215 } 216 #define V4L2_DV_BT_CEA_4096X2160P25 { \ 217 .type = V4L2_DV_BT_656_1120, \ 218 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ 219 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 220 297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \ 221 V4L2_DV_BT_STD_CEA861, \ 222 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 99) \ 223 } 224 #define V4L2_DV_BT_CEA_4096X2160P30 { \ 225 .type = V4L2_DV_BT_656_1120, \ 226 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ 227 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 228 297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \ 229 V4L2_DV_BT_STD_CEA861, \ 230 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ 231 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 100) \ 232 } 233 #define V4L2_DV_BT_CEA_4096X2160P50 { \ 234 .type = V4L2_DV_BT_656_1120, \ 235 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ 236 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 237 594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \ 238 V4L2_DV_BT_STD_CEA861, \ 239 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 101) \ 240 } 241 #define V4L2_DV_BT_CEA_4096X2160P60 { \ 242 .type = V4L2_DV_BT_656_1120, \ 243 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ 244 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 245 594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \ 246 V4L2_DV_BT_STD_CEA861, \ 247 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ 248 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 102) \ 249 } 250 #define V4L2_DV_BT_DMT_640X350P85 { \ 251 .type = V4L2_DV_BT_656_1120, \ 252 V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \ 253 31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \ 254 V4L2_DV_BT_STD_DMT, 0) \ 255 } 256 #define V4L2_DV_BT_DMT_640X400P85 { \ 257 .type = V4L2_DV_BT_656_1120, \ 258 V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \ 259 31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \ 260 V4L2_DV_BT_STD_DMT, 0) \ 261 } 262 #define V4L2_DV_BT_DMT_720X400P85 { \ 263 .type = V4L2_DV_BT_656_1120, \ 264 V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \ 265 35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \ 266 V4L2_DV_BT_STD_DMT, 0) \ 267 } 268 #define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94 269 #define V4L2_DV_BT_DMT_640X480P72 { \ 270 .type = V4L2_DV_BT_656_1120, \ 271 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 272 31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \ 273 V4L2_DV_BT_STD_DMT, 0) \ 274 } 275 #define V4L2_DV_BT_DMT_640X480P75 { \ 276 .type = V4L2_DV_BT_656_1120, \ 277 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 278 31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \ 279 V4L2_DV_BT_STD_DMT, 0) \ 280 } 281 #define V4L2_DV_BT_DMT_640X480P85 { \ 282 .type = V4L2_DV_BT_656_1120, \ 283 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 284 36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \ 285 V4L2_DV_BT_STD_DMT, 0) \ 286 } 287 #define V4L2_DV_BT_DMT_800X600P56 { \ 288 .type = V4L2_DV_BT_656_1120, \ 289 V4L2_INIT_BT_TIMINGS(800, 600, 0, \ 290 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 291 36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \ 292 V4L2_DV_BT_STD_DMT, 0) \ 293 } 294 #define V4L2_DV_BT_DMT_800X600P60 { \ 295 .type = V4L2_DV_BT_656_1120, \ 296 V4L2_INIT_BT_TIMINGS(800, 600, 0, \ 297 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 298 40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \ 299 V4L2_DV_BT_STD_DMT, 0) \ 300 } 301 #define V4L2_DV_BT_DMT_800X600P72 { \ 302 .type = V4L2_DV_BT_656_1120, \ 303 V4L2_INIT_BT_TIMINGS(800, 600, 0, \ 304 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 305 50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \ 306 V4L2_DV_BT_STD_DMT, 0) \ 307 } 308 #define V4L2_DV_BT_DMT_800X600P75 { \ 309 .type = V4L2_DV_BT_656_1120, \ 310 V4L2_INIT_BT_TIMINGS(800, 600, 0, \ 311 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 312 49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \ 313 V4L2_DV_BT_STD_DMT, 0) \ 314 } 315 #define V4L2_DV_BT_DMT_800X600P85 { \ 316 .type = V4L2_DV_BT_656_1120, \ 317 V4L2_INIT_BT_TIMINGS(800, 600, 0, \ 318 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 319 56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \ 320 V4L2_DV_BT_STD_DMT, 0) \ 321 } 322 #define V4L2_DV_BT_DMT_800X600P120_RB { \ 323 .type = V4L2_DV_BT_656_1120, \ 324 V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \ 325 73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \ 326 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 327 V4L2_DV_FL_REDUCED_BLANKING) \ 328 } 329 #define V4L2_DV_BT_DMT_848X480P60 { \ 330 .type = V4L2_DV_BT_656_1120, \ 331 V4L2_INIT_BT_TIMINGS(848, 480, 0, \ 332 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 333 33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \ 334 V4L2_DV_BT_STD_DMT, 0) \ 335 } 336 #define V4L2_DV_BT_DMT_1024X768I43 { \ 337 .type = V4L2_DV_BT_656_1120, \ 338 V4L2_INIT_BT_TIMINGS(1024, 768, 1, \ 339 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 340 44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \ 341 V4L2_DV_BT_STD_DMT, 0) \ 342 } 343 #define V4L2_DV_BT_DMT_1024X768P60 { \ 344 .type = V4L2_DV_BT_656_1120, \ 345 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \ 346 65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \ 347 V4L2_DV_BT_STD_DMT, 0) \ 348 } 349 #define V4L2_DV_BT_DMT_1024X768P70 { \ 350 .type = V4L2_DV_BT_656_1120, \ 351 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \ 352 75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \ 353 V4L2_DV_BT_STD_DMT, 0) \ 354 } 355 #define V4L2_DV_BT_DMT_1024X768P75 { \ 356 .type = V4L2_DV_BT_656_1120, \ 357 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \ 358 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 359 78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \ 360 V4L2_DV_BT_STD_DMT, 0) \ 361 } 362 #define V4L2_DV_BT_DMT_1024X768P85 { \ 363 .type = V4L2_DV_BT_656_1120, \ 364 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \ 365 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 366 94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \ 367 V4L2_DV_BT_STD_DMT, 0) \ 368 } 369 #define V4L2_DV_BT_DMT_1024X768P120_RB { \ 370 .type = V4L2_DV_BT_656_1120, \ 371 V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 372 115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \ 373 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 374 V4L2_DV_FL_REDUCED_BLANKING) \ 375 } 376 #define V4L2_DV_BT_DMT_1152X864P75 { \ 377 .type = V4L2_DV_BT_656_1120, \ 378 V4L2_INIT_BT_TIMINGS(1152, 864, 0, \ 379 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 380 108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \ 381 V4L2_DV_BT_STD_DMT, 0) \ 382 } 383 #define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60 384 #define V4L2_DV_BT_DMT_1280X768P60_RB { \ 385 .type = V4L2_DV_BT_656_1120, \ 386 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 387 68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \ 388 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 389 V4L2_DV_FL_REDUCED_BLANKING) \ 390 } 391 #define V4L2_DV_BT_DMT_1280X768P60 { \ 392 .type = V4L2_DV_BT_656_1120, \ 393 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 394 79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \ 395 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 396 } 397 #define V4L2_DV_BT_DMT_1280X768P75 { \ 398 .type = V4L2_DV_BT_656_1120, \ 399 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 400 102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \ 401 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 402 } 403 #define V4L2_DV_BT_DMT_1280X768P85 { \ 404 .type = V4L2_DV_BT_656_1120, \ 405 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 406 117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \ 407 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 408 } 409 #define V4L2_DV_BT_DMT_1280X768P120_RB { \ 410 .type = V4L2_DV_BT_656_1120, \ 411 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 412 140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \ 413 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 414 V4L2_DV_FL_REDUCED_BLANKING) \ 415 } 416 #define V4L2_DV_BT_DMT_1280X800P60_RB { \ 417 .type = V4L2_DV_BT_656_1120, \ 418 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \ 419 71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \ 420 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 421 V4L2_DV_FL_REDUCED_BLANKING) \ 422 } 423 #define V4L2_DV_BT_DMT_1280X800P60 { \ 424 .type = V4L2_DV_BT_656_1120, \ 425 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 426 83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \ 427 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 428 } 429 #define V4L2_DV_BT_DMT_1280X800P75 { \ 430 .type = V4L2_DV_BT_656_1120, \ 431 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 432 106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \ 433 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 434 } 435 #define V4L2_DV_BT_DMT_1280X800P85 { \ 436 .type = V4L2_DV_BT_656_1120, \ 437 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 438 122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \ 439 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 440 } 441 #define V4L2_DV_BT_DMT_1280X800P120_RB { \ 442 .type = V4L2_DV_BT_656_1120, \ 443 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \ 444 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \ 445 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 446 V4L2_DV_FL_REDUCED_BLANKING) \ 447 } 448 #define V4L2_DV_BT_DMT_1280X960P60 { \ 449 .type = V4L2_DV_BT_656_1120, \ 450 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \ 451 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 452 108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \ 453 V4L2_DV_BT_STD_DMT, 0) \ 454 } 455 #define V4L2_DV_BT_DMT_1280X960P85 { \ 456 .type = V4L2_DV_BT_656_1120, \ 457 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \ 458 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 459 148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \ 460 V4L2_DV_BT_STD_DMT, 0) \ 461 } 462 #define V4L2_DV_BT_DMT_1280X960P120_RB { \ 463 .type = V4L2_DV_BT_656_1120, \ 464 V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \ 465 175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \ 466 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 467 V4L2_DV_FL_REDUCED_BLANKING) \ 468 } 469 #define V4L2_DV_BT_DMT_1280X1024P60 { \ 470 .type = V4L2_DV_BT_656_1120, \ 471 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ 472 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 473 108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \ 474 V4L2_DV_BT_STD_DMT, 0) \ 475 } 476 #define V4L2_DV_BT_DMT_1280X1024P75 { \ 477 .type = V4L2_DV_BT_656_1120, \ 478 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ 479 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 480 135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \ 481 V4L2_DV_BT_STD_DMT, 0) \ 482 } 483 #define V4L2_DV_BT_DMT_1280X1024P85 { \ 484 .type = V4L2_DV_BT_656_1120, \ 485 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ 486 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 487 157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \ 488 V4L2_DV_BT_STD_DMT, 0) \ 489 } 490 #define V4L2_DV_BT_DMT_1280X1024P120_RB { \ 491 .type = V4L2_DV_BT_656_1120, \ 492 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \ 493 187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \ 494 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 495 V4L2_DV_FL_REDUCED_BLANKING) \ 496 } 497 #define V4L2_DV_BT_DMT_1360X768P60 { \ 498 .type = V4L2_DV_BT_656_1120, \ 499 V4L2_INIT_BT_TIMINGS(1360, 768, 0, \ 500 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 501 85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \ 502 V4L2_DV_BT_STD_DMT, 0) \ 503 } 504 #define V4L2_DV_BT_DMT_1360X768P120_RB { \ 505 .type = V4L2_DV_BT_656_1120, \ 506 V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 507 148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \ 508 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 509 V4L2_DV_FL_REDUCED_BLANKING) \ 510 } 511 #define V4L2_DV_BT_DMT_1366X768P60 { \ 512 .type = V4L2_DV_BT_656_1120, \ 513 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \ 514 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 515 85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \ 516 V4L2_DV_BT_STD_DMT, 0) \ 517 } 518 #define V4L2_DV_BT_DMT_1366X768P60_RB { \ 519 .type = V4L2_DV_BT_656_1120, \ 520 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \ 521 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 522 72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \ 523 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ 524 } 525 #define V4L2_DV_BT_DMT_1400X1050P60_RB { \ 526 .type = V4L2_DV_BT_656_1120, \ 527 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 528 101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \ 529 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 530 V4L2_DV_FL_REDUCED_BLANKING) \ 531 } 532 #define V4L2_DV_BT_DMT_1400X1050P60 { \ 533 .type = V4L2_DV_BT_656_1120, \ 534 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 535 121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \ 536 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 537 } 538 #define V4L2_DV_BT_DMT_1400X1050P75 { \ 539 .type = V4L2_DV_BT_656_1120, \ 540 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 541 156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \ 542 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 543 } 544 #define V4L2_DV_BT_DMT_1400X1050P85 { \ 545 .type = V4L2_DV_BT_656_1120, \ 546 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 547 179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \ 548 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 549 } 550 #define V4L2_DV_BT_DMT_1400X1050P120_RB { \ 551 .type = V4L2_DV_BT_656_1120, \ 552 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 553 208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \ 554 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 555 V4L2_DV_FL_REDUCED_BLANKING) \ 556 } 557 #define V4L2_DV_BT_DMT_1440X900P60_RB { \ 558 .type = V4L2_DV_BT_656_1120, \ 559 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \ 560 88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \ 561 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 562 V4L2_DV_FL_REDUCED_BLANKING) \ 563 } 564 #define V4L2_DV_BT_DMT_1440X900P60 { \ 565 .type = V4L2_DV_BT_656_1120, \ 566 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 567 106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \ 568 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 569 } 570 #define V4L2_DV_BT_DMT_1440X900P75 { \ 571 .type = V4L2_DV_BT_656_1120, \ 572 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 573 136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \ 574 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 575 } 576 #define V4L2_DV_BT_DMT_1440X900P85 { \ 577 .type = V4L2_DV_BT_656_1120, \ 578 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 579 157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \ 580 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 581 } 582 #define V4L2_DV_BT_DMT_1440X900P120_RB { \ 583 .type = V4L2_DV_BT_656_1120, \ 584 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \ 585 182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \ 586 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 587 V4L2_DV_FL_REDUCED_BLANKING) \ 588 } 589 #define V4L2_DV_BT_DMT_1600X900P60_RB { \ 590 .type = V4L2_DV_BT_656_1120, \ 591 V4L2_INIT_BT_TIMINGS(1600, 900, 0, \ 592 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 593 108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \ 594 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ 595 } 596 #define V4L2_DV_BT_DMT_1600X1200P60 { \ 597 .type = V4L2_DV_BT_656_1120, \ 598 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ 599 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 600 162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ 601 V4L2_DV_BT_STD_DMT, 0) \ 602 } 603 #define V4L2_DV_BT_DMT_1600X1200P65 { \ 604 .type = V4L2_DV_BT_656_1120, \ 605 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ 606 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 607 175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ 608 V4L2_DV_BT_STD_DMT, 0) \ 609 } 610 #define V4L2_DV_BT_DMT_1600X1200P70 { \ 611 .type = V4L2_DV_BT_656_1120, \ 612 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ 613 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 614 189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ 615 V4L2_DV_BT_STD_DMT, 0) \ 616 } 617 #define V4L2_DV_BT_DMT_1600X1200P75 { \ 618 .type = V4L2_DV_BT_656_1120, \ 619 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ 620 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 621 202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ 622 V4L2_DV_BT_STD_DMT, 0) \ 623 } 624 #define V4L2_DV_BT_DMT_1600X1200P85 { \ 625 .type = V4L2_DV_BT_656_1120, \ 626 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ 627 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 628 229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ 629 V4L2_DV_BT_STD_DMT, 0) \ 630 } 631 #define V4L2_DV_BT_DMT_1600X1200P120_RB { \ 632 .type = V4L2_DV_BT_656_1120, \ 633 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 634 268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \ 635 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 636 V4L2_DV_FL_REDUCED_BLANKING) \ 637 } 638 #define V4L2_DV_BT_DMT_1680X1050P60_RB { \ 639 .type = V4L2_DV_BT_656_1120, \ 640 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 641 119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \ 642 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 643 V4L2_DV_FL_REDUCED_BLANKING) \ 644 } 645 #define V4L2_DV_BT_DMT_1680X1050P60 { \ 646 .type = V4L2_DV_BT_656_1120, \ 647 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 648 146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \ 649 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 650 } 651 #define V4L2_DV_BT_DMT_1680X1050P75 { \ 652 .type = V4L2_DV_BT_656_1120, \ 653 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 654 187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \ 655 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 656 } 657 #define V4L2_DV_BT_DMT_1680X1050P85 { \ 658 .type = V4L2_DV_BT_656_1120, \ 659 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 660 214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \ 661 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 662 } 663 #define V4L2_DV_BT_DMT_1680X1050P120_RB { \ 664 .type = V4L2_DV_BT_656_1120, \ 665 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 666 245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \ 667 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 668 V4L2_DV_FL_REDUCED_BLANKING) \ 669 } 670 #define V4L2_DV_BT_DMT_1792X1344P60 { \ 671 .type = V4L2_DV_BT_656_1120, \ 672 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \ 673 204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \ 674 V4L2_DV_BT_STD_DMT, 0) \ 675 } 676 #define V4L2_DV_BT_DMT_1792X1344P75 { \ 677 .type = V4L2_DV_BT_656_1120, \ 678 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \ 679 261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \ 680 V4L2_DV_BT_STD_DMT, 0) \ 681 } 682 #define V4L2_DV_BT_DMT_1792X1344P120_RB { \ 683 .type = V4L2_DV_BT_656_1120, \ 684 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \ 685 333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \ 686 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 687 V4L2_DV_FL_REDUCED_BLANKING) \ 688 } 689 #define V4L2_DV_BT_DMT_1856X1392P60 { \ 690 .type = V4L2_DV_BT_656_1120, \ 691 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \ 692 218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \ 693 V4L2_DV_BT_STD_DMT, 0) \ 694 } 695 #define V4L2_DV_BT_DMT_1856X1392P75 { \ 696 .type = V4L2_DV_BT_656_1120, \ 697 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \ 698 288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \ 699 V4L2_DV_BT_STD_DMT, 0) \ 700 } 701 #define V4L2_DV_BT_DMT_1856X1392P120_RB { \ 702 .type = V4L2_DV_BT_656_1120, \ 703 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \ 704 356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \ 705 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 706 V4L2_DV_FL_REDUCED_BLANKING) \ 707 } 708 #define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60 709 #define V4L2_DV_BT_DMT_1920X1200P60_RB { \ 710 .type = V4L2_DV_BT_656_1120, \ 711 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 712 154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \ 713 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 714 V4L2_DV_FL_REDUCED_BLANKING) \ 715 } 716 #define V4L2_DV_BT_DMT_1920X1200P60 { \ 717 .type = V4L2_DV_BT_656_1120, \ 718 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 719 193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \ 720 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 721 } 722 #define V4L2_DV_BT_DMT_1920X1200P75 { \ 723 .type = V4L2_DV_BT_656_1120, \ 724 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 725 245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \ 726 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 727 } 728 #define V4L2_DV_BT_DMT_1920X1200P85 { \ 729 .type = V4L2_DV_BT_656_1120, \ 730 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 731 281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \ 732 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 733 } 734 #define V4L2_DV_BT_DMT_1920X1200P120_RB { \ 735 .type = V4L2_DV_BT_656_1120, \ 736 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 737 317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \ 738 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 739 V4L2_DV_FL_REDUCED_BLANKING) \ 740 } 741 #define V4L2_DV_BT_DMT_1920X1440P60 { \ 742 .type = V4L2_DV_BT_656_1120, \ 743 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \ 744 234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \ 745 V4L2_DV_BT_STD_DMT, 0) \ 746 } 747 #define V4L2_DV_BT_DMT_1920X1440P75 { \ 748 .type = V4L2_DV_BT_656_1120, \ 749 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \ 750 297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \ 751 V4L2_DV_BT_STD_DMT, 0) \ 752 } 753 #define V4L2_DV_BT_DMT_1920X1440P120_RB { \ 754 .type = V4L2_DV_BT_656_1120, \ 755 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \ 756 380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \ 757 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 758 V4L2_DV_FL_REDUCED_BLANKING) \ 759 } 760 #define V4L2_DV_BT_DMT_2048X1152P60_RB { \ 761 .type = V4L2_DV_BT_656_1120, \ 762 V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \ 763 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 764 162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \ 765 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ 766 } 767 #define V4L2_DV_BT_DMT_2560X1600P60_RB { \ 768 .type = V4L2_DV_BT_656_1120, \ 769 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \ 770 268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \ 771 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 772 V4L2_DV_FL_REDUCED_BLANKING) \ 773 } 774 #define V4L2_DV_BT_DMT_2560X1600P60 { \ 775 .type = V4L2_DV_BT_656_1120, \ 776 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 777 348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \ 778 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 779 } 780 #define V4L2_DV_BT_DMT_2560X1600P75 { \ 781 .type = V4L2_DV_BT_656_1120, \ 782 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 783 443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \ 784 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 785 } 786 #define V4L2_DV_BT_DMT_2560X1600P85 { \ 787 .type = V4L2_DV_BT_656_1120, \ 788 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 789 505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \ 790 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 791 } 792 #define V4L2_DV_BT_DMT_2560X1600P120_RB { \ 793 .type = V4L2_DV_BT_656_1120, \ 794 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \ 795 552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \ 796 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 797 V4L2_DV_FL_REDUCED_BLANKING) \ 798 } 799 #define V4L2_DV_BT_DMT_4096X2160P60_RB { \ 800 .type = V4L2_DV_BT_656_1120, \ 801 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 802 556744000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \ 803 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 804 V4L2_DV_FL_REDUCED_BLANKING) \ 805 } 806 #define V4L2_DV_BT_DMT_4096X2160P59_94_RB { \ 807 .type = V4L2_DV_BT_656_1120, \ 808 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 809 556188000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \ 810 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 811 V4L2_DV_FL_REDUCED_BLANKING) \ 812 } 813 #define V4L2_DV_BT_SDI_720X487I60 { \ 814 .type = V4L2_DV_BT_656_1120, \ 815 V4L2_INIT_BT_TIMINGS(720, 487, 1, \ 816 V4L2_DV_HSYNC_POS_POL, \ 817 13500000, 16, 121, 0, 0, 19, 0, 0, 19, 0, \ 818 V4L2_DV_BT_STD_SDI, \ 819 V4L2_DV_FL_FIRST_FIELD_EXTRA_LINE) \ 820 } 821 #endif 822