1<?xml version="1.0" encoding="UTF-8"?> 2<!-- 3Copyright © 2020 Google, Inc. 4 5Permission is hereby granted, free of charge, to any person obtaining a 6copy of this software and associated documentation files (the "Software"), 7to deal in the Software without restriction, including without limitation 8the rights to use, copy, modify, merge, publish, distribute, sublicense, 9and/or sell copies of the Software, and to permit persons to whom the 10Software is furnished to do so, subject to the following conditions: 11 12The above copyright notice and this permission notice (including the next 13paragraph) shall be included in all copies or substantial portions of the 14Software. 15 16THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22SOFTWARE. 23 --> 24 25<isa> 26 27<!-- 28 Cat3 Instructions: three-source ALU instructions 29 --> 30 31<bitset name="#cat3-src" size="13"> 32 <doc> 33 cat3 src1 and src2, some parts are similar to cat2/cat4 src 34 encoding, but a few extra bits trimmed out to squeeze in the 35 3rd src register (dropping (abs), immed encoding, and moving 36 a few other bits elsewhere) 37 </doc> 38 <encode type="struct ir3_register *" case-prefix="REG_"/> 39</bitset> 40 41<bitset name="#cat3-src-gpr" extends="#cat3-src"> 42 <display> 43 {HALF}{SRC} 44 </display> 45 <field name="SRC" low="0" high="7" type="#reg-gpr"/> 46 <pattern low="8" high="12">00000</pattern> 47 <encode> 48 <map name="SRC">src</map> 49 </encode> 50</bitset> 51 52 53<bitset name="#cat3-src-const-or-immed" extends="#cat3-src"> 54 <override> 55 <expr>{IMMED_ENCODING}</expr> 56 <display> 57 {IMMED} 58 </display> 59 <field name="IMMED" low="0" high="11" type="uint"/> 60 <pattern pos="12">1</pattern> 61 </override> 62 63 <display> 64 {HALF}c{CONST}.{SWIZ} 65 </display> 66 <field name="SWIZ" low="0" high="1" type="#swiz"/> 67 <field name="CONST" low="2" high="10" type="uint"/> 68 <pattern low="11" high="12">10</pattern> 69 <encode> 70 <map name="CONST">src->num >> 2</map> 71 <map name="SWIZ">src->num & 0x3</map> 72 <map name="IMMED">src->uim_val</map> 73 </encode> 74</bitset> 75 76<bitset name="#cat3-src-relative" extends="#cat3-src"> 77 <pattern low="11" high="12">01</pattern> 78 <encode> 79 <map name="OFFSET">src->array.offset</map> 80 </encode> 81</bitset> 82 83<bitset name="#cat3-src-relative-gpr" extends="#cat3-src-relative"> 84 <display> 85 {HALF}r<a0.x + {OFFSET}> 86 </display> 87 <field name="OFFSET" low="0" high="9" type="int"/> 88 <pattern pos="10">0</pattern> 89</bitset> 90 91<bitset name="#cat3-src-relative-const" extends="#cat3-src-relative"> 92 <display> 93 {HALF}c<a0.x + {OFFSET}> 94 </display> 95 <field name="OFFSET" low="0" high="9" type="int"/> 96 <pattern pos="10">1</pattern> 97</bitset> 98 99<bitset name="#instruction-cat3-base" extends="#instruction"> 100 <override expr="#cat2-cat3-nop-encoding"> 101 <display> 102 {SY}{SS}{JP}{SAT}(nop{NOP}) {UL}{NAME} {DST_HALF}{DST}, {SRC1_NEG}{SRC1}, {SRC2_NEG}{HALF}{SRC2}, {SRC3_NEG}{SRC3} 103 </display> 104 <derived name="NOP" expr="#cat2-cat3-nop-value" type="uint"/> 105 </override> 106 <display> 107 {SY}{SS}{JP}{SAT}{REPEAT}{UL}{NAME} {DST_HALF}{DST}, {SRC1_NEG}{SRC1_R}{SRC1}, {SRC2_NEG}{SRC2_R}{HALF}{SRC2}, {SRC3_NEG}{SRC3_R}{SRC3} 108 </display> 109 <field name="SRC1_NEG" pos="14" type="bool" display="(neg)"/> 110 <field name="SRC2_R" pos="15" type="bool" display="(r)"/> 111 <field name="SRC3_R" pos="29" type="bool" display="(r)"/> 112 <field name="SRC2_NEG" pos="30" type="bool" display="(neg)"/> 113 <field name="SRC3_NEG" pos="31" type="bool" display="(neg)"/> 114 <field name="DST" low="32" high="39" type="#reg-gpr"/> 115 <field name="REPEAT" low="40" high="41" type="#rptN"/> 116 <field name="SAT" pos="42" type="bool" display="(sat)"/> 117 <field name="SRC1_R" pos="43" type="bool" display="(r)"/> 118 <field name="SS" pos="44" type="bool" display="(ss)"/> 119 <field name="UL" pos="45" type="bool" display="(ul)"/> 120 <field name="DST_CONV" pos="46" type="bool"> 121 <doc> 122 The source precision is determined by the instruction 123 opcode. If {DST_CONV} the result is widened/narrowed 124 to the opposite precision. 125 </doc> 126 </field> 127 <field name="SRC2" low="47" high="54" type="#reg-gpr"/> 128 <!-- opcode, 4 bits --> 129 <field name="JP" pos="59" type="bool" display="(jp)"/> 130 <field name="SY" pos="60" type="bool" display="(sy)"/> 131 <pattern low="61" high="63">011</pattern> <!-- cat3 --> 132 <derived name="HALF" expr="#multisrc-half" type="bool" display="h"/> 133 <derived name="DST_HALF" expr="#dest-half" type="bool" display="h"/> 134 <encode> 135 <map name="SRC1_NEG">!!(src->srcs[0]->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))</map> 136 <map name="SRC1_R">extract_SRC1_R(src)</map> 137 <map name="SRC2_R">extract_SRC2_R(src)</map> 138 <map name="SRC3_R">!!(src->srcs[2]->flags & IR3_REG_R)</map> 139 <map name="SRC2_NEG">!!(src->srcs[1]->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))</map> 140 <map name="SRC3_NEG">!!(src->srcs[2]->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))</map> 141 <map name="SRC1">src->srcs[0]</map> 142 <map name="DST_CONV"> 143 ((src->dsts[0]->num >> 2) == 62) ? 0 : 144 !!((src->srcs[0]->flags ^ src->dsts[0]->flags) & IR3_REG_HALF) 145 </map> 146 </encode> 147</bitset> 148 149<bitset name="#instruction-cat3" extends="#instruction-cat3-base"> 150 <pattern pos="13">0</pattern> 151 152 <derived name="IMMED_ENCODING" expr="#false" type="bool" display="h"/> 153 154 <field name="SRC1" low="0" high="12" type="#cat3-src"> 155 <param name="HALF"/> 156 <param name="IMMED_ENCODING"/> 157 </field> 158 <field name="SRC3" low="16" high="28" type="#cat3-src"> 159 <param name="HALF"/> 160 <param name="IMMED_ENCODING"/> 161 </field> 162</bitset> 163 164<bitset name="#instruction-cat3-alt" extends="#instruction-cat3-base"> 165 <doc> 166 The difference is that this cat3 version does not support plain 167 const registers as src1/src3 but does support inmidiate values. 168 On the other hand it still supports relative gpr and consts. 169 </doc> 170 171 <pattern pos="13">1</pattern> 172 173 <derived name="IMMED_ENCODING" expr="#true" type="bool" display="h"/> 174 175 <field name="SRC1" low="0" high="12" type="#cat3-src"> 176 <param name="HALF"/> 177 <param name="IMMED_ENCODING"/> 178 </field> 179 <field name="SRC3" low="16" high="28" type="#cat3-src"> 180 <param name="HALF"/> 181 <param name="IMMED_ENCODING"/> 182 </field> 183 184 <encode> 185 <map name="SRC3">src->srcs[2]</map> 186 <map name="DST_CONV">false</map> 187 </encode> 188</bitset> 189 190<!-- TODO find shlg.b32 --> 191<bitset name="shlg.b16" extends="#instruction-cat3-alt"> 192 <doc> 193 (src2 << src1) | src3 194 </doc> 195 196 <!-- TODO check older gens --> 197 <gen min="600"/> 198 199 <pattern low="55" high="58">1011</pattern> <!-- OPC --> 200 <derived name="FULL" expr="#false" type="bool"/> 201</bitset> 202 203<bitset name="mad.u16" extends="#instruction-cat3"> 204 <pattern low="55" high="58">0000</pattern> <!-- OPC --> 205 <derived name="FULL" expr="#false" type="bool"/> 206</bitset> 207 208<bitset name="madsh.u16" extends="#instruction-cat3"> 209 <pattern low="55" high="58">0001</pattern> <!-- OPC --> 210 <derived name="FULL" expr="#true" type="bool"/> 211</bitset> 212 213<bitset name="mad.s16" extends="#instruction-cat3"> 214 <pattern low="55" high="58">0010</pattern> <!-- OPC --> 215 <derived name="FULL" expr="#false" type="bool"/> 216</bitset> 217 218<bitset name="madsh.m16" extends="#instruction-cat3"> 219 <pattern low="55" high="58">0011</pattern> <!-- OPC --> 220 <derived name="FULL" expr="#true" type="bool"/> 221</bitset> 222 223<bitset name="mad.u24" extends="#instruction-cat3"> 224 <pattern low="55" high="58">0100</pattern> <!-- OPC --> 225 <derived name="FULL" expr="#true" type="bool"/> 226</bitset> 227 228<bitset name="mad.s24" extends="#instruction-cat3"> 229 <pattern low="55" high="58">0101</pattern> <!-- OPC --> 230 <derived name="FULL" expr="#true" type="bool"/> 231</bitset> 232 233<bitset name="mad.f16" extends="#instruction-cat3"> 234 <pattern low="55" high="58">0110</pattern> <!-- OPC --> 235 <derived name="FULL" expr="#false" type="bool"/> 236</bitset> 237 238<bitset name="mad.f32" extends="#instruction-cat3"> 239 <pattern low="55" high="58">0111</pattern> <!-- OPC --> 240 <derived name="FULL" expr="#true" type="bool"/> 241</bitset> 242 243<bitset name="sel.b16" extends="#instruction-cat3"> 244 <pattern low="55" high="58">1000</pattern> <!-- OPC --> 245 <derived name="FULL" expr="#false" type="bool"/> 246</bitset> 247 248<bitset name="sel.b32" extends="#instruction-cat3"> 249 <pattern low="55" high="58">1001</pattern> <!-- OPC --> 250 <derived name="FULL" expr="#true" type="bool"/> 251</bitset> 252 253<bitset name="sel.s16" extends="#instruction-cat3"> 254 <pattern low="55" high="58">1010</pattern> <!-- OPC --> 255 <derived name="FULL" expr="#false" type="bool"/> 256</bitset> 257 258<bitset name="sel.s32" extends="#instruction-cat3"> 259 <pattern low="55" high="58">1011</pattern> <!-- OPC --> 260 <derived name="FULL" expr="#true" type="bool"/> 261</bitset> 262 263<bitset name="sel.f16" extends="#instruction-cat3"> 264 <pattern low="55" high="58">1100</pattern> <!-- OPC --> 265 <derived name="FULL" expr="#false" type="bool"/> 266</bitset> 267 268<bitset name="sel.f32" extends="#instruction-cat3"> 269 <pattern low="55" high="58">1101</pattern> <!-- OPC --> 270 <derived name="FULL" expr="#true" type="bool"/> 271</bitset> 272 273<bitset name="sad.s16" extends="#instruction-cat3"> 274 <pattern low="55" high="58">1110</pattern> <!-- OPC --> 275 <derived name="FULL" expr="#false" type="bool"/> 276</bitset> 277 278<bitset name="sad.s32" extends="#instruction-cat3"> 279 <pattern low="55" high="58">1111</pattern> <!-- OPC --> 280 <derived name="FULL" expr="#false" type="bool"/> <!-- We think? --> 281</bitset> 282 283</isa> 284