1 /*
2 * Copyright (c) 2012-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 */
26
27 #include "etnaviv_texture_state.h"
28
29 #include "hw/common.xml.h"
30
31 #include "etnaviv_clear_blit.h"
32 #include "etnaviv_context.h"
33 #include "etnaviv_emit.h"
34 #include "etnaviv_format.h"
35 #include "etnaviv_texture.h"
36 #include "etnaviv_translate.h"
37 #include "util/u_inlines.h"
38 #include "util/u_memory.h"
39
40 #include "drm-uapi/drm_fourcc.h"
41
42 struct etna_sampler_state {
43 struct pipe_sampler_state base;
44
45 /* sampler offset +4*sampler, interleave when committing state */
46 uint32_t config0;
47 uint32_t config1;
48 uint32_t config_lod;
49 uint32_t config_3d;
50 uint32_t baselod;
51 unsigned min_lod, max_lod, max_lod_min;
52 };
53
54 static inline struct etna_sampler_state *
etna_sampler_state(struct pipe_sampler_state * samp)55 etna_sampler_state(struct pipe_sampler_state *samp)
56 {
57 return (struct etna_sampler_state *)samp;
58 }
59
60 struct etna_sampler_view {
61 struct pipe_sampler_view base;
62
63 /* sampler offset +4*sampler, interleave when committing state */
64 uint32_t config0;
65 uint32_t config0_mask;
66 uint32_t config1;
67 uint32_t config_3d;
68 uint32_t size;
69 uint32_t log_size;
70 uint32_t astc0;
71 uint32_t linear_stride; /* only LOD0 */
72 struct etna_reloc lod_addr[VIVS_TE_SAMPLER_LOD_ADDR__LEN];
73 unsigned min_lod, max_lod; /* 5.5 fixp */
74
75 struct etna_sampler_ts ts;
76 };
77
78 static inline struct etna_sampler_view *
etna_sampler_view(struct pipe_sampler_view * view)79 etna_sampler_view(struct pipe_sampler_view *view)
80 {
81 return (struct etna_sampler_view *)view;
82 }
83
84 static void *
etna_create_sampler_state_state(struct pipe_context * pipe,const struct pipe_sampler_state * ss)85 etna_create_sampler_state_state(struct pipe_context *pipe,
86 const struct pipe_sampler_state *ss)
87 {
88 struct etna_sampler_state *cs = CALLOC_STRUCT(etna_sampler_state);
89 struct etna_context *ctx = etna_context(pipe);
90 struct etna_screen *screen = ctx->screen;
91 const bool ansio = ss->max_anisotropy > 1;
92 const bool mipmap = ss->min_mip_filter != PIPE_TEX_MIPFILTER_NONE;
93
94 if (!cs)
95 return NULL;
96
97 cs->base = *ss;
98
99 cs->config0 =
100 VIVS_TE_SAMPLER_CONFIG0_UWRAP(translate_texture_wrapmode(ss->wrap_s)) |
101 VIVS_TE_SAMPLER_CONFIG0_VWRAP(translate_texture_wrapmode(ss->wrap_t)) |
102 VIVS_TE_SAMPLER_CONFIG0_MIN(translate_texture_filter(ss->min_img_filter)) |
103 VIVS_TE_SAMPLER_CONFIG0_MIP(translate_texture_mipfilter(ss->min_mip_filter)) |
104 VIVS_TE_SAMPLER_CONFIG0_MAG(translate_texture_filter(ss->mag_img_filter)) |
105 VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY(COND(ansio, etna_log2_fixp55(ss->max_anisotropy)));
106
107 /* ROUND_UV improves precision - but not compatible with NEAREST filter */
108 if (ss->min_img_filter != PIPE_TEX_FILTER_NEAREST &&
109 ss->mag_img_filter != PIPE_TEX_FILTER_NEAREST) {
110 cs->config0 |= VIVS_TE_SAMPLER_CONFIG0_ROUND_UV;
111 }
112
113 cs->config1 = screen->specs.seamless_cube_map ?
114 COND(ss->seamless_cube_map, VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP) : 0;
115
116 cs->config_lod =
117 COND(ss->lod_bias != 0.0 && mipmap, VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE) |
118 VIVS_TE_SAMPLER_LOD_CONFIG_BIAS(etna_float_to_fixp55(ss->lod_bias));
119
120 cs->config_3d =
121 VIVS_TE_SAMPLER_3D_CONFIG_WRAP(translate_texture_wrapmode(ss->wrap_r));
122
123 if (mipmap) {
124 cs->min_lod = etna_float_to_fixp55(ss->min_lod);
125 cs->max_lod = etna_float_to_fixp55(ss->max_lod);
126 } else {
127 /* when not mipmapping, we need to set max/min lod so that always
128 * lowest LOD is selected */
129 cs->min_lod = cs->max_lod = etna_float_to_fixp55(0.0f);
130 }
131
132 /* if max_lod is 0, MIN filter will never be used (GC3000)
133 * when min filter is different from mag filter, we need HW to compute LOD
134 * the workaround is to set max_lod to at least 1
135 */
136 cs->max_lod_min = (ss->min_img_filter != ss->mag_img_filter) ? 1 : 0;
137
138 cs->baselod =
139 COND(ss->compare_mode, VIVS_NTE_SAMPLER_BASELOD_COMPARE_ENABLE) |
140 VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC(translate_texture_compare(ss->compare_func));
141
142 return cs;
143 }
144
145 static void
etna_delete_sampler_state_state(struct pipe_context * pctx,void * ss)146 etna_delete_sampler_state_state(struct pipe_context *pctx, void *ss)
147 {
148 FREE(ss);
149 }
150
151 static struct pipe_sampler_view *
etna_create_sampler_view_state(struct pipe_context * pctx,struct pipe_resource * prsc,const struct pipe_sampler_view * so)152 etna_create_sampler_view_state(struct pipe_context *pctx, struct pipe_resource *prsc,
153 const struct pipe_sampler_view *so)
154 {
155 struct etna_sampler_view *sv = CALLOC_STRUCT(etna_sampler_view);
156 struct etna_context *ctx = etna_context(pctx);
157 struct etna_screen *screen = ctx->screen;
158 const uint32_t format = translate_texture_format(so->format);
159 const bool ext = !!(format & EXT_FORMAT);
160 const bool astc = !!(format & ASTC_FORMAT);
161 const bool srgb = util_format_is_srgb(so->format);
162 const uint32_t swiz = get_texture_swiz(so->format, so->swizzle_r,
163 so->swizzle_g, so->swizzle_b,
164 so->swizzle_a);
165
166 if (!sv)
167 return NULL;
168
169 struct etna_resource *res = etna_texture_handle_incompatible(pctx, prsc);
170 if (!res) {
171 free(sv);
172 return NULL;
173 }
174
175 sv->base = *so;
176 pipe_reference_init(&sv->base.reference, 1);
177 sv->base.texture = NULL;
178 pipe_resource_reference(&sv->base.texture, prsc);
179 sv->base.context = pctx;
180
181 /* merged with sampler state */
182 sv->config0 =
183 VIVS_TE_SAMPLER_CONFIG0_TYPE(translate_texture_target(sv->base.target)) |
184 COND(!ext && !astc, VIVS_TE_SAMPLER_CONFIG0_FORMAT(format));
185 sv->config0_mask = 0xffffffff;
186
187 uint32_t base_height = res->base.height0;
188 uint32_t base_depth = res->base.depth0;
189 bool is_array = false;
190
191 switch (sv->base.target) {
192 case PIPE_TEXTURE_1D:
193 /* use 2D texture with T wrap to repeat for 1D texture
194 * TODO: check if old HW supports 1D texture
195 */
196 sv->config0_mask = ~VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK;
197 sv->config0 &= ~VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK;
198 sv->config0 |=
199 VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_2D) |
200 VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_REPEAT);
201 break;
202 case PIPE_TEXTURE_1D_ARRAY:
203 is_array = true;
204 base_height = res->base.array_size;
205 break;
206 case PIPE_TEXTURE_2D_ARRAY:
207 is_array = true;
208 base_depth = res->base.array_size;
209 break;
210 default:
211 break;
212 }
213
214 if (res->layout == ETNA_LAYOUT_LINEAR && !util_format_is_compressed(so->format)) {
215 sv->config0 |= VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(TEXTURE_ADDRESSING_MODE_LINEAR);
216
217 assert(res->base.last_level == 0);
218 sv->linear_stride = res->levels[0].stride;
219 } else {
220 sv->config0 |= VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(TEXTURE_ADDRESSING_MODE_TILED);
221 sv->linear_stride = 0;
222 }
223
224 sv->config1 |= COND(ext, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(format)) |
225 COND(astc, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(TEXTURE_FORMAT_EXT_ASTC)) |
226 COND(is_array, VIVS_TE_SAMPLER_CONFIG1_TEXTURE_ARRAY) |
227 VIVS_TE_SAMPLER_CONFIG1_HALIGN(res->halign) | swiz;
228 sv->astc0 = COND(astc, VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(format)) |
229 COND(astc && srgb, VIVS_NTE_SAMPLER_ASTC0_ASTC_SRGB) |
230 VIVS_NTE_SAMPLER_ASTC0_UNK8(0xc) |
231 VIVS_NTE_SAMPLER_ASTC0_UNK16(0xc) |
232 VIVS_NTE_SAMPLER_ASTC0_UNK24(0xc);
233 sv->size = VIVS_TE_SAMPLER_SIZE_WIDTH(res->base.width0) |
234 VIVS_TE_SAMPLER_SIZE_HEIGHT(base_height);
235 sv->log_size =
236 VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(etna_log2_fixp55(res->base.width0)) |
237 VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(etna_log2_fixp55(base_height)) |
238 COND(util_format_is_srgb(so->format) && !astc, VIVS_TE_SAMPLER_LOG_SIZE_SRGB) |
239 COND(astc, VIVS_TE_SAMPLER_LOG_SIZE_ASTC);
240 sv->config_3d =
241 VIVS_TE_SAMPLER_3D_CONFIG_DEPTH(base_depth) |
242 VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH(etna_log2_fixp55(base_depth));
243
244 /* Set up levels-of-detail */
245 for (int lod = 0; lod <= res->base.last_level; ++lod) {
246 sv->lod_addr[lod].bo = res->bo;
247 sv->lod_addr[lod].offset = res->levels[lod].offset;
248 sv->lod_addr[lod].flags = ETNA_RELOC_READ;
249 }
250 sv->min_lod = sv->base.u.tex.first_level << 5;
251 sv->max_lod = MIN2(sv->base.u.tex.last_level, res->base.last_level) << 5;
252
253 /* Workaround for npot textures -- it appears that only CLAMP_TO_EDGE is
254 * supported when the appropriate capability is not set. */
255 if (!screen->specs.npot_tex_any_wrap &&
256 (!util_is_power_of_two_or_zero(res->base.width0) ||
257 !util_is_power_of_two_or_zero(res->base.height0))) {
258 sv->config0_mask = ~(VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK |
259 VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK);
260 sv->config0 |=
261 VIVS_TE_SAMPLER_CONFIG0_UWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE) |
262 VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE);
263 }
264
265 return &sv->base;
266 }
267
268 static void
etna_sampler_view_state_destroy(struct pipe_context * pctx,struct pipe_sampler_view * view)269 etna_sampler_view_state_destroy(struct pipe_context *pctx,
270 struct pipe_sampler_view *view)
271 {
272 pipe_resource_reference(&view->texture, NULL);
273 FREE(view);
274 }
275
276 #define EMIT_STATE(state_name, src_value) \
277 etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
278
279 #define EMIT_STATE_FIXP(state_name, src_value) \
280 etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
281
282 #define EMIT_STATE_RELOC(state_name, src_value) \
283 etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
284
285 static void
etna_emit_ts_state(struct etna_context * ctx)286 etna_emit_ts_state(struct etna_context *ctx)
287 {
288 struct etna_cmd_stream *stream = ctx->stream;
289 uint32_t active_samplers = active_samplers_bits(ctx);
290 uint32_t dirty = ctx->dirty;
291 struct etna_coalesce coalesce;
292
293 etna_coalesce_start(stream, &coalesce);
294
295 if (unlikely(dirty & ETNA_DIRTY_SAMPLER_VIEWS)) {
296 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
297 if ((1 << x) & active_samplers) {
298 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
299 /*01720*/ EMIT_STATE(TS_SAMPLER_CONFIG(x), sv->ts.TS_SAMPLER_CONFIG);
300 }
301 }
302 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
303 if ((1 << x) & active_samplers) {
304 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
305 /*01740*/ EMIT_STATE_RELOC(TS_SAMPLER_STATUS_BASE(x), &sv->ts.TS_SAMPLER_STATUS_BASE);
306 }
307 }
308 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
309 if ((1 << x) & active_samplers) {
310 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
311 /*01760*/ EMIT_STATE(TS_SAMPLER_CLEAR_VALUE(x), sv->ts.TS_SAMPLER_CLEAR_VALUE);
312 }
313 }
314 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
315 if ((1 << x) & active_samplers) {
316 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
317 /*01780*/ EMIT_STATE(TS_SAMPLER_CLEAR_VALUE2(x), sv->ts.TS_SAMPLER_CLEAR_VALUE2);
318 }
319 }
320 }
321
322 etna_coalesce_end(stream, &coalesce);
323 }
324
325 static void
etna_emit_new_texture_state(struct etna_context * ctx)326 etna_emit_new_texture_state(struct etna_context *ctx)
327 {
328 struct etna_cmd_stream *stream = ctx->stream;
329 struct etna_screen *screen = ctx->screen;
330 uint32_t active_samplers = active_samplers_bits(ctx);
331 uint32_t dirty = ctx->dirty;
332 struct etna_coalesce coalesce;
333
334 etna_emit_ts_state(ctx);
335
336 etna_coalesce_start(stream, &coalesce);
337
338 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
339 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
340 uint32_t val = 0; /* 0 == sampler inactive */
341
342 /* set active samplers to their configuration value (determined by both
343 * the sampler state and sampler view) */
344 if ((1 << x) & active_samplers) {
345 struct etna_sampler_state *ss = etna_sampler_state(ctx->sampler[x]);
346 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
347
348 val = (ss->config0 & sv->config0_mask) | sv->config0;
349 }
350
351 /*10000*/ EMIT_STATE(NTE_SAMPLER_CONFIG0(x), val);
352 }
353 }
354 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
355 struct etna_sampler_state *ss;
356 struct etna_sampler_view *sv;
357
358 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
359 if ((1 << x) & active_samplers) {
360 sv = etna_sampler_view(ctx->sampler_view[x]);
361 /*10080*/ EMIT_STATE(NTE_SAMPLER_SIZE(x), sv->size);
362 }
363 }
364 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
365 if ((1 << x) & active_samplers) {
366 ss = etna_sampler_state(ctx->sampler[x]);
367 sv = etna_sampler_view(ctx->sampler_view[x]);
368 uint32_t log_size = sv->log_size;
369
370 if (texture_use_int_filter(&sv->base, &ss->base, false))
371 log_size |= VIVS_TE_SAMPLER_LOG_SIZE_INT_FILTER;
372
373 /*10100*/ EMIT_STATE(NTE_SAMPLER_LOG_SIZE(x), log_size);
374 }
375 }
376 }
377 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
378 struct etna_sampler_state *ss;
379 struct etna_sampler_view *sv;
380
381 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
382 if ((1 << x) & active_samplers) {
383 ss = etna_sampler_state(ctx->sampler[x]);
384 sv = etna_sampler_view(ctx->sampler_view[x]);
385
386 unsigned max_lod = MAX2(MIN2(ss->max_lod + sv->min_lod, sv->max_lod), ss->max_lod_min);
387 unsigned min_lod = MIN2(MAX2(ss->min_lod + sv->min_lod, sv->min_lod), max_lod);
388
389 /* min and max lod is determined both by the sampler and the view */
390 /*10180*/ EMIT_STATE(NTE_SAMPLER_LOD_CONFIG(x),
391 ss->config_lod |
392 VIVS_TE_SAMPLER_LOD_CONFIG_MAX(max_lod) |
393 VIVS_TE_SAMPLER_LOD_CONFIG_MIN(min_lod));
394 }
395 }
396 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
397 /* only LOD0 is valid for this register */
398 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
399 if ((1 << x) & active_samplers) {
400 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
401 /*10280*/ EMIT_STATE(NTE_SAMPLER_LINEAR_STRIDE(0, x), sv->linear_stride);
402 }
403 }
404 }
405 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
406 if ((1 << x) & active_samplers) {
407 ss = etna_sampler_state(ctx->sampler[x]);
408 sv = etna_sampler_view(ctx->sampler_view[x]);
409
410 /*10300*/ EMIT_STATE(NTE_SAMPLER_3D_CONFIG(x), ss->config_3d |
411 sv->config_3d);
412 }
413 }
414 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
415 if ((1 << x) & active_samplers) {
416 ss = etna_sampler_state(ctx->sampler[x]);
417 sv = etna_sampler_view(ctx->sampler_view[x]);
418
419 /*10380*/ EMIT_STATE(NTE_SAMPLER_CONFIG1(x), ss->config1 |
420 sv->config1 |
421 COND(sv->ts.enable, VIVS_TE_SAMPLER_CONFIG1_USE_TS));
422 }
423 }
424 }
425 if (unlikely(screen->specs.tex_astc && (dirty & (ETNA_DIRTY_SAMPLER_VIEWS)))) {
426 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
427 if ((1 << x) & active_samplers) {
428 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
429 /*10500*/ EMIT_STATE(NTE_SAMPLER_ASTC0(x), sv->astc0);
430 }
431 }
432 }
433 if (unlikely(dirty & (ETNA_DIRTY_SAMPLERS))) {
434 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
435 if ((1 << x) & active_samplers) {
436 struct etna_sampler_state *ss = etna_sampler_state(ctx->sampler[x]);
437 /*10700*/ EMIT_STATE(NTE_SAMPLER_BASELOD(x), ss->baselod);
438 }
439 }
440 }
441
442 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
443 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
444 if ((1 << x) & active_samplers) {
445 for (int y = 0; y < VIVS_NTE_SAMPLER_ADDR_LOD__LEN; ++y) {
446 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
447 /*10800*/ EMIT_STATE_RELOC(NTE_SAMPLER_ADDR_LOD(x, y), &sv->lod_addr[y]);
448 }
449 }
450 }
451 }
452
453 etna_coalesce_end(stream, &coalesce);
454 }
455
456 /* Emit plain (non-descriptor) texture state */
457 static void
etna_emit_texture_state(struct etna_context * ctx)458 etna_emit_texture_state(struct etna_context *ctx)
459 {
460 struct etna_cmd_stream *stream = ctx->stream;
461 struct etna_screen *screen = ctx->screen;
462 uint32_t active_samplers = active_samplers_bits(ctx);
463 uint32_t dirty = ctx->dirty;
464 struct etna_coalesce coalesce;
465
466 etna_emit_ts_state(ctx);
467
468 etna_coalesce_start(stream, &coalesce);
469
470 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
471 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
472 uint32_t val = 0; /* 0 == sampler inactive */
473
474 /* set active samplers to their configuration value (determined by both
475 * the sampler state and sampler view) */
476 if ((1 << x) & active_samplers) {
477 struct etna_sampler_state *ss = etna_sampler_state(ctx->sampler[x]);
478 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
479
480 val = (ss->config0 & sv->config0_mask) | sv->config0;
481 }
482
483 /*02000*/ EMIT_STATE(TE_SAMPLER_CONFIG0(x), val);
484 }
485 }
486 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
487 struct etna_sampler_state *ss;
488 struct etna_sampler_view *sv;
489
490 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
491 if ((1 << x) & active_samplers) {
492 sv = etna_sampler_view(ctx->sampler_view[x]);
493 /*02040*/ EMIT_STATE(TE_SAMPLER_SIZE(x), sv->size);
494 }
495 }
496 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
497 if ((1 << x) & active_samplers) {
498 ss = etna_sampler_state(ctx->sampler[x]);
499 sv = etna_sampler_view(ctx->sampler_view[x]);
500 uint32_t log_size = sv->log_size;
501
502 if (texture_use_int_filter(&sv->base, &ss->base, false))
503 log_size |= VIVS_TE_SAMPLER_LOG_SIZE_INT_FILTER;
504
505 /*02080*/ EMIT_STATE(TE_SAMPLER_LOG_SIZE(x), log_size);
506 }
507 }
508 }
509 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
510 struct etna_sampler_state *ss;
511 struct etna_sampler_view *sv;
512
513 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
514 if ((1 << x) & active_samplers) {
515 ss = etna_sampler_state(ctx->sampler[x]);
516 sv = etna_sampler_view(ctx->sampler_view[x]);
517
518 unsigned max_lod = MAX2(MIN2(ss->max_lod + sv->min_lod, sv->max_lod), ss->max_lod_min);
519 unsigned min_lod = MIN2(MAX2(ss->min_lod + sv->min_lod, sv->min_lod), max_lod);
520
521 /* min and max lod is determined both by the sampler and the view */
522 /*020C0*/ EMIT_STATE(TE_SAMPLER_LOD_CONFIG(x),
523 ss->config_lod |
524 VIVS_TE_SAMPLER_LOD_CONFIG_MAX(max_lod) |
525 VIVS_TE_SAMPLER_LOD_CONFIG_MIN(min_lod));
526 }
527 }
528 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
529 if ((1 << x) & active_samplers) {
530 ss = etna_sampler_state(ctx->sampler[x]);
531 sv = etna_sampler_view(ctx->sampler_view[x]);
532
533 /*02180*/ EMIT_STATE(TE_SAMPLER_3D_CONFIG(x), ss->config_3d |
534 sv->config_3d);
535 }
536 }
537 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
538 if ((1 << x) & active_samplers) {
539 ss = etna_sampler_state(ctx->sampler[x]);
540 sv = etna_sampler_view(ctx->sampler_view[x]);
541
542 /*021C0*/ EMIT_STATE(TE_SAMPLER_CONFIG1(x), ss->config1 |
543 sv->config1 |
544 COND(sv->ts.enable, VIVS_TE_SAMPLER_CONFIG1_USE_TS));
545 }
546 }
547 }
548 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
549 for (int y = 0; y < VIVS_TE_SAMPLER_LOD_ADDR__LEN; ++y) {
550 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
551 if ((1 << x) & active_samplers) {
552 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
553 /*02400*/ EMIT_STATE_RELOC(TE_SAMPLER_LOD_ADDR(x, y), &sv->lod_addr[y]);
554 }
555 }
556 }
557 }
558 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
559 /* only LOD0 is valid for this register */
560 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
561 if ((1 << x) & active_samplers) {
562 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
563 /*02C00*/ EMIT_STATE(TE_SAMPLER_LINEAR_STRIDE(0, x), sv->linear_stride);
564 }
565 }
566 }
567 if (unlikely(screen->specs.tex_astc && (dirty & (ETNA_DIRTY_SAMPLER_VIEWS)))) {
568 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
569 if ((1 << x) & active_samplers) {
570 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
571 /*10500*/ EMIT_STATE(NTE_SAMPLER_ASTC0(x), sv->astc0);
572 }
573 }
574 }
575
576 etna_coalesce_end(stream, &coalesce);
577 }
578
579 #undef EMIT_STATE
580 #undef EMIT_STATE_FIXP
581 #undef EMIT_STATE_RELOC
582
583 static struct etna_sampler_ts*
etna_ts_for_sampler_view_state(struct pipe_sampler_view * pview)584 etna_ts_for_sampler_view_state(struct pipe_sampler_view *pview)
585 {
586 struct etna_sampler_view *sv = etna_sampler_view(pview);
587 return &sv->ts;
588 }
589
590 void
etna_texture_state_init(struct pipe_context * pctx)591 etna_texture_state_init(struct pipe_context *pctx)
592 {
593 struct etna_context *ctx = etna_context(pctx);
594 DBG("etnaviv: Using state-based texturing");
595 ctx->base.create_sampler_state = etna_create_sampler_state_state;
596 ctx->base.delete_sampler_state = etna_delete_sampler_state_state;
597 ctx->base.create_sampler_view = etna_create_sampler_view_state;
598 ctx->base.sampler_view_destroy = etna_sampler_view_state_destroy;
599 ctx->ts_for_sampler_view = etna_ts_for_sampler_view_state;
600
601 STATIC_ASSERT(VIVS_TE_SAMPLER_LOD_ADDR__LEN == VIVS_NTE_SAMPLER_ADDR_LOD__LEN);
602
603 if (ctx->screen->specs.halti >= 1)
604 ctx->emit_texture_state = etna_emit_new_texture_state;
605 else
606 ctx->emit_texture_state = etna_emit_texture_state;
607 }
608