1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/blend.h"
27 #include "main/bufferobj.h"
28 #include "main/enums.h"
29 #include "main/fbobject.h"
30 #include "main/image.h"
31 #include "main/renderbuffer.h"
32 #include "main/glformats.h"
33
34 #include "brw_blorp.h"
35 #include "brw_context.h"
36 #include "brw_defines.h"
37 #include "brw_meta_util.h"
38 #include "brw_state.h"
39 #include "brw_buffer_objects.h"
40 #include "brw_fbo.h"
41 #include "dev/intel_debug.h"
42
43 #define FILE_DEBUG_FLAG DEBUG_BLORP
44
45 static bool
brw_blorp_lookup_shader(struct blorp_batch * batch,const void * key,uint32_t key_size,uint32_t * kernel_out,void * prog_data_out)46 brw_blorp_lookup_shader(struct blorp_batch *batch,
47 const void *key, uint32_t key_size,
48 uint32_t *kernel_out, void *prog_data_out)
49 {
50 struct brw_context *brw = batch->driver_batch;
51 return brw_search_cache(&brw->cache, BRW_CACHE_BLORP_PROG, key, key_size,
52 kernel_out, prog_data_out, true);
53 }
54
55 static bool
brw_blorp_upload_shader(struct blorp_batch * batch,uint32_t stage,const void * key,uint32_t key_size,const void * kernel,uint32_t kernel_size,const struct brw_stage_prog_data * prog_data,uint32_t prog_data_size,uint32_t * kernel_out,void * prog_data_out)56 brw_blorp_upload_shader(struct blorp_batch *batch, uint32_t stage,
57 const void *key, uint32_t key_size,
58 const void *kernel, uint32_t kernel_size,
59 const struct brw_stage_prog_data *prog_data,
60 uint32_t prog_data_size,
61 uint32_t *kernel_out, void *prog_data_out)
62 {
63 struct brw_context *brw = batch->driver_batch;
64 brw_upload_cache(&brw->cache, BRW_CACHE_BLORP_PROG, key, key_size,
65 kernel, kernel_size, prog_data, prog_data_size,
66 kernel_out, prog_data_out);
67 return true;
68 }
69
70 void
brw_blorp_init(struct brw_context * brw)71 brw_blorp_init(struct brw_context *brw)
72 {
73 const struct intel_device_info *devinfo = &brw->screen->devinfo;
74
75 blorp_init(&brw->blorp, brw, &brw->isl_dev);
76
77 brw->blorp.compiler = brw->screen->compiler;
78
79 switch (devinfo->ver) {
80 case 4:
81 if (devinfo->is_g4x) {
82 brw->blorp.exec = gfx45_blorp_exec;
83 } else {
84 brw->blorp.exec = gfx4_blorp_exec;
85 }
86 break;
87 case 5:
88 brw->blorp.exec = gfx5_blorp_exec;
89 break;
90 case 6:
91 brw->blorp.exec = gfx6_blorp_exec;
92 break;
93 case 7:
94 if (devinfo->is_haswell) {
95 brw->blorp.exec = gfx75_blorp_exec;
96 } else {
97 brw->blorp.exec = gfx7_blorp_exec;
98 }
99 break;
100 case 8:
101 brw->blorp.exec = gfx8_blorp_exec;
102 break;
103 case 9:
104 brw->blorp.exec = gfx9_blorp_exec;
105 break;
106 case 11:
107 brw->blorp.exec = gfx11_blorp_exec;
108 break;
109
110 default:
111 unreachable("Invalid gen");
112 }
113
114 brw->blorp.lookup_shader = brw_blorp_lookup_shader;
115 brw->blorp.upload_shader = brw_blorp_upload_shader;
116 }
117
118 static void
blorp_surf_for_miptree(struct brw_context * brw,struct blorp_surf * surf,const struct brw_mipmap_tree * mt,enum isl_aux_usage aux_usage,bool is_render_target,unsigned * level,unsigned start_layer,unsigned num_layers)119 blorp_surf_for_miptree(struct brw_context *brw,
120 struct blorp_surf *surf,
121 const struct brw_mipmap_tree *mt,
122 enum isl_aux_usage aux_usage,
123 bool is_render_target,
124 unsigned *level,
125 unsigned start_layer, unsigned num_layers)
126 {
127 const struct intel_device_info *devinfo = &brw->screen->devinfo;
128
129 if (mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY) {
130 const unsigned num_samples = mt->surf.samples;
131 for (unsigned i = 0; i < num_layers; i++) {
132 for (unsigned s = 0; s < num_samples; s++) {
133 const unsigned phys_layer = (start_layer + i) * num_samples + s;
134 brw_miptree_check_level_layer(mt, *level, phys_layer);
135 }
136 }
137 } else {
138 for (unsigned i = 0; i < num_layers; i++)
139 brw_miptree_check_level_layer(mt, *level, start_layer + i);
140 }
141
142 *surf = (struct blorp_surf) {
143 .surf = &mt->surf,
144 .addr = (struct blorp_address) {
145 .buffer = mt->bo,
146 .offset = mt->offset,
147 .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
148 .mocs = brw_get_bo_mocs(devinfo, mt->bo),
149 },
150 .aux_usage = aux_usage,
151 .tile_x_sa = mt->level[*level].level_x,
152 .tile_y_sa = mt->level[*level].level_y,
153 };
154
155 if (surf->aux_usage == ISL_AUX_USAGE_HIZ &&
156 !brw_miptree_level_has_hiz(mt, *level))
157 surf->aux_usage = ISL_AUX_USAGE_NONE;
158
159 if (surf->aux_usage != ISL_AUX_USAGE_NONE) {
160 /* We only really need a clear color if we also have an auxiliary
161 * surface. Without one, it does nothing.
162 */
163 surf->clear_color =
164 brw_miptree_get_clear_color(mt, (struct brw_bo **)
165 &surf->clear_color_addr.buffer,
166 &surf->clear_color_addr.offset);
167
168 surf->aux_surf = &mt->aux_buf->surf;
169 surf->aux_addr = (struct blorp_address) {
170 .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
171 .mocs = surf->addr.mocs,
172 };
173
174 surf->aux_addr.buffer = mt->aux_buf->bo;
175 surf->aux_addr.offset = mt->aux_buf->offset;
176 } else {
177 surf->aux_addr = (struct blorp_address) {
178 .buffer = NULL,
179 };
180 memset(&surf->clear_color, 0, sizeof(surf->clear_color));
181 }
182 assert((surf->aux_usage == ISL_AUX_USAGE_NONE) ==
183 (surf->aux_addr.buffer == NULL));
184
185 if (!is_render_target && brw->screen->devinfo.ver == 9)
186 gfx9_apply_single_tex_astc5x5_wa(brw, mt->format, surf->aux_usage);
187
188 /* ISL wants real levels, not offset ones. */
189 *level -= mt->first_level;
190 }
191
192 static bool
brw_blorp_supports_dst_format(struct brw_context * brw,mesa_format format)193 brw_blorp_supports_dst_format(struct brw_context *brw, mesa_format format)
194 {
195 /* If it's renderable, it's definitely supported. */
196 if (brw->mesa_format_supports_render[format])
197 return true;
198
199 /* BLORP can't compress anything */
200 if (_mesa_is_format_compressed(format))
201 return false;
202
203 /* No exotic formats such as GL_LUMINANCE_ALPHA */
204 if (_mesa_get_format_bits(format, GL_RED_BITS) == 0 &&
205 _mesa_get_format_bits(format, GL_DEPTH_BITS) == 0 &&
206 _mesa_get_format_bits(format, GL_STENCIL_BITS) == 0)
207 return false;
208
209 return true;
210 }
211
212 static enum isl_format
brw_blorp_to_isl_format(struct brw_context * brw,mesa_format format,bool is_render_target)213 brw_blorp_to_isl_format(struct brw_context *brw, mesa_format format,
214 bool is_render_target)
215 {
216 switch (format) {
217 case MESA_FORMAT_NONE:
218 return ISL_FORMAT_UNSUPPORTED;
219 case MESA_FORMAT_S_UINT8:
220 return ISL_FORMAT_R8_UINT;
221 case MESA_FORMAT_Z24_UNORM_X8_UINT:
222 case MESA_FORMAT_Z24_UNORM_S8_UINT:
223 return ISL_FORMAT_R24_UNORM_X8_TYPELESS;
224 case MESA_FORMAT_Z_FLOAT32:
225 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
226 return ISL_FORMAT_R32_FLOAT;
227 case MESA_FORMAT_Z_UNORM16:
228 return ISL_FORMAT_R16_UNORM;
229 default:
230 if (is_render_target) {
231 assert(brw_blorp_supports_dst_format(brw, format));
232 if (brw->mesa_format_supports_render[format]) {
233 return brw->mesa_to_isl_render_format[format];
234 } else {
235 return brw_isl_format_for_mesa_format(format);
236 }
237 } else {
238 /* Some destinations (is_render_target == true) are supported by
239 * blorp even though we technically can't render to them.
240 */
241 return brw_isl_format_for_mesa_format(format);
242 }
243 }
244 }
245
246 /**
247 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gfx7.5+
248 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
249 *
250 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
251 * 0 1 2 3 4 5
252 * 4 5 6 7 0 1
253 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
254 *
255 * which is simply adding 4 then modding by 8 (or anding with 7).
256 *
257 * We then may need to apply workarounds for textureGather hardware bugs.
258 */
259 static enum isl_channel_select
swizzle_to_scs(GLenum swizzle)260 swizzle_to_scs(GLenum swizzle)
261 {
262 return (enum isl_channel_select)((swizzle + 4) & 7);
263 }
264
265 /**
266 * Note: if the src (or dst) is a 2D multisample array texture on Gfx7+ using
267 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
268 * the physical layer holding sample 0. So, for example, if
269 * src_mt->surf.samples == 4, then logical layer n corresponds to src_layer ==
270 * 4*n.
271 */
272 void
brw_blorp_blit_miptrees(struct brw_context * brw,struct brw_mipmap_tree * src_mt,unsigned src_level,unsigned src_layer,mesa_format src_format,int src_swizzle,struct brw_mipmap_tree * dst_mt,unsigned dst_level,unsigned dst_layer,mesa_format dst_format,float src_x0,float src_y0,float src_x1,float src_y1,float dst_x0,float dst_y0,float dst_x1,float dst_y1,GLenum gl_filter,bool mirror_x,bool mirror_y,bool decode_srgb,bool encode_srgb)273 brw_blorp_blit_miptrees(struct brw_context *brw,
274 struct brw_mipmap_tree *src_mt,
275 unsigned src_level, unsigned src_layer,
276 mesa_format src_format, int src_swizzle,
277 struct brw_mipmap_tree *dst_mt,
278 unsigned dst_level, unsigned dst_layer,
279 mesa_format dst_format,
280 float src_x0, float src_y0,
281 float src_x1, float src_y1,
282 float dst_x0, float dst_y0,
283 float dst_x1, float dst_y1,
284 GLenum gl_filter, bool mirror_x, bool mirror_y,
285 bool decode_srgb, bool encode_srgb)
286 {
287 const struct intel_device_info *devinfo = &brw->screen->devinfo;
288
289 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f) "
290 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
291 __func__,
292 src_mt->surf.samples, _mesa_get_format_name(src_mt->format), src_mt,
293 src_level, src_layer, src_x0, src_y0, src_x1, src_y1,
294 dst_mt->surf.samples, _mesa_get_format_name(dst_mt->format), dst_mt,
295 dst_level, dst_layer, dst_x0, dst_y0, dst_x1, dst_y1,
296 mirror_x, mirror_y);
297
298 if (src_format == MESA_FORMAT_NONE)
299 src_format = src_mt->format;
300
301 if (dst_format == MESA_FORMAT_NONE)
302 dst_format = dst_mt->format;
303
304 if (!decode_srgb)
305 src_format = _mesa_get_srgb_format_linear(src_format);
306
307 if (!encode_srgb)
308 dst_format = _mesa_get_srgb_format_linear(dst_format);
309
310 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
311 * texture, the above code configures the source format for L32_FLOAT or
312 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
313 * the SAMPLE message appears to handle multisampled L32_FLOAT and
314 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
315 * around the problem by using a source format of R32_FLOAT. This
316 * shouldn't affect rendering correctness, since the destination format is
317 * R32_FLOAT, so only the contents of the red channel matters.
318 */
319 if (devinfo->ver == 6 &&
320 src_mt->surf.samples > 1 && dst_mt->surf.samples <= 1 &&
321 src_mt->format == dst_mt->format &&
322 (dst_format == MESA_FORMAT_L_FLOAT32 ||
323 dst_format == MESA_FORMAT_I_FLOAT32)) {
324 src_format = dst_format = MESA_FORMAT_R_FLOAT32;
325 }
326
327 enum blorp_filter blorp_filter;
328 if (fabsf(dst_x1 - dst_x0) == fabsf(src_x1 - src_x0) &&
329 fabsf(dst_y1 - dst_y0) == fabsf(src_y1 - src_y0)) {
330 if (src_mt->surf.samples > 1 && dst_mt->surf.samples <= 1) {
331 /* From the OpenGL ES 3.2 specification, section 16.2.1:
332 *
333 * "If the read framebuffer is multisampled (its effective value
334 * of SAMPLE_BUFFERS is one) and the draw framebuffer is not (its
335 * value of SAMPLE_BUFFERS is zero), the samples corresponding to
336 * each pixel location in the source are converted to a single
337 * sample before being written to the destination. The filter
338 * parameter is ignored. If the source formats are integer types
339 * or stencil values, a single sample’s value is selected for each
340 * pixel. If the source formats are floating-point or normalized
341 * types, the sample values for each pixel are resolved in an
342 * implementation-dependent manner. If the source formats are
343 * depth values, sample values are resolved in an implementation-
344 * dependent manner where the result will be between the minimum
345 * and maximum depth values in the pixel."
346 *
347 * For depth and stencil resolves, we choose to always use the value
348 * at sample 0.
349 */
350 GLenum base_format = _mesa_get_format_base_format(src_mt->format);
351 if (base_format == GL_DEPTH_COMPONENT ||
352 base_format == GL_STENCIL_INDEX ||
353 base_format == GL_DEPTH_STENCIL ||
354 _mesa_is_format_integer(src_mt->format)) {
355 /* The OpenGL ES 3.2 spec says:
356 *
357 * "If the source formats are integer types or stencil values,
358 * a single sample's value is selected for each pixel."
359 *
360 * Just take sample 0 in this case.
361 */
362 blorp_filter = BLORP_FILTER_SAMPLE_0;
363 } else {
364 blorp_filter = BLORP_FILTER_AVERAGE;
365 }
366 } else {
367 /* From the OpenGL 4.6 specification, section 18.3.1:
368 *
369 * "If the source and destination dimensions are identical, no
370 * filtering is applied."
371 *
372 * Using BLORP_FILTER_NONE will also handle the upsample case by
373 * replicating the one value in the source to all values in the
374 * destination.
375 */
376 blorp_filter = BLORP_FILTER_NONE;
377 }
378 } else if (gl_filter == GL_LINEAR ||
379 gl_filter == GL_SCALED_RESOLVE_FASTEST_EXT ||
380 gl_filter == GL_SCALED_RESOLVE_NICEST_EXT) {
381 blorp_filter = BLORP_FILTER_BILINEAR;
382 } else {
383 blorp_filter = BLORP_FILTER_NEAREST;
384 }
385
386 enum isl_format src_isl_format =
387 brw_blorp_to_isl_format(brw, src_format, false);
388 enum isl_aux_usage src_aux_usage =
389 brw_miptree_texture_aux_usage(brw, src_mt, src_isl_format,
390 0 /* The astc5x5 WA isn't needed */);
391 /* We do format workarounds for some depth formats so we can't reliably
392 * sample with HiZ. One of these days, we should fix that.
393 */
394 if (src_aux_usage == ISL_AUX_USAGE_HIZ && src_mt->format != src_format)
395 src_aux_usage = ISL_AUX_USAGE_NONE;
396 const bool src_clear_supported =
397 src_aux_usage != ISL_AUX_USAGE_NONE && src_mt->format == src_format;
398 brw_miptree_prepare_access(brw, src_mt, src_level, 1, src_layer, 1,
399 src_aux_usage, src_clear_supported);
400
401 enum isl_format dst_isl_format =
402 brw_blorp_to_isl_format(brw, dst_format, true);
403 enum isl_aux_usage dst_aux_usage =
404 brw_miptree_render_aux_usage(brw, dst_mt, dst_isl_format, false, false);
405 const bool dst_clear_supported = dst_aux_usage != ISL_AUX_USAGE_NONE;
406 brw_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1,
407 dst_aux_usage, dst_clear_supported);
408
409 struct blorp_surf src_surf, dst_surf;
410 blorp_surf_for_miptree(brw, &src_surf, src_mt, src_aux_usage, false,
411 &src_level, src_layer, 1);
412 blorp_surf_for_miptree(brw, &dst_surf, dst_mt, dst_aux_usage, true,
413 &dst_level, dst_layer, 1);
414
415 struct isl_swizzle src_isl_swizzle = {
416 .r = swizzle_to_scs(GET_SWZ(src_swizzle, 0)),
417 .g = swizzle_to_scs(GET_SWZ(src_swizzle, 1)),
418 .b = swizzle_to_scs(GET_SWZ(src_swizzle, 2)),
419 .a = swizzle_to_scs(GET_SWZ(src_swizzle, 3)),
420 };
421
422 struct blorp_batch batch;
423 blorp_batch_init(&brw->blorp, &batch, brw, 0);
424 blorp_blit(&batch, &src_surf, src_level, src_layer,
425 src_isl_format, src_isl_swizzle,
426 &dst_surf, dst_level, dst_layer,
427 dst_isl_format, ISL_SWIZZLE_IDENTITY,
428 src_x0, src_y0, src_x1, src_y1,
429 dst_x0, dst_y0, dst_x1, dst_y1,
430 blorp_filter, mirror_x, mirror_y);
431 blorp_batch_finish(&batch);
432
433 brw_miptree_finish_write(brw, dst_mt, dst_level, dst_layer, 1,
434 dst_aux_usage);
435 }
436
437 void
brw_blorp_copy_miptrees(struct brw_context * brw,struct brw_mipmap_tree * src_mt,unsigned src_level,unsigned src_layer,struct brw_mipmap_tree * dst_mt,unsigned dst_level,unsigned dst_layer,unsigned src_x,unsigned src_y,unsigned dst_x,unsigned dst_y,unsigned src_width,unsigned src_height)438 brw_blorp_copy_miptrees(struct brw_context *brw,
439 struct brw_mipmap_tree *src_mt,
440 unsigned src_level, unsigned src_layer,
441 struct brw_mipmap_tree *dst_mt,
442 unsigned dst_level, unsigned dst_layer,
443 unsigned src_x, unsigned src_y,
444 unsigned dst_x, unsigned dst_y,
445 unsigned src_width, unsigned src_height)
446 {
447 DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
448 "to %dx %s mt %p %d %d (%d,%d)\n",
449 __func__,
450 src_mt->surf.samples, _mesa_get_format_name(src_mt->format), src_mt,
451 src_level, src_layer, src_x, src_y, src_width, src_height,
452 dst_mt->surf.samples, _mesa_get_format_name(dst_mt->format), dst_mt,
453 dst_level, dst_layer, dst_x, dst_y);
454
455 enum isl_aux_usage src_aux_usage, dst_aux_usage;
456 bool src_clear_supported, dst_clear_supported;
457
458 switch (src_mt->aux_usage) {
459 case ISL_AUX_USAGE_HIZ:
460 if (brw_miptree_sample_with_hiz(brw, src_mt)) {
461 src_aux_usage = src_mt->aux_usage;
462 src_clear_supported = true;
463 } else {
464 src_aux_usage = ISL_AUX_USAGE_NONE;
465 src_clear_supported = false;
466 }
467 break;
468 case ISL_AUX_USAGE_MCS:
469 case ISL_AUX_USAGE_CCS_E:
470 src_aux_usage = src_mt->aux_usage;
471 src_clear_supported = false;
472 break;
473 default:
474 src_aux_usage = ISL_AUX_USAGE_NONE;
475 src_clear_supported = false;
476 break;
477 }
478
479 switch (dst_mt->aux_usage) {
480 case ISL_AUX_USAGE_MCS:
481 case ISL_AUX_USAGE_CCS_E:
482 dst_aux_usage = dst_mt->aux_usage;
483 dst_clear_supported = false;
484 break;
485 default:
486 dst_aux_usage = ISL_AUX_USAGE_NONE;
487 dst_clear_supported = false;
488 break;
489 }
490
491 brw_miptree_prepare_access(brw, src_mt, src_level, 1, src_layer, 1,
492 src_aux_usage, src_clear_supported);
493 brw_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1,
494 dst_aux_usage, dst_clear_supported);
495
496 struct blorp_surf src_surf, dst_surf;
497 blorp_surf_for_miptree(brw, &src_surf, src_mt, src_aux_usage, false,
498 &src_level, src_layer, 1);
499 blorp_surf_for_miptree(brw, &dst_surf, dst_mt, dst_aux_usage, true,
500 &dst_level, dst_layer, 1);
501
502 /* The hardware seems to have issues with having a two different format
503 * views of the same texture in the sampler cache at the same time. It's
504 * unclear exactly what the issue is but it hurts glCopyImageSubData
505 * particularly badly because it does a lot of format reinterprets. We
506 * badly need better understanding of the issue and a better fix but this
507 * works for now and fixes CTS tests.
508 *
509 * TODO: Remove this hack!
510 */
511 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL |
512 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
513
514 struct blorp_batch batch;
515 blorp_batch_init(&brw->blorp, &batch, brw, 0);
516 blorp_copy(&batch, &src_surf, src_level, src_layer,
517 &dst_surf, dst_level, dst_layer,
518 src_x, src_y, dst_x, dst_y, src_width, src_height);
519 blorp_batch_finish(&batch);
520
521 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL |
522 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
523
524 brw_miptree_finish_write(brw, dst_mt, dst_level, dst_layer, 1,
525 dst_aux_usage);
526 }
527
528 void
brw_blorp_copy_buffers(struct brw_context * brw,struct brw_bo * src_bo,unsigned src_offset,struct brw_bo * dst_bo,unsigned dst_offset,unsigned size)529 brw_blorp_copy_buffers(struct brw_context *brw,
530 struct brw_bo *src_bo,
531 unsigned src_offset,
532 struct brw_bo *dst_bo,
533 unsigned dst_offset,
534 unsigned size)
535 {
536 DBG("%s %d bytes from %p[%d] to %p[%d]",
537 __func__, size, src_bo, src_offset, dst_bo, dst_offset);
538
539 struct blorp_batch batch;
540 struct blorp_address src = { .buffer = src_bo, .offset = src_offset };
541 struct blorp_address dst = { .buffer = dst_bo, .offset = dst_offset };
542
543 blorp_batch_init(&brw->blorp, &batch, brw, 0);
544 blorp_buffer_copy(&batch, src, dst, size);
545 blorp_batch_finish(&batch);
546 }
547
548
549 static struct brw_mipmap_tree *
find_miptree(GLbitfield buffer_bit,struct brw_renderbuffer * irb)550 find_miptree(GLbitfield buffer_bit, struct brw_renderbuffer *irb)
551 {
552 struct brw_mipmap_tree *mt = irb->mt;
553 if (buffer_bit == GL_STENCIL_BUFFER_BIT && mt->stencil_mt)
554 mt = mt->stencil_mt;
555 return mt;
556 }
557
558 static int
blorp_get_texture_swizzle(const struct brw_renderbuffer * irb)559 blorp_get_texture_swizzle(const struct brw_renderbuffer *irb)
560 {
561 return irb->Base.Base._BaseFormat == GL_RGB ?
562 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE) :
563 SWIZZLE_XYZW;
564 }
565
566 static void
do_blorp_blit(struct brw_context * brw,GLbitfield buffer_bit,struct brw_renderbuffer * src_irb,mesa_format src_format,struct brw_renderbuffer * dst_irb,mesa_format dst_format,GLfloat srcX0,GLfloat srcY0,GLfloat srcX1,GLfloat srcY1,GLfloat dstX0,GLfloat dstY0,GLfloat dstX1,GLfloat dstY1,GLenum filter,bool mirror_x,bool mirror_y)567 do_blorp_blit(struct brw_context *brw, GLbitfield buffer_bit,
568 struct brw_renderbuffer *src_irb, mesa_format src_format,
569 struct brw_renderbuffer *dst_irb, mesa_format dst_format,
570 GLfloat srcX0, GLfloat srcY0, GLfloat srcX1, GLfloat srcY1,
571 GLfloat dstX0, GLfloat dstY0, GLfloat dstX1, GLfloat dstY1,
572 GLenum filter, bool mirror_x, bool mirror_y)
573 {
574 const struct gl_context *ctx = &brw->ctx;
575
576 /* Find source/dst miptrees */
577 struct brw_mipmap_tree *src_mt = find_miptree(buffer_bit, src_irb);
578 struct brw_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_irb);
579
580 const bool do_srgb = ctx->Color.sRGBEnabled;
581
582 /* Do the blit */
583 brw_blorp_blit_miptrees(brw,
584 src_mt, src_irb->mt_level, src_irb->mt_layer,
585 src_format, blorp_get_texture_swizzle(src_irb),
586 dst_mt, dst_irb->mt_level, dst_irb->mt_layer,
587 dst_format,
588 srcX0, srcY0, srcX1, srcY1,
589 dstX0, dstY0, dstX1, dstY1,
590 filter, mirror_x, mirror_y,
591 do_srgb, do_srgb);
592
593 dst_irb->need_downsample = true;
594 }
595
596 static bool
try_blorp_blit(struct brw_context * brw,const struct gl_framebuffer * read_fb,const struct gl_framebuffer * draw_fb,GLfloat srcX0,GLfloat srcY0,GLfloat srcX1,GLfloat srcY1,GLfloat dstX0,GLfloat dstY0,GLfloat dstX1,GLfloat dstY1,GLenum filter,GLbitfield buffer_bit)597 try_blorp_blit(struct brw_context *brw,
598 const struct gl_framebuffer *read_fb,
599 const struct gl_framebuffer *draw_fb,
600 GLfloat srcX0, GLfloat srcY0, GLfloat srcX1, GLfloat srcY1,
601 GLfloat dstX0, GLfloat dstY0, GLfloat dstX1, GLfloat dstY1,
602 GLenum filter, GLbitfield buffer_bit)
603 {
604 const struct intel_device_info *devinfo = &brw->screen->devinfo;
605 struct gl_context *ctx = &brw->ctx;
606
607 /* Sync up the state of window system buffers. We need to do this before
608 * we go looking for the buffers.
609 */
610 brw_prepare_render(brw);
611
612 bool mirror_x, mirror_y;
613 if (brw_meta_mirror_clip_and_scissor(ctx, read_fb, draw_fb,
614 &srcX0, &srcY0, &srcX1, &srcY1,
615 &dstX0, &dstY0, &dstX1, &dstY1,
616 &mirror_x, &mirror_y))
617 return true;
618
619 /* Find buffers */
620 struct brw_renderbuffer *src_irb;
621 struct brw_renderbuffer *dst_irb;
622 struct brw_mipmap_tree *src_mt;
623 struct brw_mipmap_tree *dst_mt;
624 switch (buffer_bit) {
625 case GL_COLOR_BUFFER_BIT:
626 src_irb = brw_renderbuffer(read_fb->_ColorReadBuffer);
627 for (unsigned i = 0; i < draw_fb->_NumColorDrawBuffers; ++i) {
628 dst_irb = brw_renderbuffer(draw_fb->_ColorDrawBuffers[i]);
629 if (dst_irb)
630 do_blorp_blit(brw, buffer_bit,
631 src_irb, src_irb->Base.Base.Format,
632 dst_irb, dst_irb->Base.Base.Format,
633 srcX0, srcY0, srcX1, srcY1,
634 dstX0, dstY0, dstX1, dstY1,
635 filter, mirror_x, mirror_y);
636 }
637 break;
638 case GL_DEPTH_BUFFER_BIT:
639 src_irb =
640 brw_renderbuffer(read_fb->Attachment[BUFFER_DEPTH].Renderbuffer);
641 dst_irb =
642 brw_renderbuffer(draw_fb->Attachment[BUFFER_DEPTH].Renderbuffer);
643 src_mt = find_miptree(buffer_bit, src_irb);
644 dst_mt = find_miptree(buffer_bit, dst_irb);
645
646 /* We also can't handle any combined depth-stencil formats because we
647 * have to reinterpret as a color format.
648 */
649 if (_mesa_get_format_base_format(src_mt->format) == GL_DEPTH_STENCIL ||
650 _mesa_get_format_base_format(dst_mt->format) == GL_DEPTH_STENCIL)
651 return false;
652
653 do_blorp_blit(brw, buffer_bit, src_irb, MESA_FORMAT_NONE,
654 dst_irb, MESA_FORMAT_NONE, srcX0, srcY0,
655 srcX1, srcY1, dstX0, dstY0, dstX1, dstY1,
656 filter, mirror_x, mirror_y);
657 break;
658 case GL_STENCIL_BUFFER_BIT:
659 /* Blorp doesn't support combined depth stencil which is all we have
660 * prior to gfx6.
661 */
662 if (devinfo->ver < 6)
663 return false;
664
665 src_irb =
666 brw_renderbuffer(read_fb->Attachment[BUFFER_STENCIL].Renderbuffer);
667 dst_irb =
668 brw_renderbuffer(draw_fb->Attachment[BUFFER_STENCIL].Renderbuffer);
669 do_blorp_blit(brw, buffer_bit, src_irb, MESA_FORMAT_NONE,
670 dst_irb, MESA_FORMAT_NONE, srcX0, srcY0,
671 srcX1, srcY1, dstX0, dstY0, dstX1, dstY1,
672 filter, mirror_x, mirror_y);
673 break;
674 default:
675 unreachable("not reached");
676 }
677
678 return true;
679 }
680
681 static void
apply_y_flip(int * y0,int * y1,int height)682 apply_y_flip(int *y0, int *y1, int height)
683 {
684 int tmp = height - *y0;
685 *y0 = height - *y1;
686 *y1 = tmp;
687 }
688
689 bool
brw_blorp_copytexsubimage(struct brw_context * brw,struct gl_renderbuffer * src_rb,struct gl_texture_image * dst_image,int slice,int srcX0,int srcY0,int dstX0,int dstY0,int width,int height)690 brw_blorp_copytexsubimage(struct brw_context *brw,
691 struct gl_renderbuffer *src_rb,
692 struct gl_texture_image *dst_image,
693 int slice,
694 int srcX0, int srcY0,
695 int dstX0, int dstY0,
696 int width, int height)
697 {
698 struct gl_context *ctx = &brw->ctx;
699 struct brw_renderbuffer *src_irb = brw_renderbuffer(src_rb);
700 struct brw_texture_image *intel_image = brw_texture_image(dst_image);
701
702 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
703 if (brw->ctx._ImageTransferState)
704 return false;
705
706 /* Sync up the state of window system buffers. We need to do this before
707 * we go looking at the src renderbuffer's miptree.
708 */
709 brw_prepare_render(brw);
710
711 struct brw_mipmap_tree *src_mt = src_irb->mt;
712 struct brw_mipmap_tree *dst_mt = intel_image->mt;
713
714 /* We can't handle any combined depth-stencil formats because we have to
715 * reinterpret as a color format.
716 */
717 if (_mesa_get_format_base_format(src_mt->format) == GL_DEPTH_STENCIL ||
718 _mesa_get_format_base_format(dst_mt->format) == GL_DEPTH_STENCIL)
719 return false;
720
721 if (!brw_blorp_supports_dst_format(brw, dst_image->TexFormat))
722 return false;
723
724 /* Source clipping shouldn't be necessary, since copytexsubimage (in
725 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
726 * takes care of it.
727 *
728 * Destination clipping shouldn't be necessary since the restrictions on
729 * glCopyTexSubImage prevent the user from specifying a destination rectangle
730 * that falls outside the bounds of the destination texture.
731 * See error_check_subtexture_dimensions().
732 */
733
734 int srcY1 = srcY0 + height;
735 int srcX1 = srcX0 + width;
736 int dstX1 = dstX0 + width;
737 int dstY1 = dstY0 + height;
738
739 /* Account for the fact that in the system framebuffer, the origin is at
740 * the lower left.
741 */
742 bool mirror_y = ctx->ReadBuffer->FlipY;
743 if (mirror_y)
744 apply_y_flip(&srcY0, &srcY1, src_rb->Height);
745
746 /* Account for face selection and texture view MinLayer */
747 int dst_slice = slice + dst_image->TexObject->Attrib.MinLayer + dst_image->Face;
748 int dst_level = dst_image->Level + dst_image->TexObject->Attrib.MinLevel;
749
750 brw_blorp_blit_miptrees(brw,
751 src_mt, src_irb->mt_level, src_irb->mt_layer,
752 src_rb->Format, blorp_get_texture_swizzle(src_irb),
753 dst_mt, dst_level, dst_slice,
754 dst_image->TexFormat,
755 srcX0, srcY0, srcX1, srcY1,
756 dstX0, dstY0, dstX1, dstY1,
757 GL_NEAREST, false, mirror_y,
758 false, false);
759
760 /* If we're copying to a packed depth stencil texture and the source
761 * framebuffer has separate stencil, we need to also copy the stencil data
762 * over.
763 */
764 src_rb = ctx->ReadBuffer->Attachment[BUFFER_STENCIL].Renderbuffer;
765 if (_mesa_get_format_bits(dst_image->TexFormat, GL_STENCIL_BITS) > 0 &&
766 src_rb != NULL) {
767 src_irb = brw_renderbuffer(src_rb);
768 src_mt = src_irb->mt;
769
770 if (src_mt->stencil_mt)
771 src_mt = src_mt->stencil_mt;
772 if (dst_mt->stencil_mt)
773 dst_mt = dst_mt->stencil_mt;
774
775 if (src_mt != dst_mt) {
776 brw_blorp_blit_miptrees(brw,
777 src_mt, src_irb->mt_level, src_irb->mt_layer,
778 src_mt->format,
779 blorp_get_texture_swizzle(src_irb),
780 dst_mt, dst_level, dst_slice,
781 dst_mt->format,
782 srcX0, srcY0, srcX1, srcY1,
783 dstX0, dstY0, dstX1, dstY1,
784 GL_NEAREST, false, mirror_y,
785 false, false);
786 }
787 }
788
789 return true;
790 }
791
792
793 GLbitfield
brw_blorp_framebuffer(struct brw_context * brw,struct gl_framebuffer * readFb,struct gl_framebuffer * drawFb,GLint srcX0,GLint srcY0,GLint srcX1,GLint srcY1,GLint dstX0,GLint dstY0,GLint dstX1,GLint dstY1,GLbitfield mask,GLenum filter)794 brw_blorp_framebuffer(struct brw_context *brw,
795 struct gl_framebuffer *readFb,
796 struct gl_framebuffer *drawFb,
797 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
798 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
799 GLbitfield mask, GLenum filter)
800 {
801 static GLbitfield buffer_bits[] = {
802 GL_COLOR_BUFFER_BIT,
803 GL_DEPTH_BUFFER_BIT,
804 GL_STENCIL_BUFFER_BIT,
805 };
806
807 for (unsigned int i = 0; i < ARRAY_SIZE(buffer_bits); ++i) {
808 if ((mask & buffer_bits[i]) &&
809 try_blorp_blit(brw, readFb, drawFb,
810 srcX0, srcY0, srcX1, srcY1,
811 dstX0, dstY0, dstX1, dstY1,
812 filter, buffer_bits[i])) {
813 mask &= ~buffer_bits[i];
814 }
815 }
816
817 /* try_blorp_blit should always be successful for color blits. */
818 assert(!(mask & GL_COLOR_BUFFER_BIT));
819 return mask;
820 }
821
822 static struct brw_bo *
blorp_get_client_bo(struct brw_context * brw,unsigned w,unsigned h,unsigned d,GLenum target,GLenum format,GLenum type,const void * pixels,const struct gl_pixelstore_attrib * packing,uint32_t * offset_out,uint32_t * row_stride_out,uint32_t * image_stride_out,bool read_only)823 blorp_get_client_bo(struct brw_context *brw,
824 unsigned w, unsigned h, unsigned d,
825 GLenum target, GLenum format, GLenum type,
826 const void *pixels,
827 const struct gl_pixelstore_attrib *packing,
828 uint32_t *offset_out, uint32_t *row_stride_out,
829 uint32_t *image_stride_out, bool read_only)
830 {
831 /* Account for SKIP_PIXELS, SKIP_ROWS, ALIGNMENT, and SKIP_IMAGES */
832 const GLuint dims = _mesa_get_texture_dimensions(target);
833 const uint32_t first_pixel = _mesa_image_offset(dims, packing, w, h,
834 format, type, 0, 0, 0);
835 const uint32_t last_pixel = _mesa_image_offset(dims, packing, w, h,
836 format, type,
837 d - 1, h - 1, w);
838 const uint32_t stride = _mesa_image_row_stride(packing, w, format, type);
839 const uint32_t size = last_pixel - first_pixel;
840
841 *row_stride_out = stride;
842 *image_stride_out = _mesa_image_image_stride(packing, w, h, format, type);
843
844 if (packing->BufferObj) {
845 const uint32_t offset = first_pixel + (intptr_t)pixels;
846
847 if (!read_only) {
848 const int32_t cpp = _mesa_bytes_per_pixel(format, type);
849 assert(cpp > 0);
850
851 if ((offset % cpp) || (stride % cpp)) {
852 perf_debug("Bad PBO alignment; fallback to CPU mapping\n");
853 return NULL;
854 }
855 }
856
857 /* This is a user-provided PBO. We just need to get the BO out */
858 struct brw_buffer_object *intel_pbo =
859 brw_buffer_object(packing->BufferObj);
860 struct brw_bo *bo =
861 brw_bufferobj_buffer(brw, intel_pbo, offset, size, !read_only);
862
863 /* We take a reference to the BO so that the caller can just always
864 * unref without having to worry about whether it's a user PBO or one
865 * we created.
866 */
867 brw_bo_reference(bo);
868
869 *offset_out = offset;
870 return bo;
871 } else {
872 /* Someone should have already checked that there is data to upload. */
873 assert(pixels);
874
875 /* Creating a temp buffer currently only works for upload */
876 assert(read_only);
877
878 /* This is not a user-provided PBO. Instead, pixels is a pointer to CPU
879 * data which we need to copy into a BO.
880 */
881 struct brw_bo *bo =
882 brw_bo_alloc(brw->bufmgr, "tmp_tex_subimage_src", size,
883 BRW_MEMZONE_OTHER);
884 if (bo == NULL) {
885 perf_debug("%s: temp bo creation failed: size = %u\n", __func__,
886 size);
887 return NULL;
888 }
889
890 if (brw_bo_subdata(bo, 0, size, pixels + first_pixel)) {
891 perf_debug("%s: temp bo upload failed\n", __func__);
892 brw_bo_unreference(bo);
893 return NULL;
894 }
895
896 *offset_out = 0;
897 return bo;
898 }
899 }
900
901 /* Consider all the restrictions and determine the format of the source. */
902 static mesa_format
blorp_get_client_format(struct brw_context * brw,GLenum format,GLenum type,const struct gl_pixelstore_attrib * packing)903 blorp_get_client_format(struct brw_context *brw,
904 GLenum format, GLenum type,
905 const struct gl_pixelstore_attrib *packing)
906 {
907 if (brw->ctx._ImageTransferState)
908 return MESA_FORMAT_NONE;
909
910 if (packing->SwapBytes || packing->LsbFirst || packing->Invert) {
911 perf_debug("%s: unsupported gl_pixelstore_attrib\n", __func__);
912 return MESA_FORMAT_NONE;
913 }
914
915 if (format != GL_RED &&
916 format != GL_RG &&
917 format != GL_RGB &&
918 format != GL_BGR &&
919 format != GL_RGBA &&
920 format != GL_BGRA &&
921 format != GL_ALPHA &&
922 format != GL_RED_INTEGER &&
923 format != GL_RG_INTEGER &&
924 format != GL_RGB_INTEGER &&
925 format != GL_BGR_INTEGER &&
926 format != GL_RGBA_INTEGER &&
927 format != GL_BGRA_INTEGER) {
928 perf_debug("%s: %s not supported", __func__,
929 _mesa_enum_to_string(format));
930 return MESA_FORMAT_NONE;
931 }
932
933 return _mesa_tex_format_from_format_and_type(&brw->ctx, format, type);
934 }
935
936 bool
brw_blorp_upload_miptree(struct brw_context * brw,struct brw_mipmap_tree * dst_mt,mesa_format dst_format,uint32_t level,uint32_t x,uint32_t y,uint32_t z,uint32_t width,uint32_t height,uint32_t depth,GLenum target,GLenum format,GLenum type,const void * pixels,const struct gl_pixelstore_attrib * packing)937 brw_blorp_upload_miptree(struct brw_context *brw,
938 struct brw_mipmap_tree *dst_mt,
939 mesa_format dst_format,
940 uint32_t level, uint32_t x, uint32_t y, uint32_t z,
941 uint32_t width, uint32_t height, uint32_t depth,
942 GLenum target, GLenum format, GLenum type,
943 const void *pixels,
944 const struct gl_pixelstore_attrib *packing)
945 {
946 const mesa_format src_format =
947 blorp_get_client_format(brw, format, type, packing);
948 if (src_format == MESA_FORMAT_NONE)
949 return false;
950
951 if (!brw->mesa_format_supports_render[dst_format]) {
952 perf_debug("%s: can't use %s as render target\n", __func__,
953 _mesa_get_format_name(dst_format));
954 return false;
955 }
956
957 uint32_t src_offset, src_row_stride, src_image_stride;
958 struct brw_bo *src_bo =
959 blorp_get_client_bo(brw, width, height, depth,
960 target, format, type, pixels, packing,
961 &src_offset, &src_row_stride,
962 &src_image_stride, true);
963 if (src_bo == NULL)
964 return false;
965
966 /* Now that source is offset to correct starting point, adjust the
967 * given dimensions to treat 1D arrays as 2D.
968 */
969 if (target == GL_TEXTURE_1D_ARRAY) {
970 assert(depth == 1);
971 assert(z == 0);
972 depth = height;
973 height = 1;
974 z = y;
975 y = 0;
976 src_image_stride = src_row_stride;
977 }
978
979 brw_miptree_check_level_layer(dst_mt, level, z + depth - 1);
980
981 bool result = false;
982
983 /* Blit slice-by-slice creating a single-slice miptree for each layer. Even
984 * in case of linear buffers hardware wants image arrays to be aligned by
985 * four rows. This way hardware only gets one image at a time and any
986 * source alignment will do.
987 */
988 for (unsigned i = 0; i < depth; ++i) {
989 struct brw_mipmap_tree *src_mt =
990 brw_miptree_create_for_bo(brw, src_bo, src_format,
991 src_offset + i * src_image_stride,
992 width, height, 1,
993 src_row_stride,
994 ISL_TILING_LINEAR, 0);
995
996 if (!src_mt) {
997 perf_debug("%s: miptree creation for src failed\n", __func__);
998 goto err;
999 }
1000
1001 /* In case exact match is needed, copy using equivalent UINT formats
1002 * preventing hardware from changing presentation for SNORM -1.
1003 */
1004 if (src_mt->format == dst_format) {
1005 brw_blorp_copy_miptrees(brw, src_mt, 0, 0,
1006 dst_mt, level, z + i,
1007 0, 0, x, y, width, height);
1008 } else {
1009 brw_blorp_blit_miptrees(brw, src_mt, 0, 0,
1010 src_format, SWIZZLE_XYZW,
1011 dst_mt, level, z + i,
1012 dst_format,
1013 0, 0, width, height,
1014 x, y, x + width, y + height,
1015 GL_NEAREST, false, false, false, false);
1016 }
1017
1018 brw_miptree_release(&src_mt);
1019 }
1020
1021 result = true;
1022
1023 err:
1024 brw_bo_unreference(src_bo);
1025
1026 return result;
1027 }
1028
1029 bool
brw_blorp_download_miptree(struct brw_context * brw,struct brw_mipmap_tree * src_mt,mesa_format src_format,uint32_t src_swizzle,uint32_t level,uint32_t x,uint32_t y,uint32_t z,uint32_t width,uint32_t height,uint32_t depth,GLenum target,GLenum format,GLenum type,bool y_flip,const void * pixels,const struct gl_pixelstore_attrib * packing)1030 brw_blorp_download_miptree(struct brw_context *brw,
1031 struct brw_mipmap_tree *src_mt,
1032 mesa_format src_format, uint32_t src_swizzle,
1033 uint32_t level, uint32_t x, uint32_t y, uint32_t z,
1034 uint32_t width, uint32_t height, uint32_t depth,
1035 GLenum target, GLenum format, GLenum type,
1036 bool y_flip, const void *pixels,
1037 const struct gl_pixelstore_attrib *packing)
1038 {
1039 const mesa_format dst_format =
1040 blorp_get_client_format(brw, format, type, packing);
1041 if (dst_format == MESA_FORMAT_NONE)
1042 return false;
1043
1044 if (!brw->mesa_format_supports_render[dst_format]) {
1045 perf_debug("%s: can't use %s as render target\n", __func__,
1046 _mesa_get_format_name(dst_format));
1047 return false;
1048 }
1049
1050 /* We can't fetch from LUMINANCE or intensity as that would require a
1051 * non-trivial swizzle.
1052 */
1053 switch (_mesa_get_format_base_format(src_format)) {
1054 case GL_LUMINANCE:
1055 case GL_LUMINANCE_ALPHA:
1056 case GL_INTENSITY:
1057 return false;
1058 default:
1059 break;
1060 }
1061
1062 /* This pass only works for PBOs */
1063 assert(packing->BufferObj);
1064
1065 uint32_t dst_offset, dst_row_stride, dst_image_stride;
1066 struct brw_bo *dst_bo =
1067 blorp_get_client_bo(brw, width, height, depth,
1068 target, format, type, pixels, packing,
1069 &dst_offset, &dst_row_stride,
1070 &dst_image_stride, false);
1071 if (dst_bo == NULL)
1072 return false;
1073
1074 /* Now that source is offset to correct starting point, adjust the
1075 * given dimensions to treat 1D arrays as 2D.
1076 */
1077 if (target == GL_TEXTURE_1D_ARRAY) {
1078 assert(depth == 1);
1079 assert(z == 0);
1080 depth = height;
1081 height = 1;
1082 z = y;
1083 y = 0;
1084 dst_image_stride = dst_row_stride;
1085 }
1086
1087 brw_miptree_check_level_layer(src_mt, level, z + depth - 1);
1088
1089 int y0 = y;
1090 int y1 = y + height;
1091 if (y_flip) {
1092 apply_y_flip(&y0, &y1, minify(src_mt->surf.phys_level0_sa.height,
1093 level - src_mt->first_level));
1094 }
1095
1096 bool result = false;
1097
1098 /* Blit slice-by-slice creating a single-slice miptree for each layer. Even
1099 * in case of linear buffers hardware wants image arrays to be aligned by
1100 * four rows. This way hardware only gets one image at a time and any
1101 * source alignment will do.
1102 */
1103 for (unsigned i = 0; i < depth; ++i) {
1104 struct brw_mipmap_tree *dst_mt =
1105 brw_miptree_create_for_bo(brw, dst_bo, dst_format,
1106 dst_offset + i * dst_image_stride,
1107 width, height, 1,
1108 dst_row_stride,
1109 ISL_TILING_LINEAR, 0);
1110
1111 if (!dst_mt) {
1112 perf_debug("%s: miptree creation for src failed\n", __func__);
1113 goto err;
1114 }
1115
1116 /* In case exact match is needed, copy using equivalent UINT formats
1117 * preventing hardware from changing presentation for SNORM -1.
1118 */
1119 if (dst_mt->format == src_format && !y_flip &&
1120 src_swizzle == SWIZZLE_XYZW) {
1121 brw_blorp_copy_miptrees(brw, src_mt, level, z + i,
1122 dst_mt, 0, 0,
1123 x, y, 0, 0, width, height);
1124 } else {
1125 brw_blorp_blit_miptrees(brw, src_mt, level, z + i,
1126 src_format, src_swizzle,
1127 dst_mt, 0, 0, dst_format,
1128 x, y0, x + width, y1,
1129 0, 0, width, height,
1130 GL_NEAREST, false, y_flip, false, false);
1131 }
1132
1133 brw_miptree_release(&dst_mt);
1134 }
1135
1136 result = true;
1137
1138 /* As we implement PBO transfers by binding the user-provided BO as a
1139 * fake framebuffer and rendering to it. This breaks the invariant of the
1140 * GL that nothing is able to render to a BO, causing nondeterministic
1141 * corruption issues because the render cache is not coherent with a
1142 * number of other caches that the BO could potentially be bound to
1143 * afterwards.
1144 *
1145 * This could be solved in the same way that we guarantee texture
1146 * coherency after a texture is attached to a framebuffer and
1147 * rendered to, but that would involve checking *all* BOs bound to
1148 * the pipeline for the case we need to emit a cache flush due to
1149 * previous rendering to any of them -- Including vertex, index,
1150 * uniform, atomic counter, shader image, transform feedback,
1151 * indirect draw buffers, etc.
1152 *
1153 * That would increase the per-draw call overhead even though it's
1154 * very unlikely that any of the BOs bound to the pipeline has been
1155 * rendered to via a PBO at any point, so it seems better to just
1156 * flush here unconditionally.
1157 */
1158 brw_emit_mi_flush(brw);
1159
1160 err:
1161 brw_bo_unreference(dst_bo);
1162
1163 return result;
1164 }
1165
1166 static bool
set_write_disables(const struct brw_renderbuffer * irb,const unsigned color_mask,uint8_t * color_write_disable)1167 set_write_disables(const struct brw_renderbuffer *irb,
1168 const unsigned color_mask, uint8_t *color_write_disable)
1169 {
1170 /* Format information in the renderbuffer represents the requirements
1171 * given by the client. There are cases where the backing miptree uses,
1172 * for example, RGBA to represent RGBX. Since the client is only expecting
1173 * RGB we can treat alpha as not used and write whatever we like into it.
1174 */
1175 const GLenum base_format = irb->Base.Base._BaseFormat;
1176 const int components = _mesa_components_in_format(base_format);
1177 assert(components > 0);
1178 *color_write_disable = ~color_mask & BITFIELD_MASK(components);
1179 return *color_write_disable;
1180 }
1181
1182 static void
do_single_blorp_clear(struct brw_context * brw,struct gl_framebuffer * fb,struct gl_renderbuffer * rb,unsigned buf,bool partial_clear,bool encode_srgb)1183 do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
1184 struct gl_renderbuffer *rb, unsigned buf,
1185 bool partial_clear, bool encode_srgb)
1186 {
1187 struct gl_context *ctx = &brw->ctx;
1188 struct brw_renderbuffer *irb = brw_renderbuffer(rb);
1189 uint32_t x0, x1, y0, y1;
1190
1191 mesa_format format = irb->Base.Base.Format;
1192 if (!encode_srgb)
1193 format = _mesa_get_srgb_format_linear(format);
1194 enum isl_format isl_format = brw->mesa_to_isl_render_format[format];
1195
1196 x0 = fb->_Xmin;
1197 x1 = fb->_Xmax;
1198 if (fb->FlipY) {
1199 y0 = rb->Height - fb->_Ymax;
1200 y1 = rb->Height - fb->_Ymin;
1201 } else {
1202 y0 = fb->_Ymin;
1203 y1 = fb->_Ymax;
1204 }
1205
1206 /* If the clear region is empty, just return. */
1207 if (x0 == x1 || y0 == y1)
1208 return;
1209
1210 bool can_fast_clear = !partial_clear;
1211
1212 if (INTEL_DEBUG(DEBUG_NO_FAST_CLEAR))
1213 can_fast_clear = false;
1214
1215 uint8_t color_write_disable = 0;
1216 if (set_write_disables(irb, GET_COLORMASK(ctx->Color.ColorMask, buf),
1217 &color_write_disable))
1218 can_fast_clear = false;
1219
1220 /* We store clear colors as floats or uints as needed. If there are
1221 * texture views in play, the formats will not properly be respected
1222 * during resolves because the resolve operations only know about the
1223 * miptree and not the renderbuffer.
1224 */
1225 if (irb->Base.Base.Format != irb->mt->format)
1226 can_fast_clear = false;
1227
1228 if (!irb->mt->supports_fast_clear ||
1229 !brw_is_color_fast_clear_compatible(brw, irb->mt, &ctx->Color.ClearColor))
1230 can_fast_clear = false;
1231
1232 /* Surface state can only record one fast clear color value. Therefore
1233 * unless different levels/layers agree on the color it can be used to
1234 * represent only single level/layer. Here it will be reserved for the
1235 * first slice (level 0, layer 0).
1236 */
1237 if (irb->layer_count > 1 || irb->mt_level || irb->mt_layer)
1238 can_fast_clear = false;
1239
1240 unsigned level = irb->mt_level;
1241 const unsigned num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
1242
1243 /* If the MCS buffer hasn't been allocated yet, we need to allocate it now.
1244 */
1245 if (can_fast_clear && !irb->mt->aux_buf) {
1246 assert(irb->mt->aux_usage == ISL_AUX_USAGE_CCS_D);
1247 if (!brw_miptree_alloc_aux(brw, irb->mt)) {
1248 /* We're out of memory. Fall back to a non-fast clear. */
1249 can_fast_clear = false;
1250 }
1251 }
1252
1253 if (can_fast_clear) {
1254 const enum isl_aux_state aux_state =
1255 brw_miptree_get_aux_state(irb->mt, irb->mt_level, irb->mt_layer);
1256 union isl_color_value clear_color =
1257 brw_meta_convert_fast_clear_color(brw, irb->mt,
1258 &ctx->Color.ClearColor);
1259
1260 /* If the buffer is already in ISL_AUX_STATE_CLEAR and the clear color
1261 * hasn't changed, the clear is redundant and can be skipped.
1262 */
1263 if (!brw_miptree_set_clear_color(brw, irb->mt, clear_color) &&
1264 aux_state == ISL_AUX_STATE_CLEAR) {
1265 return;
1266 }
1267
1268 DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__,
1269 irb->mt, irb->mt_level, irb->mt_layer, num_layers);
1270
1271 /* We can't setup the blorp_surf until we've allocated the MCS above */
1272 struct blorp_surf surf;
1273 blorp_surf_for_miptree(brw, &surf, irb->mt, irb->mt->aux_usage, true,
1274 &level, irb->mt_layer, num_layers);
1275
1276 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1277 *
1278 * "Any transition from any value in {Clear, Render, Resolve} to a
1279 * different value in {Clear, Render, Resolve} requires end of pipe
1280 * synchronization."
1281 *
1282 * In other words, fast clear ops are not properly synchronized with
1283 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1284 * contents of the previous draw hit the render target before we resolve
1285 * and again afterwards to ensure that the resolve is complete before we
1286 * do any more regular drawing.
1287 */
1288 brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH);
1289
1290 struct blorp_batch batch;
1291 blorp_batch_init(&brw->blorp, &batch, brw, 0);
1292 blorp_fast_clear(&batch, &surf, isl_format_srgb_to_linear(isl_format),
1293 ISL_SWIZZLE_IDENTITY,
1294 level, irb->mt_layer, num_layers, x0, y0, x1, y1);
1295 blorp_batch_finish(&batch);
1296
1297 brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH);
1298
1299 /* Now that the fast clear has occurred, put the buffer in
1300 * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
1301 * redundant clears.
1302 */
1303 brw_miptree_set_aux_state(brw, irb->mt, irb->mt_level,
1304 irb->mt_layer, num_layers,
1305 ISL_AUX_STATE_CLEAR);
1306 } else {
1307 DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__,
1308 irb->mt, irb->mt_level, irb->mt_layer, num_layers);
1309
1310 enum isl_aux_usage aux_usage =
1311 brw_miptree_render_aux_usage(brw, irb->mt, isl_format, false, false);
1312 brw_miptree_prepare_render(brw, irb->mt, level, irb->mt_layer,
1313 num_layers, aux_usage);
1314
1315 struct blorp_surf surf;
1316 blorp_surf_for_miptree(brw, &surf, irb->mt, aux_usage, true,
1317 &level, irb->mt_layer, num_layers);
1318
1319 union isl_color_value clear_color;
1320 memcpy(clear_color.f32, ctx->Color.ClearColor.f, sizeof(float) * 4);
1321
1322 struct blorp_batch batch;
1323 blorp_batch_init(&brw->blorp, &batch, brw, 0);
1324 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
1325 level, irb->mt_layer, num_layers,
1326 x0, y0, x1, y1,
1327 clear_color, color_write_disable);
1328 blorp_batch_finish(&batch);
1329
1330 brw_miptree_finish_render(brw, irb->mt, level, irb->mt_layer,
1331 num_layers, aux_usage);
1332 }
1333
1334 return;
1335 }
1336
1337 void
brw_blorp_clear_color(struct brw_context * brw,struct gl_framebuffer * fb,GLbitfield mask,bool partial_clear,bool encode_srgb)1338 brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb,
1339 GLbitfield mask, bool partial_clear, bool encode_srgb)
1340 {
1341 for (unsigned buf = 0; buf < fb->_NumColorDrawBuffers; buf++) {
1342 struct gl_renderbuffer *rb = fb->_ColorDrawBuffers[buf];
1343 struct brw_renderbuffer *irb = brw_renderbuffer(rb);
1344
1345 /* Only clear the buffers present in the provided mask */
1346 if (((1 << fb->_ColorDrawBufferIndexes[buf]) & mask) == 0)
1347 continue;
1348
1349 /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
1350 * the framebuffer can be complete with some attachments missing. In
1351 * this case the _ColorDrawBuffers pointer will be NULL.
1352 */
1353 if (rb == NULL)
1354 continue;
1355
1356 do_single_blorp_clear(brw, fb, rb, buf, partial_clear, encode_srgb);
1357 irb->need_downsample = true;
1358 }
1359
1360 return;
1361 }
1362
1363 void
brw_blorp_clear_depth_stencil(struct brw_context * brw,struct gl_framebuffer * fb,GLbitfield mask,bool partial_clear)1364 brw_blorp_clear_depth_stencil(struct brw_context *brw,
1365 struct gl_framebuffer *fb,
1366 GLbitfield mask, bool partial_clear)
1367 {
1368 const struct gl_context *ctx = &brw->ctx;
1369 struct gl_renderbuffer *depth_rb =
1370 fb->Attachment[BUFFER_DEPTH].Renderbuffer;
1371 struct gl_renderbuffer *stencil_rb =
1372 fb->Attachment[BUFFER_STENCIL].Renderbuffer;
1373
1374 if (!depth_rb || ctx->Depth.Mask == GL_FALSE)
1375 mask &= ~BUFFER_BIT_DEPTH;
1376
1377 if (!stencil_rb || (ctx->Stencil.WriteMask[0] & 0xff) == 0)
1378 mask &= ~BUFFER_BIT_STENCIL;
1379
1380 if (!(mask & (BUFFER_BITS_DEPTH_STENCIL)))
1381 return;
1382
1383 uint32_t x0, x1, y0, y1, rb_height;
1384 if (depth_rb) {
1385 rb_height = depth_rb->Height;
1386 if (stencil_rb) {
1387 assert(depth_rb->Width == stencil_rb->Width);
1388 assert(depth_rb->Height == stencil_rb->Height);
1389 }
1390 } else {
1391 assert(stencil_rb);
1392 rb_height = stencil_rb->Height;
1393 }
1394
1395 x0 = fb->_Xmin;
1396 x1 = fb->_Xmax;
1397 if (fb->FlipY) {
1398 y0 = rb_height - fb->_Ymax;
1399 y1 = rb_height - fb->_Ymin;
1400 } else {
1401 y0 = fb->_Ymin;
1402 y1 = fb->_Ymax;
1403 }
1404
1405 /* If the clear region is empty, just return. */
1406 if (x0 == x1 || y0 == y1)
1407 return;
1408
1409 uint32_t level = 0, start_layer = 0, num_layers;
1410 struct blorp_surf depth_surf, stencil_surf;
1411
1412 struct brw_mipmap_tree *depth_mt = NULL;
1413 if (mask & BUFFER_BIT_DEPTH) {
1414 struct brw_renderbuffer *irb = brw_renderbuffer(depth_rb);
1415 depth_mt = find_miptree(GL_DEPTH_BUFFER_BIT, irb);
1416
1417 level = irb->mt_level;
1418 start_layer = irb->mt_layer;
1419 num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
1420
1421 brw_miptree_prepare_depth(brw, depth_mt, level, start_layer, num_layers);
1422
1423 unsigned depth_level = level;
1424 blorp_surf_for_miptree(brw, &depth_surf, depth_mt, depth_mt->aux_usage,
1425 true, &depth_level, start_layer, num_layers);
1426 assert(depth_level == level);
1427 }
1428
1429 uint8_t stencil_mask = 0;
1430 struct brw_mipmap_tree *stencil_mt = NULL;
1431 if (mask & BUFFER_BIT_STENCIL) {
1432 struct brw_renderbuffer *irb = brw_renderbuffer(stencil_rb);
1433 stencil_mt = find_miptree(GL_STENCIL_BUFFER_BIT, irb);
1434
1435 if (mask & BUFFER_BIT_DEPTH) {
1436 assert(level == irb->mt_level);
1437 assert(start_layer == irb->mt_layer);
1438 assert(num_layers == fb->MaxNumLayers ? irb->layer_count : 1);
1439 }
1440
1441 level = irb->mt_level;
1442 start_layer = irb->mt_layer;
1443 num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
1444
1445 stencil_mask = ctx->Stencil.WriteMask[0] & 0xff;
1446
1447 brw_miptree_prepare_access(brw, stencil_mt, level, 1,
1448 start_layer, num_layers,
1449 ISL_AUX_USAGE_NONE, false);
1450
1451 unsigned stencil_level = level;
1452 blorp_surf_for_miptree(brw, &stencil_surf, stencil_mt,
1453 ISL_AUX_USAGE_NONE, true,
1454 &stencil_level, start_layer, num_layers);
1455 }
1456
1457 assert((mask & BUFFER_BIT_DEPTH) || stencil_mask);
1458
1459 struct blorp_batch batch;
1460 blorp_batch_init(&brw->blorp, &batch, brw, 0);
1461 blorp_clear_depth_stencil(&batch, &depth_surf, &stencil_surf,
1462 level, start_layer, num_layers,
1463 x0, y0, x1, y1,
1464 (mask & BUFFER_BIT_DEPTH), ctx->Depth.Clear,
1465 stencil_mask, ctx->Stencil.Clear);
1466 blorp_batch_finish(&batch);
1467
1468 if (mask & BUFFER_BIT_DEPTH) {
1469 brw_miptree_finish_depth(brw, depth_mt, level,
1470 start_layer, num_layers, true);
1471 }
1472
1473 if (stencil_mask) {
1474 brw_miptree_finish_write(brw, stencil_mt, level,
1475 start_layer, num_layers,
1476 ISL_AUX_USAGE_NONE);
1477 }
1478 }
1479
1480 void
brw_blorp_resolve_color(struct brw_context * brw,struct brw_mipmap_tree * mt,unsigned level,unsigned layer,enum isl_aux_op resolve_op)1481 brw_blorp_resolve_color(struct brw_context *brw, struct brw_mipmap_tree *mt,
1482 unsigned level, unsigned layer,
1483 enum isl_aux_op resolve_op)
1484 {
1485 DBG("%s to mt %p level %u layer %u\n", __FUNCTION__, mt, level, layer);
1486
1487 const mesa_format format = _mesa_get_srgb_format_linear(mt->format);
1488
1489 struct blorp_surf surf;
1490 blorp_surf_for_miptree(brw, &surf, mt, mt->aux_usage, true,
1491 &level, layer, 1 /* num_layers */);
1492
1493 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1494 *
1495 * "Any transition from any value in {Clear, Render, Resolve} to a
1496 * different value in {Clear, Render, Resolve} requires end of pipe
1497 * synchronization."
1498 *
1499 * In other words, fast clear ops are not properly synchronized with
1500 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1501 * contents of the previous draw hit the render target before we resolve
1502 * and again afterwards to ensure that the resolve is complete before we
1503 * do any more regular drawing.
1504 */
1505 brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH);
1506
1507
1508 struct blorp_batch batch;
1509 blorp_batch_init(&brw->blorp, &batch, brw, 0);
1510 blorp_ccs_resolve(&batch, &surf, level, layer, 1,
1511 brw_blorp_to_isl_format(brw, format, true),
1512 resolve_op);
1513 blorp_batch_finish(&batch);
1514
1515 /* See comment above */
1516 brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH);
1517 }
1518
1519 void
brw_blorp_mcs_partial_resolve(struct brw_context * brw,struct brw_mipmap_tree * mt,uint32_t start_layer,uint32_t num_layers)1520 brw_blorp_mcs_partial_resolve(struct brw_context *brw,
1521 struct brw_mipmap_tree *mt,
1522 uint32_t start_layer, uint32_t num_layers)
1523 {
1524 DBG("%s to mt %p layers %u-%u\n", __FUNCTION__, mt,
1525 start_layer, start_layer + num_layers - 1);
1526
1527 assert(mt->aux_usage == ISL_AUX_USAGE_MCS);
1528
1529 const mesa_format format = _mesa_get_srgb_format_linear(mt->format);
1530 enum isl_format isl_format = brw_blorp_to_isl_format(brw, format, true);
1531
1532 struct blorp_surf surf;
1533 uint32_t level = 0;
1534 blorp_surf_for_miptree(brw, &surf, mt, ISL_AUX_USAGE_MCS, true,
1535 &level, start_layer, num_layers);
1536
1537 struct blorp_batch batch;
1538 blorp_batch_init(&brw->blorp, &batch, brw, 0);
1539 blorp_mcs_partial_resolve(&batch, &surf, isl_format,
1540 start_layer, num_layers);
1541 blorp_batch_finish(&batch);
1542 }
1543
1544 /**
1545 * Perform a HiZ or depth resolve operation.
1546 *
1547 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
1548 * PRM, Volume 1, Part 2:
1549 * - 7.5.3.1 Depth Buffer Clear
1550 * - 7.5.3.2 Depth Buffer Resolve
1551 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1552 */
1553 void
brw_hiz_exec(struct brw_context * brw,struct brw_mipmap_tree * mt,unsigned int level,unsigned int start_layer,unsigned int num_layers,enum isl_aux_op op)1554 brw_hiz_exec(struct brw_context *brw, struct brw_mipmap_tree *mt,
1555 unsigned int level, unsigned int start_layer,
1556 unsigned int num_layers, enum isl_aux_op op)
1557 {
1558 assert(brw_miptree_level_has_hiz(mt, level));
1559 assert(op != ISL_AUX_OP_NONE);
1560 const struct intel_device_info *devinfo = &brw->screen->devinfo;
1561 const char *opname = NULL;
1562
1563 switch (op) {
1564 case ISL_AUX_OP_FULL_RESOLVE:
1565 opname = "depth resolve";
1566 break;
1567 case ISL_AUX_OP_AMBIGUATE:
1568 opname = "hiz ambiguate";
1569 break;
1570 case ISL_AUX_OP_FAST_CLEAR:
1571 opname = "depth clear";
1572 break;
1573 case ISL_AUX_OP_PARTIAL_RESOLVE:
1574 case ISL_AUX_OP_NONE:
1575 unreachable("Invalid HiZ op");
1576 }
1577
1578 DBG("%s %s to mt %p level %d layers %d-%d\n",
1579 __func__, opname, mt, level, start_layer, start_layer + num_layers - 1);
1580
1581 /* The following stalls and flushes are only documented to be required for
1582 * HiZ clear operations. However, they also seem to be required for
1583 * resolve operations.
1584 */
1585 if (devinfo->ver == 6) {
1586 /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
1587 *
1588 * "If other rendering operations have preceded this clear, a
1589 * PIPE_CONTROL with write cache flush enabled and Z-inhibit
1590 * disabled must be issued before the rectangle primitive used for
1591 * the depth buffer clear operation.
1592 */
1593 brw_emit_pipe_control_flush(brw,
1594 PIPE_CONTROL_RENDER_TARGET_FLUSH |
1595 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
1596 PIPE_CONTROL_CS_STALL);
1597 } else if (devinfo->ver >= 7) {
1598 /*
1599 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
1600 *
1601 * If other rendering operations have preceded this clear, a
1602 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
1603 * enabled must be issued before the rectangle primitive used for
1604 * the depth buffer clear operation.
1605 *
1606 * Same applies for Gfx8 and Gfx9.
1607 *
1608 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
1609 * PIPE_CONTROL, Depth Cache Flush Enable:
1610 *
1611 * This bit must not be set when Depth Stall Enable bit is set in
1612 * this packet.
1613 *
1614 * This is confirmed to hold for real, HSW gets immediate gpu hangs.
1615 *
1616 * Therefore issue two pipe control flushes, one for cache flush and
1617 * another for depth stall.
1618 */
1619 brw_emit_pipe_control_flush(brw,
1620 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
1621 PIPE_CONTROL_CS_STALL);
1622
1623 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
1624 }
1625
1626 assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->aux_buf);
1627
1628 struct blorp_surf surf;
1629 blorp_surf_for_miptree(brw, &surf, mt, ISL_AUX_USAGE_HIZ, true,
1630 &level, start_layer, num_layers);
1631
1632 struct blorp_batch batch;
1633 blorp_batch_init(&brw->blorp, &batch, brw,
1634 BLORP_BATCH_NO_UPDATE_CLEAR_COLOR);
1635 blorp_hiz_op(&batch, &surf, level, start_layer, num_layers, op);
1636 blorp_batch_finish(&batch);
1637
1638 /* The following stalls and flushes are only documented to be required for
1639 * HiZ clear operations. However, they also seem to be required for
1640 * resolve operations.
1641 */
1642 if (devinfo->ver == 6) {
1643 /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
1644 *
1645 * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be
1646 * followed by a PIPE_CONTROL command with DEPTH_STALL bit set
1647 * and Then followed by Depth FLUSH'
1648 */
1649 brw_emit_pipe_control_flush(brw,
1650 PIPE_CONTROL_DEPTH_STALL);
1651
1652 brw_emit_pipe_control_flush(brw,
1653 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
1654 PIPE_CONTROL_CS_STALL);
1655 } else if (devinfo->ver >= 8) {
1656 /*
1657 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
1658 *
1659 * "Depth buffer clear pass using any of the methods (WM_STATE,
1660 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
1661 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
1662 * "set" before starting to render. DepthStall and DepthFlush are
1663 * not needed between consecutive depth clear passes nor is it
1664 * required if the depth clear pass was done with
1665 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
1666 *
1667 * TODO: Such as the spec says, this could be conditional.
1668 */
1669 brw_emit_pipe_control_flush(brw,
1670 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
1671 PIPE_CONTROL_DEPTH_STALL);
1672
1673 }
1674 }
1675