Lines Matching +full:0 +full:x4104000
13 #clock-cells = <0>;
15 clock-frequency = <0>;
19 #clock-cells = <0>;
21 clock-frequency = <0>;
28 reg = <0x0 0x70000000 0x0 0x800000>;
31 ranges = <0x0 0x0 0x70000000 0x800000>;
33 atf-sram@0 {
34 reg = <0x0 0x20000>;
40 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
43 ranges = <0x0 0x0 0x00100000 0x1c000>;
47 reg = <0x00004070 0x4>;
50 ranges = <0x4070 0x4070 0x4>;
55 reg = <0x00004074 0x4>;
58 ranges = <0x4074 0x4074 0x4>;
63 reg = <0x00004078 0x4>;
66 ranges = <0x4078 0x4078 0x4>;
71 reg = <0x0000407c 0x4>;
74 ranges = <0x407c 0x407c 0x4>;
79 reg = <0x00004080 0x50>;
81 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
82 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
83 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
84 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
85 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
98 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
99 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
110 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
111 <0x00 0x01900000 0x00 0x100000>; /* GICR */
118 reg = <0x00 0x01820000 0x00 0x10000>;
119 socionext,synquacer-pre-its = <0x1000000 0x400000>;
154 ti,interrupt-ranges = <0 64 64>,
161 reg = <0x0 0x33d00000 0x0 0x100000>;
167 ti,interrupt-ranges = <0 0 256>;
174 reg = <0x00 0x32c00000 0x00 0x100000>,
175 <0x00 0x32400000 0x00 0x100000>,
176 <0x00 0x32800000 0x00 0x100000>;
183 reg = <0x0 0x36600000 0x0 0x100000>;
193 reg = <0x00 0x30e00000 0x00 0x1000>;
199 reg = <0x00 0x31f80000 0x00 0x200>;
208 reg = <0x00 0x31f81000 0x00 0x200>;
217 reg = <0x00 0x31f82000 0x00 0x200>;
226 reg = <0x00 0x31f83000 0x00 0x200>;
235 reg = <0x00 0x31f84000 0x00 0x200>;
244 reg = <0x00 0x31f85000 0x00 0x200>;
253 reg = <0x00 0x31f86000 0x00 0x200>;
262 reg = <0x00 0x31f87000 0x00 0x200>;
271 reg = <0x00 0x31f88000 0x00 0x200>;
280 reg = <0x00 0x31f89000 0x00 0x200>;
289 reg = <0x00 0x31f8a000 0x00 0x200>;
298 reg = <0x00 0x31f8b000 0x00 0x200>;
307 reg = <0x0 0x3c000000 0x0 0x400000>,
308 <0x0 0x38000000 0x0 0x400000>,
309 <0x0 0x31120000 0x0 0x100>,
310 <0x0 0x33000000 0x0 0x40000>;
313 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
321 reg = <0x0 0x31150000 0x0 0x100>,
322 <0x0 0x34000000 0x0 0x100000>,
323 <0x0 0x35000000 0x0 0x100000>;
332 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
333 <0x0f>, /* TX_HCHAN */
334 <0x10>; /* TX_UHCHAN */
335 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
336 <0x0b>, /* RX_HCHAN */
337 <0x0c>; /* RX_UHCHAN */
338 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
343 reg = <0x0 0x310d0000 0x0 0x400>;
356 reg = <0x0 0x4e00000 0x0 0x1200>;
360 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
364 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
365 <&main_udmap 0x4001>;
371 reg = <0x0 0x4e10000 0x0 0x7d>;
379 /* Proxy 0 addressing */
380 reg = <0x0 0x11c000 0x0 0x2b4>;
383 pinctrl-single,function-mask = <0xffffffff>;
393 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
397 ranges = <0x5000000 0x0 0x5000000 0x10000>;
401 #clock-cells = <0>;
407 clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
408 #clock-cells = <0>;
410 assigned-clock-parents = <&k3_clks 292 0>;
414 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
415 #clock-cells = <0>;
422 #clock-cells = <0>;
427 #clock-cells = <0>;
433 reg = <0x5000000 0x10000>;
435 #size-cells = <0>;
436 resets = <&serdes_wiz0 0>;
450 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
454 ranges = <0x5010000 0x0 0x5010000 0x10000>;
458 #clock-cells = <0>;
464 clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
465 #clock-cells = <0>;
467 assigned-clock-parents = <&k3_clks 293 0>;
471 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
472 #clock-cells = <0>;
479 #clock-cells = <0>;
484 #clock-cells = <0>;
490 reg = <0x5010000 0x10000>;
492 #size-cells = <0>;
493 resets = <&serdes_wiz1 0>;
507 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
511 ranges = <0x5020000 0x0 0x5020000 0x10000>;
515 #clock-cells = <0>;
521 clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
522 #clock-cells = <0>;
524 assigned-clock-parents = <&k3_clks 294 0>;
528 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
529 #clock-cells = <0>;
536 #clock-cells = <0>;
541 #clock-cells = <0>;
547 reg = <0x5020000 0x10000>;
549 #size-cells = <0>;
550 resets = <&serdes_wiz2 0>;
564 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
568 ranges = <0x5030000 0x0 0x5030000 0x10000>;
572 #clock-cells = <0>;
578 clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
579 #clock-cells = <0>;
581 assigned-clock-parents = <&k3_clks 295 0>;
585 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
586 #clock-cells = <0>;
593 #clock-cells = <0>;
598 #clock-cells = <0>;
604 reg = <0x5030000 0x10000>;
606 #size-cells = <0>;
607 resets = <&serdes_wiz3 0>;
616 reg = <0x00 0x02900000 0x00 0x1000>,
617 <0x00 0x02907000 0x00 0x400>,
618 <0x00 0x0d000000 0x00 0x00800000>,
619 <0x00 0x10000000 0x00 0x00001000>;
632 bus-range = <0x0 0xff>;
633 vendor-id = <0x104c>;
634 device-id = <0xb00d>;
635 msi-map = <0x0 &gic_its 0x0 0x10000>;
637 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
638 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
639 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
644 reg = <0x00 0x02900000 0x00 0x1000>,
645 <0x00 0x02907000 0x00 0x400>,
646 <0x00 0x0d000000 0x00 0x00800000>,
647 <0x00 0x10000000 0x00 0x08000000>;
659 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
665 reg = <0x00 0x02910000 0x00 0x1000>,
666 <0x00 0x02917000 0x00 0x400>,
667 <0x00 0x0d800000 0x00 0x00800000>,
668 <0x00 0x18000000 0x00 0x00001000>;
681 bus-range = <0x0 0xff>;
682 vendor-id = <0x104c>;
683 device-id = <0xb00d>;
684 msi-map = <0x0 &gic_its 0x10000 0x10000>;
686 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
687 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
688 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
693 reg = <0x00 0x02910000 0x00 0x1000>,
694 <0x00 0x02917000 0x00 0x400>,
695 <0x00 0x0d800000 0x00 0x00800000>,
696 <0x00 0x18000000 0x00 0x08000000>;
708 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
714 reg = <0x00 0x02920000 0x00 0x1000>,
715 <0x00 0x02927000 0x00 0x400>,
716 <0x00 0x0e000000 0x00 0x00800000>,
717 <0x44 0x00000000 0x00 0x00001000>;
730 bus-range = <0x0 0xff>;
731 vendor-id = <0x104c>;
732 device-id = <0xb00d>;
733 msi-map = <0x0 &gic_its 0x20000 0x10000>;
735 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
736 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
737 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
742 reg = <0x00 0x02920000 0x00 0x1000>,
743 <0x00 0x02927000 0x00 0x400>,
744 <0x00 0x0e000000 0x00 0x00800000>,
745 <0x44 0x00000000 0x00 0x08000000>;
757 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
763 reg = <0x00 0x02930000 0x00 0x1000>,
764 <0x00 0x02937000 0x00 0x400>,
765 <0x00 0x0e800000 0x00 0x00800000>,
766 <0x44 0x10000000 0x00 0x00001000>;
779 bus-range = <0x0 0xff>;
780 vendor-id = <0x104c>;
781 device-id = <0xb00d>;
782 msi-map = <0x0 &gic_its 0x30000 0x10000>;
784 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
785 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
786 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
791 reg = <0x00 0x02930000 0x00 0x1000>,
792 <0x00 0x02937000 0x00 0x400>,
793 <0x00 0x0e800000 0x00 0x00800000>,
794 <0x44 0x10000000 0x00 0x08000000>;
806 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
814 reg = <0x00 0x02800000 0x00 0x100>;
821 clocks = <&k3_clks 146 0>;
827 reg = <0x00 0x02810000 0x00 0x100>;
834 clocks = <&k3_clks 278 0>;
840 reg = <0x00 0x02820000 0x00 0x100>;
847 clocks = <&k3_clks 279 0>;
853 reg = <0x00 0x02830000 0x00 0x100>;
860 clocks = <&k3_clks 280 0>;
866 reg = <0x00 0x02840000 0x00 0x100>;
873 clocks = <&k3_clks 281 0>;
879 reg = <0x00 0x02850000 0x00 0x100>;
886 clocks = <&k3_clks 282 0>;
892 reg = <0x00 0x02860000 0x00 0x100>;
899 clocks = <&k3_clks 283 0>;
905 reg = <0x00 0x02870000 0x00 0x100>;
912 clocks = <&k3_clks 284 0>;
918 reg = <0x00 0x02880000 0x00 0x100>;
925 clocks = <&k3_clks 285 0>;
931 reg = <0x00 0x02890000 0x00 0x100>;
938 clocks = <&k3_clks 286 0>;
944 reg = <0x0 0x00600000 0x0 0x100>;
953 ti,davinci-gpio-unbanked = <0>;
955 clocks = <&k3_clks 105 0>;
961 reg = <0x0 0x00601000 0x0 0x100>;
969 ti,davinci-gpio-unbanked = <0>;
971 clocks = <&k3_clks 106 0>;
977 reg = <0x0 0x00610000 0x0 0x100>;
986 ti,davinci-gpio-unbanked = <0>;
988 clocks = <&k3_clks 107 0>;
994 reg = <0x0 0x00611000 0x0 0x100>;
1002 ti,davinci-gpio-unbanked = <0>;
1004 clocks = <&k3_clks 108 0>;
1010 reg = <0x0 0x00620000 0x0 0x100>;
1019 ti,davinci-gpio-unbanked = <0>;
1021 clocks = <&k3_clks 109 0>;
1027 reg = <0x0 0x00621000 0x0 0x100>;
1035 ti,davinci-gpio-unbanked = <0>;
1037 clocks = <&k3_clks 110 0>;
1043 reg = <0x0 0x00630000 0x0 0x100>;
1052 ti,davinci-gpio-unbanked = <0>;
1054 clocks = <&k3_clks 111 0>;
1060 reg = <0x0 0x00631000 0x0 0x100>;
1068 ti,davinci-gpio-unbanked = <0>;
1070 clocks = <&k3_clks 112 0>;
1076 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
1080 clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
1086 ti,otap-del-sel = <0x2>;
1087 ti,trm-icp = <0x8>;
1088 ti,strobe-sel = <0x77>;
1094 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
1098 clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
1099 assigned-clocks = <&k3_clks 92 0>;
1101 ti,otap-del-sel = <0x2>;
1102 ti,trm-icp = <0x8>;
1103 ti,clkbuf-sel = <0x7>;
1110 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
1114 clocks = <&k3_clks 93 0>, <&k3_clks 93 5>;
1115 assigned-clocks = <&k3_clks 93 0>;
1117 ti,otap-del-sel = <0x2>;
1118 ti,trm-icp = <0x8>;
1119 ti,clkbuf-sel = <0x7>;
1126 reg = <0x00 0x4104000 0x00 0x100>;
1139 reg = <0x00 0x6000000 0x00 0x10000>,
1140 <0x00 0x6010000 0x00 0x10000>,
1141 <0x00 0x6020000 0x00 0x10000>;
1143 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1145 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1156 reg = <0x00 0x4114000 0x00 0x100>;
1169 reg = <0x00 0x6400000 0x00 0x10000>,
1170 <0x00 0x6410000 0x00 0x10000>,
1171 <0x00 0x6420000 0x00 0x10000>;
1173 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1175 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1186 reg = <0x0 0x2000000 0x0 0x100>;
1189 #size-cells = <0>;
1191 clocks = <&k3_clks 187 0>;
1197 reg = <0x0 0x2010000 0x0 0x100>;
1200 #size-cells = <0>;
1202 clocks = <&k3_clks 188 0>;
1208 reg = <0x0 0x2020000 0x0 0x100>;
1211 #size-cells = <0>;
1213 clocks = <&k3_clks 189 0>;
1219 reg = <0x0 0x2030000 0x0 0x100>;
1222 #size-cells = <0>;
1224 clocks = <&k3_clks 190 0>;
1230 reg = <0x0 0x2040000 0x0 0x100>;
1233 #size-cells = <0>;
1235 clocks = <&k3_clks 191 0>;
1241 reg = <0x0 0x2050000 0x0 0x100>;
1244 #size-cells = <0>;
1246 clocks = <&k3_clks 192 0>;
1252 reg = <0x0 0x2060000 0x0 0x100>;
1255 #size-cells = <0>;
1257 clocks = <&k3_clks 193 0>;
1263 reg = <0x0 0x4e80000 0x0 0x100>;
1274 reg = <0x0 0x4e84000 0x0 0x10000>;
1277 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1286 <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1287 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1288 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1289 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1291 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1292 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1293 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1294 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1296 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1297 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1298 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1299 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1301 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1302 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1303 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1304 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1305 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1314 clocks = <&k3_clks 152 0>,
1336 #size-cells = <0>;
1342 reg = <0x0 0x02b00000 0x0 0x2000>,
1343 <0x0 0x02b08000 0x0 0x1000>;
1349 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1361 reg = <0x0 0x02b10000 0x0 0x2000>,
1362 <0x0 0x02b18000 0x0 0x1000>;
1368 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1380 reg = <0x0 0x02b20000 0x0 0x2000>,
1381 <0x0 0x02b28000 0x0 0x1000>;
1387 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1399 reg = <0x0 0x02b30000 0x0 0x2000>,
1400 <0x0 0x02b38000 0x0 0x1000>;
1406 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
1418 reg = <0x0 0x02b40000 0x0 0x2000>,
1419 <0x0 0x02b48000 0x0 0x1000>;
1425 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
1437 reg = <0x0 0x02b50000 0x0 0x2000>,
1438 <0x0 0x02b58000 0x0 0x1000>;
1444 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
1456 reg = <0x0 0x02b60000 0x0 0x2000>,
1457 <0x0 0x02b68000 0x0 0x1000>;
1463 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
1475 reg = <0x0 0x02b70000 0x0 0x2000>,
1476 <0x0 0x02b78000 0x0 0x1000>;
1482 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
1494 reg = <0x0 0x02b80000 0x0 0x2000>,
1495 <0x0 0x02b88000 0x0 0x1000>;
1501 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
1513 reg = <0x0 0x02b90000 0x0 0x2000>,
1514 <0x0 0x02b98000 0x0 0x1000>;
1520 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
1532 reg = <0x0 0x02ba0000 0x0 0x2000>,
1533 <0x0 0x02ba8000 0x0 0x1000>;
1539 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
1551 reg = <0x0 0x02bb0000 0x0 0x2000>,
1552 <0x0 0x02bb8000 0x0 0x1000>;
1558 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
1570 reg = <0x0 0x2200000 0x0 0x100>;
1579 reg = <0x0 0x2210000 0x0 0x100>;
1588 reg = <0x4d 0x80800000 0x00 0x00048000>,
1589 <0x4d 0x80e00000 0x00 0x00008000>,
1590 <0x4d 0x80f00000 0x00 0x00008000>;
1594 ti,sci-proc-ids = <0x03 0xff>;
1601 reg = <0x4d 0x81800000 0x00 0x00048000>,
1602 <0x4d 0x81e00000 0x00 0x00008000>,
1603 <0x4d 0x81f00000 0x00 0x00008000>;
1607 ti,sci-proc-ids = <0x04 0xff>;
1614 reg = <0x00 0x64800000 0x00 0x00080000>,
1615 <0x00 0x64e00000 0x00 0x0000c000>;
1619 ti,sci-proc-ids = <0x30 0xff>;