1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/mux/ti-serdes.h> 10 11/ { 12 cmn_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17 18 cmn_refclk1: clock-cmnrefclk1 { 19 #clock-cells = <0>; 20 compatible = "fixed-clock"; 21 clock-frequency = <0>; 22 }; 23}; 24 25&cbass_main { 26 msmc_ram: sram@70000000 { 27 compatible = "mmio-sram"; 28 reg = <0x0 0x70000000 0x0 0x800000>; 29 #address-cells = <1>; 30 #size-cells = <1>; 31 ranges = <0x0 0x0 0x70000000 0x800000>; 32 33 atf-sram@0 { 34 reg = <0x0 0x20000>; 35 }; 36 }; 37 38 scm_conf: scm-conf@100000 { 39 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 40 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 41 #address-cells = <1>; 42 #size-cells = <1>; 43 ranges = <0x0 0x0 0x00100000 0x1c000>; 44 45 pcie0_ctrl: syscon@4070 { 46 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 47 reg = <0x00004070 0x4>; 48 #address-cells = <1>; 49 #size-cells = <1>; 50 ranges = <0x4070 0x4070 0x4>; 51 }; 52 53 pcie1_ctrl: syscon@4074 { 54 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 55 reg = <0x00004074 0x4>; 56 #address-cells = <1>; 57 #size-cells = <1>; 58 ranges = <0x4074 0x4074 0x4>; 59 }; 60 61 pcie2_ctrl: syscon@4078 { 62 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 63 reg = <0x00004078 0x4>; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 ranges = <0x4078 0x4078 0x4>; 67 }; 68 69 pcie3_ctrl: syscon@407c { 70 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 71 reg = <0x0000407c 0x4>; 72 #address-cells = <1>; 73 #size-cells = <1>; 74 ranges = <0x407c 0x407c 0x4>; 75 }; 76 77 serdes_ln_ctrl: mux@4080 { 78 compatible = "mmio-mux"; 79 reg = <0x00004080 0x50>; 80 #mux-control-cells = <1>; 81 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 82 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 83 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 84 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ 85 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; 86 /* SERDES4 lane0/1/2/3 select */ 87 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 88 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 89 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 90 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, 91 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 92 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 93 }; 94 95 usb_serdes_mux: mux-controller@4000 { 96 compatible = "mmio-mux"; 97 #mux-control-cells = <1>; 98 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ 99 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ 100 }; 101 }; 102 103 gic500: interrupt-controller@1800000 { 104 compatible = "arm,gic-v3"; 105 #address-cells = <2>; 106 #size-cells = <2>; 107 ranges; 108 #interrupt-cells = <3>; 109 interrupt-controller; 110 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 111 <0x00 0x01900000 0x00 0x100000>; /* GICR */ 112 113 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 114 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 115 116 gic_its: msi-controller@1820000 { 117 compatible = "arm,gic-v3-its"; 118 reg = <0x00 0x01820000 0x00 0x10000>; 119 socionext,synquacer-pre-its = <0x1000000 0x400000>; 120 msi-controller; 121 #msi-cells = <1>; 122 }; 123 }; 124 125 main_gpio_intr: interrupt-controller0 { 126 compatible = "ti,sci-intr"; 127 ti,intr-trigger-type = <1>; 128 interrupt-controller; 129 interrupt-parent = <&gic500>; 130 #interrupt-cells = <1>; 131 ti,sci = <&dmsc>; 132 ti,sci-dev-id = <131>; 133 ti,interrupt-ranges = <8 392 56>; 134 }; 135 136 main-navss { 137 compatible = "simple-mfd"; 138 #address-cells = <2>; 139 #size-cells = <2>; 140 ranges; 141 dma-coherent; 142 dma-ranges; 143 144 ti,sci-dev-id = <199>; 145 146 main_navss_intr: interrupt-controller1 { 147 compatible = "ti,sci-intr"; 148 ti,intr-trigger-type = <4>; 149 interrupt-controller; 150 interrupt-parent = <&gic500>; 151 #interrupt-cells = <1>; 152 ti,sci = <&dmsc>; 153 ti,sci-dev-id = <213>; 154 ti,interrupt-ranges = <0 64 64>, 155 <64 448 64>, 156 <128 672 64>; 157 }; 158 159 main_udmass_inta: interrupt-controller@33d00000 { 160 compatible = "ti,sci-inta"; 161 reg = <0x0 0x33d00000 0x0 0x100000>; 162 interrupt-controller; 163 interrupt-parent = <&main_navss_intr>; 164 msi-controller; 165 ti,sci = <&dmsc>; 166 ti,sci-dev-id = <209>; 167 ti,interrupt-ranges = <0 0 256>; 168 }; 169 170 secure_proxy_main: mailbox@32c00000 { 171 compatible = "ti,am654-secure-proxy"; 172 #mbox-cells = <1>; 173 reg-names = "target_data", "rt", "scfg"; 174 reg = <0x00 0x32c00000 0x00 0x100000>, 175 <0x00 0x32400000 0x00 0x100000>, 176 <0x00 0x32800000 0x00 0x100000>; 177 interrupt-names = "rx_011"; 178 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 179 }; 180 181 smmu0: iommu@36600000 { 182 compatible = "arm,smmu-v3"; 183 reg = <0x0 0x36600000 0x0 0x100000>; 184 interrupt-parent = <&gic500>; 185 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 186 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 187 interrupt-names = "eventq", "gerror"; 188 #iommu-cells = <1>; 189 }; 190 191 hwspinlock: spinlock@30e00000 { 192 compatible = "ti,am654-hwspinlock"; 193 reg = <0x00 0x30e00000 0x00 0x1000>; 194 #hwlock-cells = <1>; 195 }; 196 197 mailbox0_cluster0: mailbox@31f80000 { 198 compatible = "ti,am654-mailbox"; 199 reg = <0x00 0x31f80000 0x00 0x200>; 200 #mbox-cells = <1>; 201 ti,mbox-num-users = <4>; 202 ti,mbox-num-fifos = <16>; 203 interrupt-parent = <&main_navss_intr>; 204 }; 205 206 mailbox0_cluster1: mailbox@31f81000 { 207 compatible = "ti,am654-mailbox"; 208 reg = <0x00 0x31f81000 0x00 0x200>; 209 #mbox-cells = <1>; 210 ti,mbox-num-users = <4>; 211 ti,mbox-num-fifos = <16>; 212 interrupt-parent = <&main_navss_intr>; 213 }; 214 215 mailbox0_cluster2: mailbox@31f82000 { 216 compatible = "ti,am654-mailbox"; 217 reg = <0x00 0x31f82000 0x00 0x200>; 218 #mbox-cells = <1>; 219 ti,mbox-num-users = <4>; 220 ti,mbox-num-fifos = <16>; 221 interrupt-parent = <&main_navss_intr>; 222 }; 223 224 mailbox0_cluster3: mailbox@31f83000 { 225 compatible = "ti,am654-mailbox"; 226 reg = <0x00 0x31f83000 0x00 0x200>; 227 #mbox-cells = <1>; 228 ti,mbox-num-users = <4>; 229 ti,mbox-num-fifos = <16>; 230 interrupt-parent = <&main_navss_intr>; 231 }; 232 233 mailbox0_cluster4: mailbox@31f84000 { 234 compatible = "ti,am654-mailbox"; 235 reg = <0x00 0x31f84000 0x00 0x200>; 236 #mbox-cells = <1>; 237 ti,mbox-num-users = <4>; 238 ti,mbox-num-fifos = <16>; 239 interrupt-parent = <&main_navss_intr>; 240 }; 241 242 mailbox0_cluster5: mailbox@31f85000 { 243 compatible = "ti,am654-mailbox"; 244 reg = <0x00 0x31f85000 0x00 0x200>; 245 #mbox-cells = <1>; 246 ti,mbox-num-users = <4>; 247 ti,mbox-num-fifos = <16>; 248 interrupt-parent = <&main_navss_intr>; 249 }; 250 251 mailbox0_cluster6: mailbox@31f86000 { 252 compatible = "ti,am654-mailbox"; 253 reg = <0x00 0x31f86000 0x00 0x200>; 254 #mbox-cells = <1>; 255 ti,mbox-num-users = <4>; 256 ti,mbox-num-fifos = <16>; 257 interrupt-parent = <&main_navss_intr>; 258 }; 259 260 mailbox0_cluster7: mailbox@31f87000 { 261 compatible = "ti,am654-mailbox"; 262 reg = <0x00 0x31f87000 0x00 0x200>; 263 #mbox-cells = <1>; 264 ti,mbox-num-users = <4>; 265 ti,mbox-num-fifos = <16>; 266 interrupt-parent = <&main_navss_intr>; 267 }; 268 269 mailbox0_cluster8: mailbox@31f88000 { 270 compatible = "ti,am654-mailbox"; 271 reg = <0x00 0x31f88000 0x00 0x200>; 272 #mbox-cells = <1>; 273 ti,mbox-num-users = <4>; 274 ti,mbox-num-fifos = <16>; 275 interrupt-parent = <&main_navss_intr>; 276 }; 277 278 mailbox0_cluster9: mailbox@31f89000 { 279 compatible = "ti,am654-mailbox"; 280 reg = <0x00 0x31f89000 0x00 0x200>; 281 #mbox-cells = <1>; 282 ti,mbox-num-users = <4>; 283 ti,mbox-num-fifos = <16>; 284 interrupt-parent = <&main_navss_intr>; 285 }; 286 287 mailbox0_cluster10: mailbox@31f8a000 { 288 compatible = "ti,am654-mailbox"; 289 reg = <0x00 0x31f8a000 0x00 0x200>; 290 #mbox-cells = <1>; 291 ti,mbox-num-users = <4>; 292 ti,mbox-num-fifos = <16>; 293 interrupt-parent = <&main_navss_intr>; 294 }; 295 296 mailbox0_cluster11: mailbox@31f8b000 { 297 compatible = "ti,am654-mailbox"; 298 reg = <0x00 0x31f8b000 0x00 0x200>; 299 #mbox-cells = <1>; 300 ti,mbox-num-users = <4>; 301 ti,mbox-num-fifos = <16>; 302 interrupt-parent = <&main_navss_intr>; 303 }; 304 305 main_ringacc: ringacc@3c000000 { 306 compatible = "ti,am654-navss-ringacc"; 307 reg = <0x0 0x3c000000 0x0 0x400000>, 308 <0x0 0x38000000 0x0 0x400000>, 309 <0x0 0x31120000 0x0 0x100>, 310 <0x0 0x33000000 0x0 0x40000>; 311 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 312 ti,num-rings = <1024>; 313 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 314 ti,sci = <&dmsc>; 315 ti,sci-dev-id = <211>; 316 msi-parent = <&main_udmass_inta>; 317 }; 318 319 main_udmap: dma-controller@31150000 { 320 compatible = "ti,j721e-navss-main-udmap"; 321 reg = <0x0 0x31150000 0x0 0x100>, 322 <0x0 0x34000000 0x0 0x100000>, 323 <0x0 0x35000000 0x0 0x100000>; 324 reg-names = "gcfg", "rchanrt", "tchanrt"; 325 msi-parent = <&main_udmass_inta>; 326 #dma-cells = <1>; 327 328 ti,sci = <&dmsc>; 329 ti,sci-dev-id = <212>; 330 ti,ringacc = <&main_ringacc>; 331 332 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 333 <0x0f>, /* TX_HCHAN */ 334 <0x10>; /* TX_UHCHAN */ 335 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 336 <0x0b>, /* RX_HCHAN */ 337 <0x0c>; /* RX_UHCHAN */ 338 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 339 }; 340 341 cpts@310d0000 { 342 compatible = "ti,j721e-cpts"; 343 reg = <0x0 0x310d0000 0x0 0x400>; 344 reg-names = "cpts"; 345 clocks = <&k3_clks 201 1>; 346 clock-names = "cpts"; 347 interrupts-extended = <&main_navss_intr 391>; 348 interrupt-names = "cpts"; 349 ti,cpts-periodic-outputs = <6>; 350 ti,cpts-ext-ts-inputs = <8>; 351 }; 352 }; 353 354 main_crypto: crypto@4e00000 { 355 compatible = "ti,j721e-sa2ul"; 356 reg = <0x0 0x4e00000 0x0 0x1200>; 357 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 358 #address-cells = <2>; 359 #size-cells = <2>; 360 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 361 362 status = "okay"; 363 364 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 365 <&main_udmap 0x4001>; 366 dma-names = "tx", "rx1", "rx2"; 367 dma-coherent; 368 369 rng: rng@4e10000 { 370 compatible = "inside-secure,safexcel-eip76"; 371 reg = <0x0 0x4e10000 0x0 0x7d>; 372 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&k3_clks 264 1>; 374 }; 375 }; 376 377 main_pmx0: pinctrl@11c000 { 378 compatible = "pinctrl-single"; 379 /* Proxy 0 addressing */ 380 reg = <0x0 0x11c000 0x0 0x2b4>; 381 #pinctrl-cells = <1>; 382 pinctrl-single,register-width = <32>; 383 pinctrl-single,function-mask = <0xffffffff>; 384 }; 385 386 serdes_wiz0: wiz@5000000 { 387 compatible = "ti,j721e-wiz-16g"; 388 #address-cells = <1>; 389 #size-cells = <1>; 390 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 391 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; 392 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 393 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 394 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 395 num-lanes = <2>; 396 #reset-cells = <1>; 397 ranges = <0x5000000 0x0 0x5000000 0x10000>; 398 399 wiz0_pll0_refclk: pll0-refclk { 400 clocks = <&k3_clks 292 11>, <&cmn_refclk>; 401 #clock-cells = <0>; 402 assigned-clocks = <&wiz0_pll0_refclk>; 403 assigned-clock-parents = <&k3_clks 292 11>; 404 }; 405 406 wiz0_pll1_refclk: pll1-refclk { 407 clocks = <&k3_clks 292 0>, <&cmn_refclk1>; 408 #clock-cells = <0>; 409 assigned-clocks = <&wiz0_pll1_refclk>; 410 assigned-clock-parents = <&k3_clks 292 0>; 411 }; 412 413 wiz0_refclk_dig: refclk-dig { 414 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; 415 #clock-cells = <0>; 416 assigned-clocks = <&wiz0_refclk_dig>; 417 assigned-clock-parents = <&k3_clks 292 11>; 418 }; 419 420 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 421 clocks = <&wiz0_refclk_dig>; 422 #clock-cells = <0>; 423 }; 424 425 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 426 clocks = <&wiz0_pll1_refclk>; 427 #clock-cells = <0>; 428 }; 429 430 serdes0: serdes@5000000 { 431 compatible = "ti,sierra-phy-t0"; 432 reg-names = "serdes"; 433 reg = <0x5000000 0x10000>; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 resets = <&serdes_wiz0 0>; 437 reset-names = "sierra_reset"; 438 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; 439 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 440 }; 441 }; 442 443 serdes_wiz1: wiz@5010000 { 444 compatible = "ti,j721e-wiz-16g"; 445 #address-cells = <1>; 446 #size-cells = <1>; 447 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 448 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; 449 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 450 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; 451 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; 452 num-lanes = <2>; 453 #reset-cells = <1>; 454 ranges = <0x5010000 0x0 0x5010000 0x10000>; 455 456 wiz1_pll0_refclk: pll0-refclk { 457 clocks = <&k3_clks 293 13>, <&cmn_refclk>; 458 #clock-cells = <0>; 459 assigned-clocks = <&wiz1_pll0_refclk>; 460 assigned-clock-parents = <&k3_clks 293 13>; 461 }; 462 463 wiz1_pll1_refclk: pll1-refclk { 464 clocks = <&k3_clks 293 0>, <&cmn_refclk1>; 465 #clock-cells = <0>; 466 assigned-clocks = <&wiz1_pll1_refclk>; 467 assigned-clock-parents = <&k3_clks 293 0>; 468 }; 469 470 wiz1_refclk_dig: refclk-dig { 471 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; 472 #clock-cells = <0>; 473 assigned-clocks = <&wiz1_refclk_dig>; 474 assigned-clock-parents = <&k3_clks 293 13>; 475 }; 476 477 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ 478 clocks = <&wiz1_refclk_dig>; 479 #clock-cells = <0>; 480 }; 481 482 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 483 clocks = <&wiz1_pll1_refclk>; 484 #clock-cells = <0>; 485 }; 486 487 serdes1: serdes@5010000 { 488 compatible = "ti,sierra-phy-t0"; 489 reg-names = "serdes"; 490 reg = <0x5010000 0x10000>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 resets = <&serdes_wiz1 0>; 494 reset-names = "sierra_reset"; 495 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>; 496 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 497 }; 498 }; 499 500 serdes_wiz2: wiz@5020000 { 501 compatible = "ti,j721e-wiz-16g"; 502 #address-cells = <1>; 503 #size-cells = <1>; 504 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 505 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; 506 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 507 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; 508 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; 509 num-lanes = <2>; 510 #reset-cells = <1>; 511 ranges = <0x5020000 0x0 0x5020000 0x10000>; 512 513 wiz2_pll0_refclk: pll0-refclk { 514 clocks = <&k3_clks 294 11>, <&cmn_refclk>; 515 #clock-cells = <0>; 516 assigned-clocks = <&wiz2_pll0_refclk>; 517 assigned-clock-parents = <&k3_clks 294 11>; 518 }; 519 520 wiz2_pll1_refclk: pll1-refclk { 521 clocks = <&k3_clks 294 0>, <&cmn_refclk1>; 522 #clock-cells = <0>; 523 assigned-clocks = <&wiz2_pll1_refclk>; 524 assigned-clock-parents = <&k3_clks 294 0>; 525 }; 526 527 wiz2_refclk_dig: refclk-dig { 528 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; 529 #clock-cells = <0>; 530 assigned-clocks = <&wiz2_refclk_dig>; 531 assigned-clock-parents = <&k3_clks 294 11>; 532 }; 533 534 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { 535 clocks = <&wiz2_refclk_dig>; 536 #clock-cells = <0>; 537 }; 538 539 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 540 clocks = <&wiz2_pll1_refclk>; 541 #clock-cells = <0>; 542 }; 543 544 serdes2: serdes@5020000 { 545 compatible = "ti,sierra-phy-t0"; 546 reg-names = "serdes"; 547 reg = <0x5020000 0x10000>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 resets = <&serdes_wiz2 0>; 551 reset-names = "sierra_reset"; 552 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>; 553 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 554 }; 555 }; 556 557 serdes_wiz3: wiz@5030000 { 558 compatible = "ti,j721e-wiz-16g"; 559 #address-cells = <1>; 560 #size-cells = <1>; 561 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 562 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; 563 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 564 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; 565 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; 566 num-lanes = <2>; 567 #reset-cells = <1>; 568 ranges = <0x5030000 0x0 0x5030000 0x10000>; 569 570 wiz3_pll0_refclk: pll0-refclk { 571 clocks = <&k3_clks 295 9>, <&cmn_refclk>; 572 #clock-cells = <0>; 573 assigned-clocks = <&wiz3_pll0_refclk>; 574 assigned-clock-parents = <&k3_clks 295 9>; 575 }; 576 577 wiz3_pll1_refclk: pll1-refclk { 578 clocks = <&k3_clks 295 0>, <&cmn_refclk1>; 579 #clock-cells = <0>; 580 assigned-clocks = <&wiz3_pll1_refclk>; 581 assigned-clock-parents = <&k3_clks 295 0>; 582 }; 583 584 wiz3_refclk_dig: refclk-dig { 585 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; 586 #clock-cells = <0>; 587 assigned-clocks = <&wiz3_refclk_dig>; 588 assigned-clock-parents = <&k3_clks 295 9>; 589 }; 590 591 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { 592 clocks = <&wiz3_refclk_dig>; 593 #clock-cells = <0>; 594 }; 595 596 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 597 clocks = <&wiz3_pll1_refclk>; 598 #clock-cells = <0>; 599 }; 600 601 serdes3: serdes@5030000 { 602 compatible = "ti,sierra-phy-t0"; 603 reg-names = "serdes"; 604 reg = <0x5030000 0x10000>; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 resets = <&serdes_wiz3 0>; 608 reset-names = "sierra_reset"; 609 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>; 610 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 611 }; 612 }; 613 614 pcie0_rc: pcie@2900000 { 615 compatible = "ti,j721e-pcie-host"; 616 reg = <0x00 0x02900000 0x00 0x1000>, 617 <0x00 0x02907000 0x00 0x400>, 618 <0x00 0x0d000000 0x00 0x00800000>, 619 <0x00 0x10000000 0x00 0x00001000>; 620 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 621 interrupt-names = "link_state"; 622 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 623 device_type = "pci"; 624 ti,syscon-pcie-ctrl = <&pcie0_ctrl>; 625 max-link-speed = <3>; 626 num-lanes = <2>; 627 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 628 clocks = <&k3_clks 239 1>; 629 clock-names = "fck"; 630 #address-cells = <3>; 631 #size-cells = <2>; 632 bus-range = <0x0 0xff>; 633 vendor-id = <0x104c>; 634 device-id = <0xb00d>; 635 msi-map = <0x0 &gic_its 0x0 0x10000>; 636 dma-coherent; 637 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, 638 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; 639 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 640 }; 641 642 pcie0_ep: pcie-ep@2900000 { 643 compatible = "ti,j721e-pcie-ep"; 644 reg = <0x00 0x02900000 0x00 0x1000>, 645 <0x00 0x02907000 0x00 0x400>, 646 <0x00 0x0d000000 0x00 0x00800000>, 647 <0x00 0x10000000 0x00 0x08000000>; 648 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 649 interrupt-names = "link_state"; 650 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 651 ti,syscon-pcie-ctrl = <&pcie0_ctrl>; 652 max-link-speed = <3>; 653 num-lanes = <2>; 654 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 655 clocks = <&k3_clks 239 1>; 656 clock-names = "fck"; 657 cdns,max-outbound-regions = <16>; 658 max-functions = /bits/ 8 <6>; 659 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 660 dma-coherent; 661 }; 662 663 pcie1_rc: pcie@2910000 { 664 compatible = "ti,j721e-pcie-host"; 665 reg = <0x00 0x02910000 0x00 0x1000>, 666 <0x00 0x02917000 0x00 0x400>, 667 <0x00 0x0d800000 0x00 0x00800000>, 668 <0x00 0x18000000 0x00 0x00001000>; 669 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 670 interrupt-names = "link_state"; 671 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 672 device_type = "pci"; 673 ti,syscon-pcie-ctrl = <&pcie1_ctrl>; 674 max-link-speed = <3>; 675 num-lanes = <2>; 676 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 677 clocks = <&k3_clks 240 1>; 678 clock-names = "fck"; 679 #address-cells = <3>; 680 #size-cells = <2>; 681 bus-range = <0x0 0xff>; 682 vendor-id = <0x104c>; 683 device-id = <0xb00d>; 684 msi-map = <0x0 &gic_its 0x10000 0x10000>; 685 dma-coherent; 686 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, 687 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; 688 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 689 }; 690 691 pcie1_ep: pcie-ep@2910000 { 692 compatible = "ti,j721e-pcie-ep"; 693 reg = <0x00 0x02910000 0x00 0x1000>, 694 <0x00 0x02917000 0x00 0x400>, 695 <0x00 0x0d800000 0x00 0x00800000>, 696 <0x00 0x18000000 0x00 0x08000000>; 697 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 698 interrupt-names = "link_state"; 699 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 700 ti,syscon-pcie-ctrl = <&pcie1_ctrl>; 701 max-link-speed = <3>; 702 num-lanes = <2>; 703 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 704 clocks = <&k3_clks 240 1>; 705 clock-names = "fck"; 706 cdns,max-outbound-regions = <16>; 707 max-functions = /bits/ 8 <6>; 708 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 709 dma-coherent; 710 }; 711 712 pcie2_rc: pcie@2920000 { 713 compatible = "ti,j721e-pcie-host"; 714 reg = <0x00 0x02920000 0x00 0x1000>, 715 <0x00 0x02927000 0x00 0x400>, 716 <0x00 0x0e000000 0x00 0x00800000>, 717 <0x44 0x00000000 0x00 0x00001000>; 718 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 719 interrupt-names = "link_state"; 720 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 721 device_type = "pci"; 722 ti,syscon-pcie-ctrl = <&pcie2_ctrl>; 723 max-link-speed = <3>; 724 num-lanes = <2>; 725 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 726 clocks = <&k3_clks 241 1>; 727 clock-names = "fck"; 728 #address-cells = <3>; 729 #size-cells = <2>; 730 bus-range = <0x0 0xff>; 731 vendor-id = <0x104c>; 732 device-id = <0xb00d>; 733 msi-map = <0x0 &gic_its 0x20000 0x10000>; 734 dma-coherent; 735 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 736 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 737 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 738 }; 739 740 pcie2_ep: pcie-ep@2920000 { 741 compatible = "ti,j721e-pcie-ep"; 742 reg = <0x00 0x02920000 0x00 0x1000>, 743 <0x00 0x02927000 0x00 0x400>, 744 <0x00 0x0e000000 0x00 0x00800000>, 745 <0x44 0x00000000 0x00 0x08000000>; 746 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 747 interrupt-names = "link_state"; 748 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 749 ti,syscon-pcie-ctrl = <&pcie2_ctrl>; 750 max-link-speed = <3>; 751 num-lanes = <2>; 752 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 753 clocks = <&k3_clks 241 1>; 754 clock-names = "fck"; 755 cdns,max-outbound-regions = <16>; 756 max-functions = /bits/ 8 <6>; 757 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 758 dma-coherent; 759 }; 760 761 pcie3_rc: pcie@2930000 { 762 compatible = "ti,j721e-pcie-host"; 763 reg = <0x00 0x02930000 0x00 0x1000>, 764 <0x00 0x02937000 0x00 0x400>, 765 <0x00 0x0e800000 0x00 0x00800000>, 766 <0x44 0x10000000 0x00 0x00001000>; 767 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 768 interrupt-names = "link_state"; 769 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 770 device_type = "pci"; 771 ti,syscon-pcie-ctrl = <&pcie3_ctrl>; 772 max-link-speed = <3>; 773 num-lanes = <2>; 774 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 775 clocks = <&k3_clks 242 1>; 776 clock-names = "fck"; 777 #address-cells = <3>; 778 #size-cells = <2>; 779 bus-range = <0x0 0xff>; 780 vendor-id = <0x104c>; 781 device-id = <0xb00d>; 782 msi-map = <0x0 &gic_its 0x30000 0x10000>; 783 dma-coherent; 784 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 785 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 786 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 787 }; 788 789 pcie3_ep: pcie-ep@2930000 { 790 compatible = "ti,j721e-pcie-ep"; 791 reg = <0x00 0x02930000 0x00 0x1000>, 792 <0x00 0x02937000 0x00 0x400>, 793 <0x00 0x0e800000 0x00 0x00800000>, 794 <0x44 0x10000000 0x00 0x08000000>; 795 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 796 interrupt-names = "link_state"; 797 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 798 ti,syscon-pcie-ctrl = <&pcie3_ctrl>; 799 max-link-speed = <3>; 800 num-lanes = <2>; 801 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 802 clocks = <&k3_clks 242 1>; 803 clock-names = "fck"; 804 cdns,max-outbound-regions = <16>; 805 max-functions = /bits/ 8 <6>; 806 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 807 dma-coherent; 808 #address-cells = <2>; 809 #size-cells = <2>; 810 }; 811 812 main_uart0: serial@2800000 { 813 compatible = "ti,j721e-uart", "ti,am654-uart"; 814 reg = <0x00 0x02800000 0x00 0x100>; 815 reg-shift = <2>; 816 reg-io-width = <4>; 817 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 818 clock-frequency = <48000000>; 819 current-speed = <115200>; 820 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 821 clocks = <&k3_clks 146 0>; 822 clock-names = "fclk"; 823 }; 824 825 main_uart1: serial@2810000 { 826 compatible = "ti,j721e-uart", "ti,am654-uart"; 827 reg = <0x00 0x02810000 0x00 0x100>; 828 reg-shift = <2>; 829 reg-io-width = <4>; 830 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 831 clock-frequency = <48000000>; 832 current-speed = <115200>; 833 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 834 clocks = <&k3_clks 278 0>; 835 clock-names = "fclk"; 836 }; 837 838 main_uart2: serial@2820000 { 839 compatible = "ti,j721e-uart", "ti,am654-uart"; 840 reg = <0x00 0x02820000 0x00 0x100>; 841 reg-shift = <2>; 842 reg-io-width = <4>; 843 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 844 clock-frequency = <48000000>; 845 current-speed = <115200>; 846 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 847 clocks = <&k3_clks 279 0>; 848 clock-names = "fclk"; 849 }; 850 851 main_uart3: serial@2830000 { 852 compatible = "ti,j721e-uart", "ti,am654-uart"; 853 reg = <0x00 0x02830000 0x00 0x100>; 854 reg-shift = <2>; 855 reg-io-width = <4>; 856 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 857 clock-frequency = <48000000>; 858 current-speed = <115200>; 859 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 860 clocks = <&k3_clks 280 0>; 861 clock-names = "fclk"; 862 }; 863 864 main_uart4: serial@2840000 { 865 compatible = "ti,j721e-uart", "ti,am654-uart"; 866 reg = <0x00 0x02840000 0x00 0x100>; 867 reg-shift = <2>; 868 reg-io-width = <4>; 869 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 870 clock-frequency = <48000000>; 871 current-speed = <115200>; 872 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 873 clocks = <&k3_clks 281 0>; 874 clock-names = "fclk"; 875 }; 876 877 main_uart5: serial@2850000 { 878 compatible = "ti,j721e-uart", "ti,am654-uart"; 879 reg = <0x00 0x02850000 0x00 0x100>; 880 reg-shift = <2>; 881 reg-io-width = <4>; 882 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 883 clock-frequency = <48000000>; 884 current-speed = <115200>; 885 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 886 clocks = <&k3_clks 282 0>; 887 clock-names = "fclk"; 888 }; 889 890 main_uart6: serial@2860000 { 891 compatible = "ti,j721e-uart", "ti,am654-uart"; 892 reg = <0x00 0x02860000 0x00 0x100>; 893 reg-shift = <2>; 894 reg-io-width = <4>; 895 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 896 clock-frequency = <48000000>; 897 current-speed = <115200>; 898 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 899 clocks = <&k3_clks 283 0>; 900 clock-names = "fclk"; 901 }; 902 903 main_uart7: serial@2870000 { 904 compatible = "ti,j721e-uart", "ti,am654-uart"; 905 reg = <0x00 0x02870000 0x00 0x100>; 906 reg-shift = <2>; 907 reg-io-width = <4>; 908 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 909 clock-frequency = <48000000>; 910 current-speed = <115200>; 911 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 912 clocks = <&k3_clks 284 0>; 913 clock-names = "fclk"; 914 }; 915 916 main_uart8: serial@2880000 { 917 compatible = "ti,j721e-uart", "ti,am654-uart"; 918 reg = <0x00 0x02880000 0x00 0x100>; 919 reg-shift = <2>; 920 reg-io-width = <4>; 921 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 922 clock-frequency = <48000000>; 923 current-speed = <115200>; 924 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 925 clocks = <&k3_clks 285 0>; 926 clock-names = "fclk"; 927 }; 928 929 main_uart9: serial@2890000 { 930 compatible = "ti,j721e-uart", "ti,am654-uart"; 931 reg = <0x00 0x02890000 0x00 0x100>; 932 reg-shift = <2>; 933 reg-io-width = <4>; 934 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 935 clock-frequency = <48000000>; 936 current-speed = <115200>; 937 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 938 clocks = <&k3_clks 286 0>; 939 clock-names = "fclk"; 940 }; 941 942 main_gpio0: gpio@600000 { 943 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 944 reg = <0x0 0x00600000 0x0 0x100>; 945 gpio-controller; 946 #gpio-cells = <2>; 947 interrupt-parent = <&main_gpio_intr>; 948 interrupts = <256>, <257>, <258>, <259>, 949 <260>, <261>, <262>, <263>; 950 interrupt-controller; 951 #interrupt-cells = <2>; 952 ti,ngpio = <128>; 953 ti,davinci-gpio-unbanked = <0>; 954 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 955 clocks = <&k3_clks 105 0>; 956 clock-names = "gpio"; 957 }; 958 959 main_gpio1: gpio@601000 { 960 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 961 reg = <0x0 0x00601000 0x0 0x100>; 962 gpio-controller; 963 #gpio-cells = <2>; 964 interrupt-parent = <&main_gpio_intr>; 965 interrupts = <288>, <289>, <290>; 966 interrupt-controller; 967 #interrupt-cells = <2>; 968 ti,ngpio = <36>; 969 ti,davinci-gpio-unbanked = <0>; 970 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 971 clocks = <&k3_clks 106 0>; 972 clock-names = "gpio"; 973 }; 974 975 main_gpio2: gpio@610000 { 976 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 977 reg = <0x0 0x00610000 0x0 0x100>; 978 gpio-controller; 979 #gpio-cells = <2>; 980 interrupt-parent = <&main_gpio_intr>; 981 interrupts = <264>, <265>, <266>, <267>, 982 <268>, <269>, <270>, <271>; 983 interrupt-controller; 984 #interrupt-cells = <2>; 985 ti,ngpio = <128>; 986 ti,davinci-gpio-unbanked = <0>; 987 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 988 clocks = <&k3_clks 107 0>; 989 clock-names = "gpio"; 990 }; 991 992 main_gpio3: gpio@611000 { 993 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 994 reg = <0x0 0x00611000 0x0 0x100>; 995 gpio-controller; 996 #gpio-cells = <2>; 997 interrupt-parent = <&main_gpio_intr>; 998 interrupts = <292>, <293>, <294>; 999 interrupt-controller; 1000 #interrupt-cells = <2>; 1001 ti,ngpio = <36>; 1002 ti,davinci-gpio-unbanked = <0>; 1003 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 1004 clocks = <&k3_clks 108 0>; 1005 clock-names = "gpio"; 1006 }; 1007 1008 main_gpio4: gpio@620000 { 1009 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1010 reg = <0x0 0x00620000 0x0 0x100>; 1011 gpio-controller; 1012 #gpio-cells = <2>; 1013 interrupt-parent = <&main_gpio_intr>; 1014 interrupts = <272>, <273>, <274>, <275>, 1015 <276>, <277>, <278>, <279>; 1016 interrupt-controller; 1017 #interrupt-cells = <2>; 1018 ti,ngpio = <128>; 1019 ti,davinci-gpio-unbanked = <0>; 1020 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 1021 clocks = <&k3_clks 109 0>; 1022 clock-names = "gpio"; 1023 }; 1024 1025 main_gpio5: gpio@621000 { 1026 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1027 reg = <0x0 0x00621000 0x0 0x100>; 1028 gpio-controller; 1029 #gpio-cells = <2>; 1030 interrupt-parent = <&main_gpio_intr>; 1031 interrupts = <296>, <297>, <298>; 1032 interrupt-controller; 1033 #interrupt-cells = <2>; 1034 ti,ngpio = <36>; 1035 ti,davinci-gpio-unbanked = <0>; 1036 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 1037 clocks = <&k3_clks 110 0>; 1038 clock-names = "gpio"; 1039 }; 1040 1041 main_gpio6: gpio@630000 { 1042 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1043 reg = <0x0 0x00630000 0x0 0x100>; 1044 gpio-controller; 1045 #gpio-cells = <2>; 1046 interrupt-parent = <&main_gpio_intr>; 1047 interrupts = <280>, <281>, <282>, <283>, 1048 <284>, <285>, <286>, <287>; 1049 interrupt-controller; 1050 #interrupt-cells = <2>; 1051 ti,ngpio = <128>; 1052 ti,davinci-gpio-unbanked = <0>; 1053 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 1054 clocks = <&k3_clks 111 0>; 1055 clock-names = "gpio"; 1056 }; 1057 1058 main_gpio7: gpio@631000 { 1059 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1060 reg = <0x0 0x00631000 0x0 0x100>; 1061 gpio-controller; 1062 #gpio-cells = <2>; 1063 interrupt-parent = <&main_gpio_intr>; 1064 interrupts = <300>, <301>, <302>; 1065 interrupt-controller; 1066 #interrupt-cells = <2>; 1067 ti,ngpio = <36>; 1068 ti,davinci-gpio-unbanked = <0>; 1069 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 1070 clocks = <&k3_clks 112 0>; 1071 clock-names = "gpio"; 1072 }; 1073 1074 main_sdhci0: sdhci@4f80000 { 1075 compatible = "ti,j721e-sdhci-8bit"; 1076 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 1077 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1078 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1079 clock-names = "clk_xin", "clk_ahb"; 1080 clocks = <&k3_clks 91 1>, <&k3_clks 91 0>; 1081 assigned-clocks = <&k3_clks 91 1>; 1082 assigned-clock-parents = <&k3_clks 91 2>; 1083 bus-width = <8>; 1084 mmc-hs400-1_8v; 1085 mmc-ddr-1_8v; 1086 ti,otap-del-sel = <0x2>; 1087 ti,trm-icp = <0x8>; 1088 ti,strobe-sel = <0x77>; 1089 dma-coherent; 1090 }; 1091 1092 main_sdhci1: sdhci@4fb0000 { 1093 compatible = "ti,j721e-sdhci-4bit"; 1094 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 1095 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1096 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1097 clock-names = "clk_xin", "clk_ahb"; 1098 clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; 1099 assigned-clocks = <&k3_clks 92 0>; 1100 assigned-clock-parents = <&k3_clks 92 1>; 1101 ti,otap-del-sel = <0x2>; 1102 ti,trm-icp = <0x8>; 1103 ti,clkbuf-sel = <0x7>; 1104 dma-coherent; 1105 no-1-8-v; 1106 }; 1107 1108 main_sdhci2: sdhci@4f98000 { 1109 compatible = "ti,j721e-sdhci-4bit"; 1110 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 1111 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1112 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1113 clock-names = "clk_xin", "clk_ahb"; 1114 clocks = <&k3_clks 93 0>, <&k3_clks 93 5>; 1115 assigned-clocks = <&k3_clks 93 0>; 1116 assigned-clock-parents = <&k3_clks 93 1>; 1117 ti,otap-del-sel = <0x2>; 1118 ti,trm-icp = <0x8>; 1119 ti,clkbuf-sel = <0x7>; 1120 dma-coherent; 1121 no-1-8-v; 1122 }; 1123 1124 usbss0: cdns-usb@4104000 { 1125 compatible = "ti,j721e-usb"; 1126 reg = <0x00 0x4104000 0x00 0x100>; 1127 dma-coherent; 1128 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 1129 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 1130 clock-names = "ref", "lpm"; 1131 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 1132 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 1133 #address-cells = <2>; 1134 #size-cells = <2>; 1135 ranges; 1136 1137 usb0: usb@6000000 { 1138 compatible = "cdns,usb3"; 1139 reg = <0x00 0x6000000 0x00 0x10000>, 1140 <0x00 0x6010000 0x00 0x10000>, 1141 <0x00 0x6020000 0x00 0x10000>; 1142 reg-names = "otg", "xhci", "dev"; 1143 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1144 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1145 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1146 interrupt-names = "host", 1147 "peripheral", 1148 "otg"; 1149 maximum-speed = "super-speed"; 1150 dr_mode = "otg"; 1151 }; 1152 }; 1153 1154 usbss1: cdns-usb@4114000 { 1155 compatible = "ti,j721e-usb"; 1156 reg = <0x00 0x4114000 0x00 0x100>; 1157 dma-coherent; 1158 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 1159 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 1160 clock-names = "ref", "lpm"; 1161 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 1162 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 1163 #address-cells = <2>; 1164 #size-cells = <2>; 1165 ranges; 1166 1167 usb1: usb@6400000 { 1168 compatible = "cdns,usb3"; 1169 reg = <0x00 0x6400000 0x00 0x10000>, 1170 <0x00 0x6410000 0x00 0x10000>, 1171 <0x00 0x6420000 0x00 0x10000>; 1172 reg-names = "otg", "xhci", "dev"; 1173 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1174 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1175 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1176 interrupt-names = "host", 1177 "peripheral", 1178 "otg"; 1179 maximum-speed = "super-speed"; 1180 dr_mode = "otg"; 1181 }; 1182 }; 1183 1184 main_i2c0: i2c@2000000 { 1185 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1186 reg = <0x0 0x2000000 0x0 0x100>; 1187 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 clock-names = "fck"; 1191 clocks = <&k3_clks 187 0>; 1192 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 1193 }; 1194 1195 main_i2c1: i2c@2010000 { 1196 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1197 reg = <0x0 0x2010000 0x0 0x100>; 1198 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 clock-names = "fck"; 1202 clocks = <&k3_clks 188 0>; 1203 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1204 }; 1205 1206 main_i2c2: i2c@2020000 { 1207 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1208 reg = <0x0 0x2020000 0x0 0x100>; 1209 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1210 #address-cells = <1>; 1211 #size-cells = <0>; 1212 clock-names = "fck"; 1213 clocks = <&k3_clks 189 0>; 1214 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1215 }; 1216 1217 main_i2c3: i2c@2030000 { 1218 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1219 reg = <0x0 0x2030000 0x0 0x100>; 1220 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 clock-names = "fck"; 1224 clocks = <&k3_clks 190 0>; 1225 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1226 }; 1227 1228 main_i2c4: i2c@2040000 { 1229 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1230 reg = <0x0 0x2040000 0x0 0x100>; 1231 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 clock-names = "fck"; 1235 clocks = <&k3_clks 191 0>; 1236 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1237 }; 1238 1239 main_i2c5: i2c@2050000 { 1240 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1241 reg = <0x0 0x2050000 0x0 0x100>; 1242 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1243 #address-cells = <1>; 1244 #size-cells = <0>; 1245 clock-names = "fck"; 1246 clocks = <&k3_clks 192 0>; 1247 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1248 }; 1249 1250 main_i2c6: i2c@2060000 { 1251 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1252 reg = <0x0 0x2060000 0x0 0x100>; 1253 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 clock-names = "fck"; 1257 clocks = <&k3_clks 193 0>; 1258 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1259 }; 1260 1261 ufs_wrapper: ufs-wrapper@4e80000 { 1262 compatible = "ti,j721e-ufs"; 1263 reg = <0x0 0x4e80000 0x0 0x100>; 1264 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1265 clocks = <&k3_clks 277 1>; 1266 assigned-clocks = <&k3_clks 277 1>; 1267 assigned-clock-parents = <&k3_clks 277 4>; 1268 ranges; 1269 #address-cells = <2>; 1270 #size-cells = <2>; 1271 1272 ufs@4e84000 { 1273 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1274 reg = <0x0 0x4e84000 0x0 0x10000>; 1275 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1276 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 1277 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 1278 clock-names = "core_clk", "phy_clk", "ref_clk"; 1279 dma-coherent; 1280 }; 1281 }; 1282 1283 dss: dss@4a00000 { 1284 compatible = "ti,j721e-dss"; 1285 reg = 1286 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1287 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1288 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1289 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1290 1291 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1292 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1293 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1294 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1295 1296 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1297 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1298 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1299 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1300 1301 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1302 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1303 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1304 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1305 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1306 1307 reg-names = "common_m", "common_s0", 1308 "common_s1", "common_s2", 1309 "vidl1", "vidl2","vid1","vid2", 1310 "ovr1", "ovr2", "ovr3", "ovr4", 1311 "vp1", "vp2", "vp3", "vp4", 1312 "wb"; 1313 1314 clocks = <&k3_clks 152 0>, 1315 <&k3_clks 152 1>, 1316 <&k3_clks 152 4>, 1317 <&k3_clks 152 9>, 1318 <&k3_clks 152 13>; 1319 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1320 1321 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1322 1323 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1324 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1325 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1326 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1327 interrupt-names = "common_m", 1328 "common_s0", 1329 "common_s1", 1330 "common_s2"; 1331 1332 status = "disabled"; 1333 1334 dss_ports: ports { 1335 #address-cells = <1>; 1336 #size-cells = <0>; 1337 }; 1338 }; 1339 1340 mcasp0: mcasp@2b00000 { 1341 compatible = "ti,am33xx-mcasp-audio"; 1342 reg = <0x0 0x02b00000 0x0 0x2000>, 1343 <0x0 0x02b08000 0x0 0x1000>; 1344 reg-names = "mpu","dat"; 1345 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 1346 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 1347 interrupt-names = "tx", "rx"; 1348 1349 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 1350 dma-names = "tx", "rx"; 1351 1352 clocks = <&k3_clks 174 1>; 1353 clock-names = "fck"; 1354 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1355 1356 status = "disabled"; 1357 }; 1358 1359 mcasp1: mcasp@2b10000 { 1360 compatible = "ti,am33xx-mcasp-audio"; 1361 reg = <0x0 0x02b10000 0x0 0x2000>, 1362 <0x0 0x02b18000 0x0 0x1000>; 1363 reg-names = "mpu","dat"; 1364 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 1366 interrupt-names = "tx", "rx"; 1367 1368 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 1369 dma-names = "tx", "rx"; 1370 1371 clocks = <&k3_clks 175 1>; 1372 clock-names = "fck"; 1373 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 1374 1375 status = "disabled"; 1376 }; 1377 1378 mcasp2: mcasp@2b20000 { 1379 compatible = "ti,am33xx-mcasp-audio"; 1380 reg = <0x0 0x02b20000 0x0 0x2000>, 1381 <0x0 0x02b28000 0x0 0x1000>; 1382 reg-names = "mpu","dat"; 1383 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 1385 interrupt-names = "tx", "rx"; 1386 1387 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 1388 dma-names = "tx", "rx"; 1389 1390 clocks = <&k3_clks 176 1>; 1391 clock-names = "fck"; 1392 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 1393 1394 status = "disabled"; 1395 }; 1396 1397 mcasp3: mcasp@2b30000 { 1398 compatible = "ti,am33xx-mcasp-audio"; 1399 reg = <0x0 0x02b30000 0x0 0x2000>, 1400 <0x0 0x02b38000 0x0 0x1000>; 1401 reg-names = "mpu","dat"; 1402 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1404 interrupt-names = "tx", "rx"; 1405 1406 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 1407 dma-names = "tx", "rx"; 1408 1409 clocks = <&k3_clks 177 1>; 1410 clock-names = "fck"; 1411 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 1412 1413 status = "disabled"; 1414 }; 1415 1416 mcasp4: mcasp@2b40000 { 1417 compatible = "ti,am33xx-mcasp-audio"; 1418 reg = <0x0 0x02b40000 0x0 0x2000>, 1419 <0x0 0x02b48000 0x0 0x1000>; 1420 reg-names = "mpu","dat"; 1421 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 1423 interrupt-names = "tx", "rx"; 1424 1425 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 1426 dma-names = "tx", "rx"; 1427 1428 clocks = <&k3_clks 178 1>; 1429 clock-names = "fck"; 1430 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 1431 1432 status = "disabled"; 1433 }; 1434 1435 mcasp5: mcasp@2b50000 { 1436 compatible = "ti,am33xx-mcasp-audio"; 1437 reg = <0x0 0x02b50000 0x0 0x2000>, 1438 <0x0 0x02b58000 0x0 0x1000>; 1439 reg-names = "mpu","dat"; 1440 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 1442 interrupt-names = "tx", "rx"; 1443 1444 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 1445 dma-names = "tx", "rx"; 1446 1447 clocks = <&k3_clks 179 1>; 1448 clock-names = "fck"; 1449 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 1450 1451 status = "disabled"; 1452 }; 1453 1454 mcasp6: mcasp@2b60000 { 1455 compatible = "ti,am33xx-mcasp-audio"; 1456 reg = <0x0 0x02b60000 0x0 0x2000>, 1457 <0x0 0x02b68000 0x0 0x1000>; 1458 reg-names = "mpu","dat"; 1459 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 1461 interrupt-names = "tx", "rx"; 1462 1463 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 1464 dma-names = "tx", "rx"; 1465 1466 clocks = <&k3_clks 180 1>; 1467 clock-names = "fck"; 1468 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 1469 1470 status = "disabled"; 1471 }; 1472 1473 mcasp7: mcasp@2b70000 { 1474 compatible = "ti,am33xx-mcasp-audio"; 1475 reg = <0x0 0x02b70000 0x0 0x2000>, 1476 <0x0 0x02b78000 0x0 0x1000>; 1477 reg-names = "mpu","dat"; 1478 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 1480 interrupt-names = "tx", "rx"; 1481 1482 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 1483 dma-names = "tx", "rx"; 1484 1485 clocks = <&k3_clks 181 1>; 1486 clock-names = "fck"; 1487 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 1488 1489 status = "disabled"; 1490 }; 1491 1492 mcasp8: mcasp@2b80000 { 1493 compatible = "ti,am33xx-mcasp-audio"; 1494 reg = <0x0 0x02b80000 0x0 0x2000>, 1495 <0x0 0x02b88000 0x0 0x1000>; 1496 reg-names = "mpu","dat"; 1497 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 1499 interrupt-names = "tx", "rx"; 1500 1501 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 1502 dma-names = "tx", "rx"; 1503 1504 clocks = <&k3_clks 182 1>; 1505 clock-names = "fck"; 1506 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1507 1508 status = "disabled"; 1509 }; 1510 1511 mcasp9: mcasp@2b90000 { 1512 compatible = "ti,am33xx-mcasp-audio"; 1513 reg = <0x0 0x02b90000 0x0 0x2000>, 1514 <0x0 0x02b98000 0x0 0x1000>; 1515 reg-names = "mpu","dat"; 1516 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 1518 interrupt-names = "tx", "rx"; 1519 1520 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 1521 dma-names = "tx", "rx"; 1522 1523 clocks = <&k3_clks 183 1>; 1524 clock-names = "fck"; 1525 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1526 1527 status = "disabled"; 1528 }; 1529 1530 mcasp10: mcasp@2ba0000 { 1531 compatible = "ti,am33xx-mcasp-audio"; 1532 reg = <0x0 0x02ba0000 0x0 0x2000>, 1533 <0x0 0x02ba8000 0x0 0x1000>; 1534 reg-names = "mpu","dat"; 1535 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 1537 interrupt-names = "tx", "rx"; 1538 1539 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 1540 dma-names = "tx", "rx"; 1541 1542 clocks = <&k3_clks 184 1>; 1543 clock-names = "fck"; 1544 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1545 1546 status = "disabled"; 1547 }; 1548 1549 mcasp11: mcasp@2bb0000 { 1550 compatible = "ti,am33xx-mcasp-audio"; 1551 reg = <0x0 0x02bb0000 0x0 0x2000>, 1552 <0x0 0x02bb8000 0x0 0x1000>; 1553 reg-names = "mpu","dat"; 1554 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 1556 interrupt-names = "tx", "rx"; 1557 1558 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 1559 dma-names = "tx", "rx"; 1560 1561 clocks = <&k3_clks 185 1>; 1562 clock-names = "fck"; 1563 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1564 1565 status = "disabled"; 1566 }; 1567 1568 watchdog0: watchdog@2200000 { 1569 compatible = "ti,j7-rti-wdt"; 1570 reg = <0x0 0x2200000 0x0 0x100>; 1571 clocks = <&k3_clks 252 1>; 1572 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1573 assigned-clocks = <&k3_clks 252 1>; 1574 assigned-clock-parents = <&k3_clks 252 5>; 1575 }; 1576 1577 watchdog1: watchdog@2210000 { 1578 compatible = "ti,j7-rti-wdt"; 1579 reg = <0x0 0x2210000 0x0 0x100>; 1580 clocks = <&k3_clks 253 1>; 1581 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1582 assigned-clocks = <&k3_clks 253 1>; 1583 assigned-clock-parents = <&k3_clks 253 5>; 1584 }; 1585 1586 c66_0: dsp@4d80800000 { 1587 compatible = "ti,j721e-c66-dsp"; 1588 reg = <0x4d 0x80800000 0x00 0x00048000>, 1589 <0x4d 0x80e00000 0x00 0x00008000>, 1590 <0x4d 0x80f00000 0x00 0x00008000>; 1591 reg-names = "l2sram", "l1pram", "l1dram"; 1592 ti,sci = <&dmsc>; 1593 ti,sci-dev-id = <142>; 1594 ti,sci-proc-ids = <0x03 0xff>; 1595 resets = <&k3_reset 142 1>; 1596 firmware-name = "j7-c66_0-fw"; 1597 }; 1598 1599 c66_1: dsp@4d81800000 { 1600 compatible = "ti,j721e-c66-dsp"; 1601 reg = <0x4d 0x81800000 0x00 0x00048000>, 1602 <0x4d 0x81e00000 0x00 0x00008000>, 1603 <0x4d 0x81f00000 0x00 0x00008000>; 1604 reg-names = "l2sram", "l1pram", "l1dram"; 1605 ti,sci = <&dmsc>; 1606 ti,sci-dev-id = <143>; 1607 ti,sci-proc-ids = <0x04 0xff>; 1608 resets = <&k3_reset 143 1>; 1609 firmware-name = "j7-c66_1-fw"; 1610 }; 1611 1612 c71_0: dsp@64800000 { 1613 compatible = "ti,j721e-c71-dsp"; 1614 reg = <0x00 0x64800000 0x00 0x00080000>, 1615 <0x00 0x64e00000 0x00 0x0000c000>; 1616 reg-names = "l2sram", "l1dram"; 1617 ti,sci = <&dmsc>; 1618 ti,sci-dev-id = <15>; 1619 ti,sci-proc-ids = <0x30 0xff>; 1620 resets = <&k3_reset 15 1>; 1621 firmware-name = "j7-c71_0-fw"; 1622 }; 1623}; 1624