Home
last modified time | relevance | path

Searched defs:CCR (Results 1 – 16 of 16) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelLowering.cpp4474 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSignedALUO() local
4594 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT() local
4629 SDValue CCR = Cond.getOperand(3); in LowerSELECT() local
4698 SDValue TrueVal, SDValue ARMcc, SDValue CCR, in getCMOV()
5046 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local
5081 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local
5188 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in OptimizeVFPBrcond() local
5237 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBRCOND() local
5291 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local
5300 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local
[all …]
/third_party/cmsis/CMSIS/Core/Include/
Dcore_cm0.h348 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
Dcore_cm1.h348 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
Dcore_sc000.h359 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
Dcore_cm0plus.h366 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
Dcore_sc300.h386 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
Dcore_cm3.h386 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
Dcore_armv8mbl.h394 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
Dcore_cm4.h452 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
Dcore_cm23.h394 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
Dcore_cm7.h467 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
Dcore_armv8mml.h511 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
Dcore_cm35p.h511 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
Dcore_cm33.h511 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
Dcore_cm55.h518 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
Dcore_armv81mml.h518 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member