1 /**************************************************************************//**
2 * @file core_sc000.h
3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
4 * @version V5.0.7
5 * @date 27. March 2020
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef __CORE_SC000_H_GENERIC
32 #define __CORE_SC000_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup SC000
60 @{
61 */
62
63 #include "cmsis_version.h"
64
65 /* CMSIS SC000 definitions */
66 #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67 #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
69 __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
71 #define __CORTEX_SC (000U) /*!< Cortex secure core */
72
73 /** __FPU_USED indicates whether an FPU is used or not.
74 This core does not support an FPU at all
75 */
76 #define __FPU_USED 0U
77
78 #if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81 #endif
82
83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84 #if defined __ARM_FP
85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86 #endif
87
88 #elif defined ( __GNUC__ )
89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91 #endif
92
93 #elif defined ( __ICCARM__ )
94 #if defined __ARMVFP__
95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96 #endif
97
98 #elif defined ( __TI_ARM__ )
99 #if defined __TI_VFP_SUPPORT__
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101 #endif
102
103 #elif defined ( __TASKING__ )
104 #if defined __FPU_VFP__
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #endif
107
108 #elif defined ( __CSMC__ )
109 #if ( __CSMC__ & 0x400U)
110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111 #endif
112
113 #endif
114
115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
116
117
118 #ifdef __cplusplus
119 }
120 #endif
121
122 #endif /* __CORE_SC000_H_GENERIC */
123
124 #ifndef __CMSIS_GENERIC
125
126 #ifndef __CORE_SC000_H_DEPENDANT
127 #define __CORE_SC000_H_DEPENDANT
128
129 #ifdef __cplusplus
130 extern "C" {
131 #endif
132
133 /* check device defines and use defaults */
134 #if defined __CHECK_DEVICE_DEFINES
135 #ifndef __SC000_REV
136 #define __SC000_REV 0x0000U
137 #warning "__SC000_REV not defined in device header file; using default!"
138 #endif
139
140 #ifndef __MPU_PRESENT
141 #define __MPU_PRESENT 0U
142 #warning "__MPU_PRESENT not defined in device header file; using default!"
143 #endif
144
145 #ifndef __VTOR_PRESENT
146 #define __VTOR_PRESENT 0U
147 #warning "__VTOR_PRESENT not defined in device header file; using default!"
148 #endif
149
150 #ifndef __NVIC_PRIO_BITS
151 #define __NVIC_PRIO_BITS 2U
152 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
153 #endif
154
155 #ifndef __Vendor_SysTickConfig
156 #define __Vendor_SysTickConfig 0U
157 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
158 #endif
159 #endif
160
161 /* IO definitions (access restrictions to peripheral registers) */
162 /**
163 \defgroup CMSIS_glob_defs CMSIS Global Defines
164
165 <strong>IO Type Qualifiers</strong> are used
166 \li to specify the access to peripheral variables.
167 \li for automatic generation of peripheral register debug information.
168 */
169 #ifdef __cplusplus
170 #define __I volatile /*!< Defines 'read only' permissions */
171 #else
172 #define __I volatile const /*!< Defines 'read only' permissions */
173 #endif
174 #define __O volatile /*!< Defines 'write only' permissions */
175 #define __IO volatile /*!< Defines 'read / write' permissions */
176
177 /* following defines should be used for structure members */
178 #define __IM volatile const /*! Defines 'read only' structure member permissions */
179 #define __OM volatile /*! Defines 'write only' structure member permissions */
180 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
181
182 /*@} end of group SC000 */
183
184
185
186 /*******************************************************************************
187 * Register Abstraction
188 Core Register contain:
189 - Core Register
190 - Core NVIC Register
191 - Core SCB Register
192 - Core SysTick Register
193 - Core MPU Register
194 ******************************************************************************/
195 /**
196 \defgroup CMSIS_core_register Defines and Type Definitions
197 \brief Type definitions and defines for Cortex-M processor based devices.
198 */
199
200 /**
201 \ingroup CMSIS_core_register
202 \defgroup CMSIS_CORE Status and Control Registers
203 \brief Core Register type definitions.
204 @{
205 */
206
207 /**
208 \brief Union type to access the Application Program Status Register (APSR).
209 */
210 typedef union
211 {
212 struct
213 {
214 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
215 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
216 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
217 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
218 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
219 } b; /*!< Structure used for bit access */
220 uint32_t w; /*!< Type used for word access */
221 } APSR_Type;
222
223 /* APSR Register Definitions */
224 #define APSR_N_Pos 31U /*!< APSR: N Position */
225 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
226
227 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
228 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
229
230 #define APSR_C_Pos 29U /*!< APSR: C Position */
231 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
232
233 #define APSR_V_Pos 28U /*!< APSR: V Position */
234 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
235
236
237 /**
238 \brief Union type to access the Interrupt Program Status Register (IPSR).
239 */
240 typedef union
241 {
242 struct
243 {
244 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
245 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
246 } b; /*!< Structure used for bit access */
247 uint32_t w; /*!< Type used for word access */
248 } IPSR_Type;
249
250 /* IPSR Register Definitions */
251 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
252 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
253
254
255 /**
256 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
257 */
258 typedef union
259 {
260 struct
261 {
262 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
263 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
264 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
265 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
266 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
267 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
268 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
269 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
270 } b; /*!< Structure used for bit access */
271 uint32_t w; /*!< Type used for word access */
272 } xPSR_Type;
273
274 /* xPSR Register Definitions */
275 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
276 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
277
278 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
279 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
280
281 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
282 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
283
284 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
285 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
286
287 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
288 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
289
290 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
291 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
292
293
294 /**
295 \brief Union type to access the Control Registers (CONTROL).
296 */
297 typedef union
298 {
299 struct
300 {
301 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
302 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
303 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
304 } b; /*!< Structure used for bit access */
305 uint32_t w; /*!< Type used for word access */
306 } CONTROL_Type;
307
308 /* CONTROL Register Definitions */
309 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
310 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
311
312 /*@} end of group CMSIS_CORE */
313
314
315 /**
316 \ingroup CMSIS_core_register
317 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
318 \brief Type definitions for the NVIC Registers
319 @{
320 */
321
322 /**
323 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
324 */
325 typedef struct
326 {
327 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
328 uint32_t RESERVED0[31U];
329 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
330 uint32_t RSERVED1[31U];
331 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
332 uint32_t RESERVED2[31U];
333 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
334 uint32_t RESERVED3[31U];
335 uint32_t RESERVED4[64U];
336 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
337 } NVIC_Type;
338
339 /*@} end of group CMSIS_NVIC */
340
341
342 /**
343 \ingroup CMSIS_core_register
344 \defgroup CMSIS_SCB System Control Block (SCB)
345 \brief Type definitions for the System Control Block Registers
346 @{
347 */
348
349 /**
350 \brief Structure type to access the System Control Block (SCB).
351 */
352 typedef struct
353 {
354 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
355 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
356 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
357 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
358 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
359 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
360 uint32_t RESERVED0[1U];
361 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
362 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
363 uint32_t RESERVED1[154U];
364 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
365 } SCB_Type;
366
367 /* SCB CPUID Register Definitions */
368 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
369 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
370
371 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
372 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
373
374 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
375 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
376
377 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
378 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
379
380 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
381 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
382
383 /* SCB Interrupt Control State Register Definitions */
384 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
385 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
386
387 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
388 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
389
390 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
391 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
392
393 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
394 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
395
396 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
397 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
398
399 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
400 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
401
402 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
403 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
404
405 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
406 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
407
408 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
409 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
410
411 /* SCB Interrupt Control State Register Definitions */
412 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
413 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
414
415 /* SCB Application Interrupt and Reset Control Register Definitions */
416 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
417 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
418
419 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
420 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
421
422 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
423 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
424
425 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
426 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
427
428 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
429 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
430
431 /* SCB System Control Register Definitions */
432 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
433 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
434
435 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
436 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
437
438 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
439 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
440
441 /* SCB Configuration Control Register Definitions */
442 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
443 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
444
445 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
446 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
447
448 /* SCB System Handler Control and State Register Definitions */
449 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
450 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
451
452 /*@} end of group CMSIS_SCB */
453
454
455 /**
456 \ingroup CMSIS_core_register
457 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
458 \brief Type definitions for the System Control and ID Register not in the SCB
459 @{
460 */
461
462 /**
463 \brief Structure type to access the System Control and ID Register not in the SCB.
464 */
465 typedef struct
466 {
467 uint32_t RESERVED0[2U];
468 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
469 } SCnSCB_Type;
470
471 /* Auxiliary Control Register Definitions */
472 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
473 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
474
475 /*@} end of group CMSIS_SCnotSCB */
476
477
478 /**
479 \ingroup CMSIS_core_register
480 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
481 \brief Type definitions for the System Timer Registers.
482 @{
483 */
484
485 /**
486 \brief Structure type to access the System Timer (SysTick).
487 */
488 typedef struct
489 {
490 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
491 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
492 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
493 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
494 } SysTick_Type;
495
496 /* SysTick Control / Status Register Definitions */
497 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
498 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
499
500 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
501 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
502
503 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
504 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
505
506 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
507 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
508
509 /* SysTick Reload Register Definitions */
510 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
511 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
512
513 /* SysTick Current Register Definitions */
514 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
515 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
516
517 /* SysTick Calibration Register Definitions */
518 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
519 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
520
521 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
522 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
523
524 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
525 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
526
527 /*@} end of group CMSIS_SysTick */
528
529 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
530 /**
531 \ingroup CMSIS_core_register
532 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
533 \brief Type definitions for the Memory Protection Unit (MPU)
534 @{
535 */
536
537 /**
538 \brief Structure type to access the Memory Protection Unit (MPU).
539 */
540 typedef struct
541 {
542 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
543 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
544 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
545 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
546 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
547 } MPU_Type;
548
549 /* MPU Type Register Definitions */
550 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
551 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
552
553 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
554 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
555
556 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
557 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
558
559 /* MPU Control Register Definitions */
560 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
561 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
562
563 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
564 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
565
566 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
567 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
568
569 /* MPU Region Number Register Definitions */
570 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
571 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
572
573 /* MPU Region Base Address Register Definitions */
574 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
575 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
576
577 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
578 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
579
580 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
581 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
582
583 /* MPU Region Attribute and Size Register Definitions */
584 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
585 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
586
587 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
588 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
589
590 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
591 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
592
593 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
594 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
595
596 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
597 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
598
599 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
600 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
601
602 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
603 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
604
605 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
606 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
607
608 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
609 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
610
611 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
612 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
613
614 /*@} end of group CMSIS_MPU */
615 #endif
616
617
618 /**
619 \ingroup CMSIS_core_register
620 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
621 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
622 Therefore they are not covered by the SC000 header file.
623 @{
624 */
625 /*@} end of group CMSIS_CoreDebug */
626
627
628 /**
629 \ingroup CMSIS_core_register
630 \defgroup CMSIS_core_bitfield Core register bit field macros
631 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
632 @{
633 */
634
635 /**
636 \brief Mask and shift a bit field value for use in a register bit range.
637 \param[in] field Name of the register bit field.
638 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
639 \return Masked and shifted value.
640 */
641 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
642
643 /**
644 \brief Mask and shift a register value to extract a bit filed value.
645 \param[in] field Name of the register bit field.
646 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
647 \return Masked and shifted bit field value.
648 */
649 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
650
651 /*@} end of group CMSIS_core_bitfield */
652
653
654 /**
655 \ingroup CMSIS_core_register
656 \defgroup CMSIS_core_base Core Definitions
657 \brief Definitions for base addresses, unions, and structures.
658 @{
659 */
660
661 /* Memory mapping of Core Hardware */
662 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
663 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
664 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
665 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
666
667 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
668 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
669 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
670 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
671
672 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
673 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
674 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
675 #endif
676
677 /*@} */
678
679
680
681 /*******************************************************************************
682 * Hardware Abstraction Layer
683 Core Function Interface contains:
684 - Core NVIC Functions
685 - Core SysTick Functions
686 - Core Register Access Functions
687 ******************************************************************************/
688 /**
689 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
690 */
691
692
693
694 /* ########################## NVIC functions #################################### */
695 /**
696 \ingroup CMSIS_Core_FunctionInterface
697 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
698 \brief Functions that manage interrupts and exceptions via the NVIC.
699 @{
700 */
701
702 #ifdef CMSIS_NVIC_VIRTUAL
703 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
704 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
705 #endif
706 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
707 #else
708 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
709 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
710 #define NVIC_EnableIRQ __NVIC_EnableIRQ
711 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
712 #define NVIC_DisableIRQ __NVIC_DisableIRQ
713 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
714 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
715 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
716 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
717 #define NVIC_SetPriority __NVIC_SetPriority
718 #define NVIC_GetPriority __NVIC_GetPriority
719 #define NVIC_SystemReset __NVIC_SystemReset
720 #endif /* CMSIS_NVIC_VIRTUAL */
721
722 #ifdef CMSIS_VECTAB_VIRTUAL
723 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
724 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
725 #endif
726 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
727 #else
728 #define NVIC_SetVector __NVIC_SetVector
729 #define NVIC_GetVector __NVIC_GetVector
730 #endif /* (CMSIS_VECTAB_VIRTUAL) */
731
732 #define NVIC_USER_IRQ_OFFSET 16
733
734
735 /* The following EXC_RETURN values are saved the LR on exception entry */
736 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
737 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
738 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
739
740
741 /* Interrupt Priorities are WORD accessible only under Armv6-M */
742 /* The following MACROS handle generation of the register offset and byte masks */
743 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
744 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
745 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
746
747
748 /**
749 \brief Enable Interrupt
750 \details Enables a device specific interrupt in the NVIC interrupt controller.
751 \param [in] IRQn Device specific interrupt number.
752 \note IRQn must not be negative.
753 */
__NVIC_EnableIRQ(IRQn_Type IRQn)754 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
755 {
756 if ((int32_t)(IRQn) >= 0)
757 {
758 __COMPILER_BARRIER();
759 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
760 __COMPILER_BARRIER();
761 }
762 }
763
764
765 /**
766 \brief Get Interrupt Enable status
767 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
768 \param [in] IRQn Device specific interrupt number.
769 \return 0 Interrupt is not enabled.
770 \return 1 Interrupt is enabled.
771 \note IRQn must not be negative.
772 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)773 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
774 {
775 if ((int32_t)(IRQn) >= 0)
776 {
777 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
778 }
779 else
780 {
781 return(0U);
782 }
783 }
784
785
786 /**
787 \brief Disable Interrupt
788 \details Disables a device specific interrupt in the NVIC interrupt controller.
789 \param [in] IRQn Device specific interrupt number.
790 \note IRQn must not be negative.
791 */
__NVIC_DisableIRQ(IRQn_Type IRQn)792 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
793 {
794 if ((int32_t)(IRQn) >= 0)
795 {
796 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
797 __DSB();
798 __ISB();
799 }
800 }
801
802
803 /**
804 \brief Get Pending Interrupt
805 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
806 \param [in] IRQn Device specific interrupt number.
807 \return 0 Interrupt status is not pending.
808 \return 1 Interrupt status is pending.
809 \note IRQn must not be negative.
810 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)811 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
812 {
813 if ((int32_t)(IRQn) >= 0)
814 {
815 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
816 }
817 else
818 {
819 return(0U);
820 }
821 }
822
823
824 /**
825 \brief Set Pending Interrupt
826 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
827 \param [in] IRQn Device specific interrupt number.
828 \note IRQn must not be negative.
829 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)830 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
831 {
832 if ((int32_t)(IRQn) >= 0)
833 {
834 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
835 }
836 }
837
838
839 /**
840 \brief Clear Pending Interrupt
841 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
842 \param [in] IRQn Device specific interrupt number.
843 \note IRQn must not be negative.
844 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)845 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
846 {
847 if ((int32_t)(IRQn) >= 0)
848 {
849 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
850 }
851 }
852
853
854 /**
855 \brief Set Interrupt Priority
856 \details Sets the priority of a device specific interrupt or a processor exception.
857 The interrupt number can be positive to specify a device specific interrupt,
858 or negative to specify a processor exception.
859 \param [in] IRQn Interrupt number.
860 \param [in] priority Priority to set.
861 \note The priority cannot be set for every processor exception.
862 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)863 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
864 {
865 if ((int32_t)(IRQn) >= 0)
866 {
867 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
868 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
869 }
870 else
871 {
872 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
873 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
874 }
875 }
876
877
878 /**
879 \brief Get Interrupt Priority
880 \details Reads the priority of a device specific interrupt or a processor exception.
881 The interrupt number can be positive to specify a device specific interrupt,
882 or negative to specify a processor exception.
883 \param [in] IRQn Interrupt number.
884 \return Interrupt Priority.
885 Value is aligned automatically to the implemented priority bits of the microcontroller.
886 */
__NVIC_GetPriority(IRQn_Type IRQn)887 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
888 {
889
890 if ((int32_t)(IRQn) >= 0)
891 {
892 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
893 }
894 else
895 {
896 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
897 }
898 }
899
900
901 /**
902 \brief Set Interrupt Vector
903 \details Sets an interrupt vector in SRAM based interrupt vector table.
904 The interrupt number can be positive to specify a device specific interrupt,
905 or negative to specify a processor exception.
906 VTOR must been relocated to SRAM before.
907 \param [in] IRQn Interrupt number
908 \param [in] vector Address of interrupt handler function
909 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)910 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
911 {
912 uint32_t *vectors = (uint32_t *)SCB->VTOR;
913 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
914 /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */
915 }
916
917
918 /**
919 \brief Get Interrupt Vector
920 \details Reads an interrupt vector from interrupt vector table.
921 The interrupt number can be positive to specify a device specific interrupt,
922 or negative to specify a processor exception.
923 \param [in] IRQn Interrupt number.
924 \return Address of interrupt handler function
925 */
__NVIC_GetVector(IRQn_Type IRQn)926 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
927 {
928 uint32_t *vectors = (uint32_t *)SCB->VTOR;
929 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
930 }
931
932
933 /**
934 \brief System Reset
935 \details Initiates a system reset request to reset the MCU.
936 */
__NVIC_SystemReset(void)937 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
938 {
939 __DSB(); /* Ensure all outstanding memory accesses included
940 buffered write are completed before reset */
941 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
942 SCB_AIRCR_SYSRESETREQ_Msk);
943 __DSB(); /* Ensure completion of memory access */
944
945 for(;;) /* wait until reset */
946 {
947 __NOP();
948 }
949 }
950
951 /*@} end of CMSIS_Core_NVICFunctions */
952
953
954 /* ########################## FPU functions #################################### */
955 /**
956 \ingroup CMSIS_Core_FunctionInterface
957 \defgroup CMSIS_Core_FpuFunctions FPU Functions
958 \brief Function that provides FPU type.
959 @{
960 */
961
962 /**
963 \brief get FPU type
964 \details returns the FPU type
965 \returns
966 - \b 0: No FPU
967 - \b 1: Single precision FPU
968 - \b 2: Double + Single precision FPU
969 */
SCB_GetFPUType(void)970 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
971 {
972 return 0U; /* No FPU */
973 }
974
975
976 /*@} end of CMSIS_Core_FpuFunctions */
977
978
979
980 /* ################################## SysTick function ############################################ */
981 /**
982 \ingroup CMSIS_Core_FunctionInterface
983 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
984 \brief Functions that configure the System.
985 @{
986 */
987
988 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
989
990 /**
991 \brief System Tick Configuration
992 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
993 Counter is in free running mode to generate periodic interrupts.
994 \param [in] ticks Number of ticks between two interrupts.
995 \return 0 Function succeeded.
996 \return 1 Function failed.
997 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
998 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
999 must contain a vendor-specific implementation of this function.
1000 */
SysTick_Config(uint32_t ticks)1001 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1002 {
1003 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1004 {
1005 return (1UL); /* Reload value impossible */
1006 }
1007
1008 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1009 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1010 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1011 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1012 SysTick_CTRL_TICKINT_Msk |
1013 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1014 return (0UL); /* Function successful */
1015 }
1016
1017 #endif
1018
1019 /*@} end of CMSIS_Core_SysTickFunctions */
1020
1021
1022
1023
1024 #ifdef __cplusplus
1025 }
1026 #endif
1027
1028 #endif /* __CORE_SC000_H_DEPENDANT */
1029
1030 #endif /* __CMSIS_GENERIC */
1031