| /third_party/musl/porting/uniproton/kernel/include/sys/ |
| D | ttydefaults.h | 9 #define CTRL(x) ((x)&037) macro
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| /third_party/musl/porting/liteos_m/kernel/include/sys/ |
| D | ttydefaults.h | 9 #define CTRL(x) ((x)&037) macro
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| /third_party/musl/porting/liteos_m_iccarm/kernel/include/sys/ |
| D | ttydefaults.h | 9 #define CTRL(x) ((x)&037) macro
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| /third_party/musl/ndk_musl_include/sys/ |
| D | ttydefaults.h | 9 #define CTRL(x) ((x)&037) macro
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| /third_party/musl/include/sys/ |
| D | ttydefaults.h | 9 #define CTRL(x) ((x)&037) macro
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| /third_party/python/Modules/ |
| D | termios.c | 8 #define CTRL(c) ((c)&037) macro
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| /third_party/cmsis/CMSIS/Core/Include/ |
| D | core_sc000.h | 490 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
543 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
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| D | core_cm0plus.h | 474 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
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| D | core_armv8mbl.h | 562 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
614 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
829 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
935 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
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| D | core_cm23.h | 562 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
614 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
904 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1010 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
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| D | core_cm0.h | 450 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
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| D | core_sc300.h | 693 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
833 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1143 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
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| D | core_cm3.h | 708 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
848 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1158 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
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| D | core_cm4.h | 766 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
906 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1216 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
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| D | core_cm1.h | 476 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
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| D | core_armv8mml.h | 964 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1116 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1402 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1514 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
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| D | core_cm35p.h | 964 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1116 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1477 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1589 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
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| D | core_cm33.h | 964 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1116 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1477 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1589 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
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| D | core_cm7.h | 990 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1130 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1443 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
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| D | core_cm55.h | 1025 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1178 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1523 …__IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ member
2316 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
2431 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
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| D | core_armv81mml.h | 1025 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1178 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1489 …__IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ member
2281 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
2396 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
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| /third_party/curl/tests/server/ |
| D | sws.c | 1316 #define CTRL 0 macro
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