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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Daltera_tse.txt1 * Altera Triple-Speed Ethernet MAC driver (TSE)
4 - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
5 be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
8 - reg: Address and length of the register set for the device. It contains
9 the information of registers in the same order as described by reg-names
10 - reg-names: Should contain the reg names
18 - interrupts: Should contain the TSE interrupts and it's mode.
19 - interrupt-names: Should contain the interrupt names
22 - rx-fifo-depth: MAC receive FIFO buffer depth in bytes
23 - tx-fifo-depth: MAC transmit FIFO buffer depth in bytes
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Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Ardelean <alexandru.ardelean@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
33 adi,fifo-depth-bits:
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/
Dmeson-sm1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-bindings/power/meson-sm1-power.h>
10 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
11 #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
16 tdmif_a: audio-controller-0 {
17 compatible = "amlogic,axg-tdm-iface";
18 #sound-dai-cells = <0>;
19 sound-name-prefix = "TDM_A";
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dspi-sifive.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: "spi-controller.yaml#"
20 - const: sifive,fu540-c000-spi
21 - const: sifive,spi0
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/kernel/linux/linux-5.10/drivers/net/ethernet/sgi/
Dmeth.h4 #define TX_RING_ENTRIES 64 /* 64-512?*/
11 #define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
32 * It consists of header, 0-3 concatination
43 u64 data_len:16; /*Length of valid data in bytes-1*/
48 u64 len:16; /*length of buffer data - 1*/
91 u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */
93 char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */
99 /* Bits in METH_MAC */
110 /* Bits 5 and 6 are used to determine the Destination address filter mode */
122 … /* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */
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/kernel/linux/linux-5.10/include/linux/
Dqcom-geni-se.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
42 * struct geni_se - GENI Serial Engine
274 * geni_se_read_proto() - Read the protocol configured for a serial engine
283 val = readl_relaxed(se->base + GENI_FW_REVISION_RO); in geni_se_read_proto()
289 * geni_se_setup_m_cmd() - Setup the primary sequencer
302 writel(m_cmd, se->base + SE_GENI_M_CMD0); in geni_se_setup_m_cmd()
306 * geni_se_setup_s_cmd() - Setup the secondary sequencer
318 s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0); in geni_se_setup_s_cmd()
322 writel(s_cmd, se->base + SE_GENI_S_CMD0); in geni_se_setup_s_cmd()
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/kernel/linux/linux-5.10/drivers/net/phy/
Ddp83867.c1 // SPDX-License-Identifier: GPL-2.0
18 #include <dt-bindings/net/ti-dp83867.h>
59 /* MICR Interrupt bits */
73 /* RGMIICTL bits */
77 /* SGMIICTL bits */
80 /* RXFCFG bits*/
87 /* STRAP_STS1 bits */
90 /* STRAP_STS2 bits */
98 /* PHY CTRL bits */
107 /* RGMIIDCTL bits */
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/kernel/linux/linux-5.10/drivers/spi/
Dspi-sifive.c1 // SPDX-License-Identifier: GPL-2.0
34 #define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
35 #define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
36 #define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
37 #define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
43 /* sckdiv bits */
46 /* sckmode bits */
52 /* csmode bits */
57 /* delay0 bits */
63 /* delay1 bits */
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Dspi-dw.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/bits.h>
11 #include <linux/spi/spi-mem.h>
85 /* Bit fields in SR, 7 bits */
86 #define SR_MASK 0x7f /* cover 7 bits */
95 /* Bit fields in ISR, IMR, RISR, 7 bits */
150 u32 fifo_len; /* depth of the FIFO buffer */
151 u32 max_mem_freq; /* max mem-ops bus freq */
196 return __raw_readl(dws->regs + offset); in dw_readl()
201 __raw_writel(val, dws->regs + offset); in dw_writel()
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/kernel/linux/linux-5.10/include/media/drv-intf/
Dexynos-fimc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010 - 2013 Samsung Electronics Co., Ltd.
12 #include <media/media-entity.h>
13 #include <media/v4l2-dev.h>
14 #include <media/v4l2-mediabus.h>
37 /* Camera MIPI-CSI2 serial bus */
39 /* FIFO link from LCD controller (WriteBack A) */
41 /* FIFO link from LCD controller (WriteBack B) */
43 /* FIFO link from FIMC-IS */
62 * struct fimc_source_info - video source description required for the host
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/kernel/linux/linux-5.10/arch/nios2/boot/dts/
D10m50_devboard.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
10 compatible = "altr,niosii-max10";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "altr,nios2-1.1";
22 interrupt-controller;
23 #interrupt-cells = <1>;
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D3c120_devboard.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "altr,nios2-1.0";
24 interrupt-controller;
25 #interrupt-cells = <1>;
26 clock-frequency = <125000000>;
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/kernel/linux/linux-5.10/drivers/staging/axis-fifo/
Daxis-fifo.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx AXIS FIFO: interface to the Xilinx AXI-Stream FIFO IP core
12 /* ----------------------------
14 * ----------------------------
38 /* ----------------------------
40 * ----------------------------
48 /* ----------------------------
50 * ----------------------------
69 /* ----------------------------
71 * ----------------------------
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/kernel/linux/linux-5.10/sound/soc/fsl/
Dfsl_dma.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
16 #include <linux/dma-mapping.h>
40 * that is 8, 16, or 32 bits.
72 /** fsl_dma_private: p-substream DMA data
74 * Each substream has a 1-to-1 association with a DMA channel.
76 * The link[] array is first because it needs to be aligned on a 32-byte
120 * Since each link descriptor has a 32-bit byte count field, we set
121 * period_bytes_max to the largest 32-bit number. We also have no maximum
137 .period_bytes_max = (u32) -1,
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Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
12 // sane processor vendors have a FIFO per AC97 slot, the i.MX has only
13 // one FIFO which combines all valid receive slots. We cannot even select
16 // we receive in our (PCM-) data stream. The only chance we have is to
23 // provides us status bits when the read register is updated with *another*
25 // contains the same value) these status bits are not set. We work
26 // around this by not polling these bits but only wait a fixed delay.
52 #include "imx-pcm.h"
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/zte/
Dzx296718.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/input/input.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/clock/zx296718-clock.h>
51 #address-cells = <1>;
52 #size-cells = <1>;
53 interrupt-parent = <&gic>;
67 #address-cells = <2>;
68 #size-cells = <0>;
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/
Dfsl-imx-sdma.txt4 - compatible : Should be one of
5 "fsl,imx25-sdma"
6 "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
7 "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
8 "fsl,imx51-sdma"
9 "fsl,imx53-sdma"
10 "fsl,imx6q-sdma"
11 "fsl,imx7d-sdma"
12 "fsl,imx8mq-sdma"
13 "fsl,imx8mm-sdma"
[all …]
/kernel/linux/linux-5.10/drivers/mmc/host/
Ddw_mmc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
57 * struct dw_mci - MMC controller state shared between all slots
61 * @fifo_reg: Pointer to MMIO registers for data FIFO
75 * @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
78 * @dma_ops: Pointer to platform-specific DMA callbacks.
82 * @dms: structure of slave-dma private data.
109 * @fifo_depth: depth of FIFO.
110 * @data_addr_override: override fifo reg offset with this value.
111 * @wm_aligned: force fifo watermark equal with data length in PIO mode.
113 * @data_shift: log2 of FIFO item size.
[all …]
/kernel/linux/linux-5.10/drivers/i2c/busses/
Di2c-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
37 /* 1 = Auto init FIFO to zeroes */
58 * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0]
59 * bits. A write access to this register always initiates a transfer if the I2C
116 /* FIFO depth at which the DATA interrupt occurs */
117 #define CDNS_I2C_DATA_INTR_DEPTH (CDNS_I2C_FIFO_DEPTH - 2)
119 /* Transfer size in multiples of data interrupt depth */
120 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_MAX_TRANSFER_SIZE - 3)
122 #define DRIVER_NAME "cdns-i2c"
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/kernel/linux/linux-5.10/drivers/tty/serial/
Dsifive.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2018-2019 SiFive
18 * - drivers/tty/serial/pxa.c
19 * - drivers/tty/serial/amba-pl011.c
20 * - drivers/tty/serial/uartlite.c
21 * - drivers/tty/serial/omap-serial.c
22 * - drivers/pwm/pwm-sifive.c
25 * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
26 * SiFive FE310-G000 v2p3
27 * - The tree/master/src/main/scala/devices/uart directory of
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/kernel/linux/linux-5.10/drivers/video/fbdev/aty/
Dmach64_accel.c1 // SPDX-License-Identifier: GPL-2.0
49 /* ensure engine is not locked up by clearing any FIFO or */ in aty_reset_engine()
54 par->fifo_space = 0; in aty_reset_engine()
73 pitch_value = info->fix.line_length / (info->var.bits_per_pixel / 8); in aty_init_engine()
74 vxres = info->var.xres_virtual; in aty_init_engine()
76 if (info->var.bits_per_pixel == 24) { in aty_init_engine()
77 /* In 24 bpp, the engine is in 8 bpp - this requires that all */ in aty_init_engine()
89 /* Ensure that vga page pointers are set to zero - the upper */ in aty_init_engine()
95 /* ---- Setup standard engine context ---- */ in aty_init_engine()
97 /* All GUI registers here are FIFOed - therefore, wait for */ in aty_init_engine()
[all …]
/kernel/linux/linux-5.10/sound/arm/
Daaci.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
28 #define DRIVER_NAME "aaci-pl041"
39 u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num); in aaci_ac97_select_codec()
44 v = readl(aaci->base + AACI_SLFR); in aaci_ac97_select_codec()
46 readl(aaci->base + AACI_SL2RX); in aaci_ac97_select_codec()
48 readl(aaci->base + AACI_SL1RX); in aaci_ac97_select_codec()
50 if (maincr != readl(aaci->base + AACI_MAINCR)) { in aaci_ac97_select_codec()
51 writel(maincr, aaci->base + AACI_MAINCR); in aaci_ac97_select_codec()
52 readl(aaci->base + AACI_MAINCR); in aaci_ac97_select_codec()
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/xilinx/
Dzynqmp-zcu104-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2019, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
18 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
32 stdout-path = "serial0:115200n8";
51 phy-handle = <&phy0>;
52 phy-mode = "rgmii-id";
53 phy0: ethernet-phy@c {
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dexynos3250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
50 #address-cells = <1>;
51 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi5_core.c1 // SPDX-License-Identifier: GPL-2.0-only
27 /* only 24 bit color depth used for now */
41 void __iomem *base = core->base; in hdmi_core_ddc_init()
120 void __iomem *base = core->base; in hdmi_core_ddc_uninit()
130 void __iomem *base = core->base; in hdmi_core_ddc_edid()
165 return -EIO; in hdmi_core_ddc_edid()
177 return -EIO; in hdmi_core_ddc_edid()
191 int max_ext_blocks = (len / 128) - 1; in hdmi5_read_edid()
194 return -EINVAL; in hdmi5_read_edid()
222 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\ in hdmi5_core_dump()
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