/kernel/linux/linux-5.10/arch/parisc/include/asm/ |
D | asmregs.h | 11 rp: .reg %r2 12 arg3: .reg %r23 13 arg2: .reg %r24 14 arg1: .reg %r25 15 arg0: .reg %r26 16 dp: .reg %r27 17 ret0: .reg %r28 18 ret1: .reg %r29 19 sl: .reg %r29 20 sp: .reg %r30 [all …]
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/kernel/linux/linux-5.10/arch/mips/include/asm/ |
D | asm-eva.h | 19 #define kernel_ll(reg, addr) "ll " reg ", " addr "\n" argument 20 #define kernel_sc(reg, addr) "sc " reg ", " addr "\n" argument 21 #define kernel_lw(reg, addr) "lw " reg ", " addr "\n" argument 22 #define kernel_lwl(reg, addr) "lwl " reg ", " addr "\n" argument 23 #define kernel_lwr(reg, addr) "lwr " reg ", " addr "\n" argument 24 #define kernel_lh(reg, addr) "lh " reg ", " addr "\n" argument 25 #define kernel_lb(reg, addr) "lb " reg ", " addr "\n" argument 26 #define kernel_lbu(reg, addr) "lbu " reg ", " addr "\n" argument 27 #define kernel_sw(reg, addr) "sw " reg ", " addr "\n" argument 28 #define kernel_swl(reg, addr) "swl " reg ", " addr "\n" argument [all …]
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/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/analogix/ |
D | analogix_dp_reg.c | 28 u32 reg; in analogix_dp_enable_video_mute() local 31 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute() 32 reg |= HDCP_VIDEO_MUTE; in analogix_dp_enable_video_mute() 33 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute() 35 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute() 36 reg &= ~HDCP_VIDEO_MUTE; in analogix_dp_enable_video_mute() 37 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute() 43 u32 reg; in analogix_dp_stop_video() local 45 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video() 46 reg &= ~VIDEO_EN; in analogix_dp_stop_video() [all …]
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/kernel/linux/linux-5.10/tools/testing/selftests/powerpc/include/ |
D | vmx_asm.h | 9 #define PUSH_VMX(pos,reg) \ argument 10 li reg,pos; \ 11 stvx v20,reg,%r1; \ 12 addi reg,reg,16; \ 13 stvx v21,reg,%r1; \ 14 addi reg,reg,16; \ 15 stvx v22,reg,%r1; \ 16 addi reg,reg,16; \ 17 stvx v23,reg,%r1; \ 18 addi reg,reg,16; \ [all …]
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/ |
D | reg_helper.h | 36 * REG ==> macro to location of register offset 37 * eg. aud110->regs->reg 40 dm_read_reg(CTX, REG(reg_name)) 43 dm_write_reg(CTX, REG(reg_name), value) 56 REG(reg_name), \ 67 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ argument 68 REG_SET_N(reg, 2, init_value, \ 69 FN(reg, f1), v1,\ 70 FN(reg, f2), v2) 72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ argument [all …]
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/kernel/linux/linux-5.10/drivers/media/platform/s5p-jpeg/ |
D | jpeg-hw-s5p.c | 19 unsigned long reg; in s5p_jpeg_reset() local 22 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset() 24 while (reg != 0) { in s5p_jpeg_reset() 26 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset() 37 unsigned long reg, m; in s5p_jpeg_input_raw_mode() local 45 reg = readl(regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode() 46 reg &= ~S5P_MOD_SEL_MASK; in s5p_jpeg_input_raw_mode() 47 reg |= m; in s5p_jpeg_input_raw_mode() 48 writel(reg, regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode() 53 unsigned long reg, m; in s5p_jpeg_proc_mode() local [all …]
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D | jpeg-hw-exynos4.c | 18 unsigned int reg; in exynos4_jpeg_sw_reset() local 20 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset() 21 writel(reg & ~(EXYNOS4_DEC_MODE | EXYNOS4_ENC_MODE), in exynos4_jpeg_sw_reset() 24 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset() 25 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset() 29 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset() 34 unsigned int reg; in exynos4_jpeg_set_enc_dec_mode() local 36 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode() 39 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode() 43 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode() [all …]
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D | jpeg-hw-exynos3250.c | 20 u32 reg = 1; in exynos3250_jpeg_reset() local 25 while (reg != 0 && --count > 0) { in exynos3250_jpeg_reset() 28 reg = readl(regs + EXYNOS3250_SW_RESET); in exynos3250_jpeg_reset() 31 reg = 0; in exynos3250_jpeg_reset() 34 while (reg != 1 && --count > 0) { in exynos3250_jpeg_reset() 38 reg = readl(regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset() 62 u32 reg; in exynos3250_jpeg_clk_set() local 64 reg = readl(base + EXYNOS3250_JPGCMOD) & ~EXYNOS3250_HALF_EN_MASK; in exynos3250_jpeg_clk_set() 66 writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_clk_set() 71 u32 reg; in exynos3250_jpeg_input_raw_fmt() local [all …]
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/kernel/linux/linux-5.10/drivers/media/cec/platform/s5p/ |
D | exynos_hdmi_cecctrl.c | 26 unsigned int reg; in s5p_cec_set_divider() local 30 if (regmap_read(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, ®)) { in s5p_cec_set_divider() 35 reg = (reg & ~(0x3FF << 16)) | (div_ratio << 16); in s5p_cec_set_divider() 37 if (regmap_write(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, reg)) { in s5p_cec_set_divider() 44 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_3); in s5p_cec_set_divider() 45 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_2); in s5p_cec_set_divider() 46 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_1); in s5p_cec_set_divider() 47 writeb(div_val, cec->reg + S5P_CEC_DIVISOR_0); in s5p_cec_set_divider() 52 u8 reg; in s5p_cec_enable_rx() local 54 reg = readb(cec->reg + S5P_CEC_RX_CTRL); in s5p_cec_enable_rx() [all …]
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/kernel/linux/linux-5.10/drivers/scsi/qla2xxx/ |
D | qla_dbg.c | 108 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla27xx_dump_mpi_ram() local 121 wrt_reg_word(®->mailbox0, MBC_LOAD_DUMP_MPI_RAM); in qla27xx_dump_mpi_ram() 122 wrt_reg_word(®->mailbox1, LSW(addr)); in qla27xx_dump_mpi_ram() 123 wrt_reg_word(®->mailbox8, MSW(addr)); in qla27xx_dump_mpi_ram() 125 wrt_reg_word(®->mailbox2, MSW(LSD(dump_dma))); in qla27xx_dump_mpi_ram() 126 wrt_reg_word(®->mailbox3, LSW(LSD(dump_dma))); in qla27xx_dump_mpi_ram() 127 wrt_reg_word(®->mailbox6, MSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram() 128 wrt_reg_word(®->mailbox7, LSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram() 130 wrt_reg_word(®->mailbox4, MSW(dwords)); in qla27xx_dump_mpi_ram() 131 wrt_reg_word(®->mailbox5, LSW(dwords)); in qla27xx_dump_mpi_ram() [all …]
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/kernel/linux/linux-5.10/arch/riscv/include/asm/ |
D | gdb_xml.h | 26 "<reg name=\""DBG_REG_ZERO"\" bitsize=\"64\" type=\"int\" regnum=\"0\"/>" 27 "<reg name=\""DBG_REG_RA"\" bitsize=\"64\" type=\"code_ptr\"/>" 28 "<reg name=\""DBG_REG_SP"\" bitsize=\"64\" type=\"data_ptr\"/>" 29 "<reg name=\""DBG_REG_GP"\" bitsize=\"64\" type=\"data_ptr\"/>" 30 "<reg name=\""DBG_REG_TP"\" bitsize=\"64\" type=\"data_ptr\"/>" 31 "<reg name=\""DBG_REG_T0"\" bitsize=\"64\" type=\"int\"/>" 32 "<reg name=\""DBG_REG_T1"\" bitsize=\"64\" type=\"int\"/>" 33 "<reg name=\""DBG_REG_T2"\" bitsize=\"64\" type=\"int\"/>" 34 "<reg name=\""DBG_REG_FP"\" bitsize=\"64\" type=\"data_ptr\"/>" 35 "<reg name=\""DBG_REG_S1"\" bitsize=\"64\" type=\"int\"/>" [all …]
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/kernel/linux/linux-5.10/drivers/video/fbdev/riva/ |
D | nvreg.h | 44 #define DEVICE_ACCESS(device,reg) \ argument 45 nvCONTROL[(NV_##device##_##reg)/4] 47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument 48 #define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg) argument 49 #define DEVICE_PRINT(device,reg) \ argument 50 ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg)) 56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument 57 #define PDAC_Read(reg) DEVICE_READ(PDAC,reg) argument 58 #define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg) argument 63 #define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value) argument [all …]
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/kernel/linux/linux-5.10/tools/perf/arch/csky/util/ |
D | unwind-libdw.c | 15 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro 22 dwarf_regs[0] = REG(A0); in libdw__arch_set_initial_registers() 23 dwarf_regs[1] = REG(A1); in libdw__arch_set_initial_registers() 24 dwarf_regs[2] = REG(A2); in libdw__arch_set_initial_registers() 25 dwarf_regs[3] = REG(A3); in libdw__arch_set_initial_registers() 26 dwarf_regs[4] = REG(REGS0); in libdw__arch_set_initial_registers() 27 dwarf_regs[5] = REG(REGS1); in libdw__arch_set_initial_registers() 28 dwarf_regs[6] = REG(REGS2); in libdw__arch_set_initial_registers() 29 dwarf_regs[7] = REG(REGS3); in libdw__arch_set_initial_registers() 30 dwarf_regs[8] = REG(REGS4); in libdw__arch_set_initial_registers() [all …]
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/kernel/linux/linux-5.10/drivers/net/ethernet/microchip/ |
D | encx24j600-regmap.c | 60 static int regmap_encx24j600_sfr_read(void *context, u8 reg, u8 *val, in regmap_encx24j600_sfr_read() argument 64 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_read() 65 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); in regmap_encx24j600_sfr_read() 71 if (reg < 0x80) { in regmap_encx24j600_sfr_read() 81 switch (reg) { in regmap_encx24j600_sfr_read() 104 tx_buf[i++] = reg; in regmap_encx24j600_sfr_read() 112 u8 reg, u8 *val, size_t len, in regmap_encx24j600_sfr_update() argument 115 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_update() 116 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); in regmap_encx24j600_sfr_update() 120 { .tx_buf = ®, .len = sizeof(reg), }, in regmap_encx24j600_sfr_update() [all …]
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/kernel/linux/linux-5.10/arch/ia64/include/asm/native/ |
D | inst.h | 11 #define MOV_FROM_IFA(reg) \ argument 12 mov reg = cr.ifa 14 #define MOV_FROM_ITIR(reg) \ argument 15 mov reg = cr.itir 17 #define MOV_FROM_ISR(reg) \ argument 18 mov reg = cr.isr 20 #define MOV_FROM_IHA(reg) \ argument 21 mov reg = cr.iha 23 #define MOV_FROM_IPSR(pred, reg) \ argument 24 (pred) mov reg = cr.ipsr [all …]
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/kernel/linux/linux-5.10/drivers/clk/ |
D | clk-highbank.c | 39 void __iomem *reg; member 47 u32 reg; in clk_pll_prepare() local 49 reg = readl(hbclk->reg); in clk_pll_prepare() 50 reg &= ~HB_PLL_RESET; in clk_pll_prepare() 51 writel(reg, hbclk->reg); in clk_pll_prepare() 53 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) in clk_pll_prepare() 55 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) in clk_pll_prepare() 64 u32 reg; in clk_pll_unprepare() local 66 reg = readl(hbclk->reg); in clk_pll_unprepare() 67 reg |= HB_PLL_RESET; in clk_pll_unprepare() [all …]
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/kernel/linux/linux-5.10/drivers/net/wireless/ralink/rt2x00/ |
D | rt2400pci.c | 48 u32 reg; in rt2400pci_bbp_write() local 56 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2400pci_bbp_write() 57 reg = 0; in rt2400pci_bbp_write() 58 rt2x00_set_field32(®, BBPCSR_VALUE, value); in rt2400pci_bbp_write() 59 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2400pci_bbp_write() 60 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2400pci_bbp_write() 61 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); in rt2400pci_bbp_write() 63 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2400pci_bbp_write() 72 u32 reg; in rt2400pci_bbp_read() local 82 * doesn't become available in time, reg will be 0xffffffff in rt2400pci_bbp_read() [all …]
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/kernel/linux/linux-5.10/drivers/net/ethernet/intel/ixgbe/ |
D | ixgbe_dcb_82598.c | 23 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82598() local 28 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; in ixgbe_dcb_config_rx_arbiter_82598() 29 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); in ixgbe_dcb_config_rx_arbiter_82598() 31 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); in ixgbe_dcb_config_rx_arbiter_82598() 33 reg &= ~IXGBE_RMCS_ARBDIS; in ixgbe_dcb_config_rx_arbiter_82598() 35 reg |= IXGBE_RMCS_RRM; in ixgbe_dcb_config_rx_arbiter_82598() 37 reg |= IXGBE_RMCS_DFP; in ixgbe_dcb_config_rx_arbiter_82598() 39 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); in ixgbe_dcb_config_rx_arbiter_82598() 46 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); in ixgbe_dcb_config_rx_arbiter_82598() 49 reg |= IXGBE_RT2CR_LSP; in ixgbe_dcb_config_rx_arbiter_82598() [all …]
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/kernel/linux/linux-5.10/drivers/media/pci/cx23885/ |
D | cx23885-ioctl.c | 32 struct v4l2_dbg_register *reg) in cx23417_g_register() argument 39 if ((reg->reg & 0x3) != 0 || reg->reg >= 0x10000) in cx23417_g_register() 42 if (mc417_register_read(dev, (u16) reg->reg, &value)) in cx23417_g_register() 45 reg->size = 4; in cx23417_g_register() 46 reg->val = value; in cx23417_g_register() 51 struct v4l2_dbg_register *reg) in cx23885_g_register() argument 55 if (reg->match.addr > 1) in cx23885_g_register() 57 if (reg->match.addr) in cx23885_g_register() 58 return cx23417_g_register(dev, reg); in cx23885_g_register() 60 if ((reg->reg & 0x3) != 0 || reg->reg >= pci_resource_len(dev->pci, 0)) in cx23885_g_register() [all …]
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/kernel/linux/linux-5.10/drivers/clk/imx/ |
D | clk.h | 70 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ argument 72 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ 78 #define imx_clk_pfd(name, parent_name, reg, idx) \ argument 79 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx)) 81 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ argument 82 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask)) 90 #define imx_clk_divider(name, parent, reg, shift, width) \ argument 91 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width)) 93 #define imx_clk_divider2(name, parent, reg, shift, width) \ argument 94 to_clk(imx_clk_hw_divider2(name, parent, reg, shift, width)) [all …]
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/kernel/linux/linux-5.10/drivers/net/ethernet/mscc/ |
D | ocelot_vsc7514.c | 24 REG(ANA_ADVLEARN, 0x009000), 25 REG(ANA_VLANMASK, 0x009004), 26 REG(ANA_PORT_B_DOMAIN, 0x009008), 27 REG(ANA_ANAGEFIL, 0x00900c), 28 REG(ANA_ANEVENTS, 0x009010), 29 REG(ANA_STORMLIMIT_BURST, 0x009014), 30 REG(ANA_STORMLIMIT_CFG, 0x009018), 31 REG(ANA_ISOLATED_PORTS, 0x009028), 32 REG(ANA_COMMUNITY_PORTS, 0x00902c), 33 REG(ANA_AUTOAGE, 0x009030), [all …]
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/kernel/linux/linux-5.10/drivers/memory/tegra/ |
D | tegra210.c | 20 .reg = 0x228, 24 .reg = 0x2e8, 34 .reg = 0x228, 38 .reg = 0x2f4, 48 .reg = 0x228, 52 .reg = 0x2e8, 62 .reg = 0x228, 66 .reg = 0x2f4, 76 .reg = 0x228, 80 .reg = 0x2ec, [all …]
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D | tegra30.c | 44 .reg = 0x228, 48 .reg = 0x2e8, 58 .reg = 0x228, 62 .reg = 0x2f4, 72 .reg = 0x228, 76 .reg = 0x2e8, 86 .reg = 0x228, 90 .reg = 0x2f4, 100 .reg = 0x228, 104 .reg = 0x2ec, [all …]
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/kernel/linux/linux-5.10/tools/perf/arch/s390/util/ |
D | unwind-libdw.c | 15 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro 24 dwarf_regs[0] = REG(R0); in libdw__arch_set_initial_registers() 25 dwarf_regs[1] = REG(R1); in libdw__arch_set_initial_registers() 26 dwarf_regs[2] = REG(R2); in libdw__arch_set_initial_registers() 27 dwarf_regs[3] = REG(R3); in libdw__arch_set_initial_registers() 28 dwarf_regs[4] = REG(R4); in libdw__arch_set_initial_registers() 29 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers() 30 dwarf_regs[6] = REG(R6); in libdw__arch_set_initial_registers() 31 dwarf_regs[7] = REG(R7); in libdw__arch_set_initial_registers() 32 dwarf_regs[8] = REG(R8); in libdw__arch_set_initial_registers() [all …]
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
D | smu_helper.h | 124 #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT argument 125 #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK argument 127 #define PHM_SET_FIELD(origval, reg, field, fieldval) \ argument 128 (((origval) & ~PHM_FIELD_MASK(reg, field)) | \ 129 (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field)))) 131 #define PHM_GET_FIELD(value, reg, field) \ argument 132 (((value) & PHM_FIELD_MASK(reg, field)) >> \ 133 PHM_FIELD_SHIFT(reg, field)) 138 #define PHM_READ_FIELD(device, reg, field) \ argument 139 PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field) [all …]
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