/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
D | adi,adin.yaml | 1 # SPDX-License-Identifier: GPL-2.0+ 3 --- 4 $id: http://devicetree.org/schemas/net/adi,adin.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Alexandru Ardelean <alexandru.ardelean@analog.com> 16 - $ref: ethernet-phy.yaml# 19 adi,rx-internal-delay-ps: 21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with 22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds. 26 adi,tx-internal-delay-ps: [all …]
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D | amlogic,meson-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: "http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#" 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#" 11 - Neil Armstrong <narmstrong@baylibre.com> 12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com> 20 - amlogic,meson6-dwmac 21 - amlogic,meson8b-dwmac 22 - amlogic,meson8m2-dwmac 23 - amlogic,meson-gxbb-dwmac [all …]
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D | ethernet-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - David S. Miller <davem@davemloft.net> 16 local-mac-address: 19 $ref: /schemas/types.yaml#definitions/uint8-array 21 - minItems: 6 24 mac-address: 29 local-mac-address property. [all …]
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D | qca,ar803x.yaml | 1 # SPDX-License-Identifier: GPL-2.0+ 3 --- 4 $id: http://devicetree.org/schemas/net/qca,ar803x.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Andrew Lunn <andrew@lunn.ch> 11 - Florian Fainelli <f.fainelli@gmail.com> 12 - Heiner Kallweit <hkallweit1@gmail.com> 18 - $ref: ethernet-phy.yaml# 21 qca,clk-out-frequency: 26 qca,clk-out-strength: [all …]
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D | xilinx_gmii2rgmii.txt | 2 -------------------------------------------------------- 5 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant 18 - compatible : Should be "xlnx,gmii-to-rgmii-1.0" 19 - reg : The ID number for the phy, usually a small integer 20 - phy-handle : Should point to the external phy device. 25 #address-cells = <1>; 26 #size-cells = <0>; 27 phy: ethernet-phy@0 { 31 compatible = "xlnx,gmii-to-rgmii-1.0"; 33 phy-handle = <&phy>;
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D | ti,dp83867.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) 4 --- 5 $id: "http://devicetree.org/schemas/net/ti,dp83867.yaml#" 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#" 11 - $ref: "ethernet-controller.yaml#" 14 - Dan Murphy <dmurphy@ti.com> 18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX 19 and 1000BASE-T Ethernet protocols. 25 Media Independent Interface (GMII) or Reduced GMII (RGMII). 34 ti,min-output-impedance: [all …]
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D | apm-xgene-enet.txt | 1 APM X-Gene SoC Ethernet nodes 3 Ethernet nodes are defined to describe on-chip ethernet interfaces in 4 APM X-Gene SoC. 7 - compatible: Should state binding information from the following list, 8 - "apm,xgene-enet": RGMII based 1G interface 9 - "apm,xgene1-sgenet": SGMII based 1G interface 10 - "apm,xgene1-xgenet": XFI based 10G interface 11 - reg: Address and length of the register set for the device. It contains the 12 information of registers in the same order as described by reg-names 13 - reg-names: Should contain the register set names [all …]
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D | apm-xgene-mdio.txt | 1 APM X-Gene SoC MDIO node 3 MDIO node is defined to describe on-chip MDIO controller. 6 - compatible: Must be "apm,xgene-mdio-rgmii" or "apm,xgene-mdio-xfi" 7 - #address-cells: Must be <1>. 8 - #size-cells: Must be <0>. 9 - reg: Address and length of the register set 10 - clocks: Reference to the clock entry 13 - compatible: PHY identifier. Please refer ./phy.txt for the format. 14 - reg: The ID number for the phy. 19 compatible = "apm,xgene-mdio-rgmii"; [all …]
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/dsa/ |
D | sja1105.txt | 6 - compatible: 8 - "nxp,sja1105e" 9 - "nxp,sja1105t" 10 - "nxp,sja1105p" 11 - "nxp,sja1105q" 12 - "nxp,sja1105r" 13 - "nxp,sja1105s" 15 Although the device ID could be detected at runtime, explicit bindings 18 and the non-SGMII devices, while pin-compatible, are not equal in terms 19 of support for RGMII internal delays (supported on P/Q/R/S, but not on [all …]
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/kernel/linux/linux-5.10/arch/arm/boot/dts/ |
D | ls1021a-tsn.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright 2016-2018 NXP Semiconductors 6 /dts-v1/; 10 model = "NXP LS1021A-TSN Board"; 12 sys_mclk: clock-mclk { 13 compatible = "fixed-clock"; 14 #clock-cells = <0>; 15 clock-frequency = <24576000>; 18 reg_vdda_codec: regulator-3V3 { 19 compatible = "regulator-fixed"; [all …]
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D | ls1021a-moxa-uc-8410a.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2017 Moxa Inc. - https://www.moxa.com/ 10 /dts-v1/; 12 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/input/input.h> 17 model = "Moxa UC-8410A"; 18 compatible = "fsl,ls1021a-moxa-uc-8410a", "fsl,ls1021a"; 26 sys_mclk: clock-mclk { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; [all …]
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D | armada-388-rd.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 * (RD-88F6820-AP) 8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 12 /dts-v1/; 13 #include "armada-388.dtsi" 17 compatible = "marvell,a385-rd", "marvell,armada388", 21 stdout-path = "serial0:115200n8"; 35 internal-regs { 38 clock-frequency = <100000>; [all …]
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D | kirkwood-guruplug-server-plus.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 5 #include "kirkwood-6281.dtsi" 9 …compatible = "globalscale,guruplug-server-plus", "globalscale,guruplug", "marvell,kirkwood-88f6281… 18 stdout-path = &uart0; 22 pinctrl: pin-controller@10000 { 23 pmx_led_health_r: pmx-led-health-r { 27 pmx_led_health_g: pmx-led-health-g { 31 pmx_led_wmode_r: pmx-led-wmode-r { 35 pmx_led_wmode_g: pmx-led-wmode-g { [all …]
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/xilinx/ |
D | zynqmp-zc1751-xm018-dc4.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4 5 * (C) Copyright 2015 - 2019, Xilinx, Inc. 10 /dts-v1/; 13 #include "zynqmp-clk-ccf.dtsi" 16 model = "ZynqMP zc1751-xm018-dc4"; 17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 33 stdout-path = "serial0:115200n8"; 116 phy-mode = "rgmii-id"; 117 phy-handle = <ðernet_phy0>; [all …]
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/kernel/linux/linux-5.10/Documentation/ABI/testing/ |
D | sysfs-class-net-phydev | 24 This attribute contains the 32-bit PHY Identifier as reported 26 This ID is used to match the device with the appropriate 41 <empty> (not available), mii, gmii, sgmii, tbi, rev-mii, 42 rmii, rgmii, rgmii-id, rgmii-rxid, rgmii-txid, rtbi, smii 43 xgmii, moca, qsgmii, trgmii, 1000base-x, 2500base-x, rxaui, 44 xaui, 10gbase-kr, unknown
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/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/ |
D | mvme7100.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A. 10 /include/ "mpc8641si-pre.dtsi" 37 phy-handle = <&phy0>; 38 phy-connection-type = "rgmii-id"; 42 phy0: ethernet-phy@1 { 45 phy1: ethernet-phy@2 { 48 phy2: ethernet-phy@3 { 51 phy3: ethernet-phy@4 { 57 phy-handle = <&phy1>; [all …]
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D | sbc8641d.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 12 /include/ "mpc8641si-pre.dtsi" 35 compatible = "cfi-flash"; 37 bank-width = <2>; 38 device-width = <2>; 39 #address-cells = <1>; 40 #size-cells = <1>; 44 read-only; 49 read-only; 58 read-only; [all …]
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D | mvme2500.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 5 * Copyright 2014 Elettra-Sincrotrone Trieste S.C.p.A. 11 /include/ "p2020si-pre.dtsi" 66 fsl,espi-num-chipselects = <2>; 69 compatible = "atmel,at25df641", "jedec,spi-nor"; 71 spi-max-frequency = <10000000>; 74 compatible = "atmel,at25df641", "jedec,spi-nor"; 76 spi-max-frequency = <10000000>; 86 tbi-handle = <&tbi0>; 87 phy-handle = <&phy1>; [all …]
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/kernel/linux/linux-5.10/drivers/net/ethernet/broadcom/genet/ |
D | bcmmii.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (c) 2014-2017 Broadcom 24 #include <linux/platform_data/mdio-bcm-unimac.h> 29 * update UMAC and RGMII block when link up 34 struct phy_device *phydev = dev->phydev; in bcmgenet_mii_setup() 38 if (priv->old_link != phydev->link) { in bcmgenet_mii_setup() 40 priv->old_link = phydev->link; in bcmgenet_mii_setup() 43 if (phydev->link) { in bcmgenet_mii_setup() 45 if (priv->old_speed != phydev->speed) { in bcmgenet_mii_setup() 47 priv->old_speed = phydev->speed; in bcmgenet_mii_setup() [all …]
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
D | ucc.txt | 4 - device_type : should be "network", "hldc", "uart", "transparent" 6 - compatible : could be "ucc_geth" or "fsl_atm" and so on. 7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM. 8 - reg : Offset and length of the register set for the device 9 - interrupts : <a b> where a is the interrupt number and b is a 14 - pio-handle : The phandle for the Parallel I/O port configuration. 15 - port-number : for UART drivers, the port number to use, between 0 and 3. 18 CPM UART driver, the port-number is required for the QE UART driver. 19 - soft-uart : for UART drivers, if specified this means the QE UART device 20 driver should use "Soft-UART" mode, which is needed on some SOCs that have [all …]
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/kernel/linux/linux-5.10/drivers/pinctrl/qcom/ |
D | pinctrl-ipq4019.c | 1 // SPDX-License-Identifier: GPL-2.0-only 11 #include "pinctrl-msm.h" 226 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14) \ argument 228 .name = "gpio" #id, \ 229 .pins = gpio##id##_pins, \ 230 .npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \ 249 .ctl_reg = 0x0 + 0x1000 * id, \ 250 .io_reg = 0x4 + 0x1000 * id, \ 251 .intr_cfg_reg = 0x8 + 0x1000 * id, \ 252 .intr_status_reg = 0xc + 0x1000 * id, \ [all …]
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/kernel/linux/linux-5.10/arch/mips/ralink/ |
D | rt305x.c | 1 // SPDX-License-Identifier: GPL-2.0-only 6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 17 #include <asm/mach-ralink/ralink_regs.h> 18 #include <asm/mach-ralink/rt305x.h> 19 #include <asm/mach-ralink/pinmux.h> 44 FUNC("rgmii", 0, 24, 12) 46 static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) }; 63 GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII), 76 GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII), 210 rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc"); in ralink_of_remap() [all …]
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/kernel/linux/linux-5.10/drivers/net/ethernet/apm/xgene/ |
D | xgene_enet_hw.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Applied Micro X-Gene SoC Ethernet Driver 15 u32 *ring_cfg = ring->state; in xgene_enet_ring_init() 16 u64 addr = ring->dma; in xgene_enet_ring_init() 17 enum xgene_enet_ring_cfgsize cfgsize = ring->cfgsize; in xgene_enet_ring_init() 35 u32 *ring_cfg = ring->state; in xgene_enet_ring_set_type() 39 is_bufpool = xgene_enet_is_bufpool(ring->id); in xgene_enet_ring_set_type() 52 u32 *ring_cfg = ring->state; in xgene_enet_ring_set_recombbuf() 63 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); in xgene_enet_ring_wr32() 65 iowrite32(data, pdata->ring_csr_addr + offset); in xgene_enet_ring_wr32() [all …]
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
D | fsl-ls1028a-kontron-sl28-var4.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Device Tree file for the Kontron SMARC-sAL28 board. 6 * extends the base and provides one more port connected via RGMII. 12 /dts-v1/; 13 #include "fsl-ls1028a-kontron-sl28.dts" 14 #include <dt-bindings/net/qca-ar803x.h> 17 model = "Kontron SMARC-sAL28 (Dual PHY)"; 18 compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a"; 22 phy-handle = <&phy1>; 23 phy-connection-type = "rgmii-id"; [all …]
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/kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/ |
D | dwmac-ipq806x.c | 46 /* Mode is coded on 1 bit but is different depending on the MAC ID: 47 * MAC0: QSGMII=0 RGMII=1 48 * MAC1: QSGMII=0 SGMII=0 RGMII=1 72 (0x13c + (4 * (x - 2)))) 88 uint32_t id; member 95 struct device *dev = &gmac->pdev->dev; in get_clk_div_sgmii() 113 return -EINVAL; in get_clk_div_sgmii() 121 struct device *dev = &gmac->pdev->dev; in get_clk_div_rgmii() 138 dev_err(dev, "Speed %dMbps not supported in RGMII\n", speed); in get_clk_div_rgmii() 139 return -EINVAL; in get_clk_div_rgmii() [all …]
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