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Searched refs:PACKET3 (Results 1 – 25 of 29) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c2102 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v7_0_ring_test_ring()
2149 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_hdp_flush()
2162 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v7_0_ring_emit_vgt_flush()
2166 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v7_0_ring_emit_vgt_flush()
2188 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v7_0_ring_emit_fence_gfx()
2200 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v7_0_ring_emit_fence_gfx()
2229 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in gfx_v7_0_ring_emit_fence_compute()
2266 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_ib_gfx()
2271 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v7_0_ring_emit_ib_gfx()
2273 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v7_0_ring_emit_ib_gfx()
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Dgfx_v6_0.c1807 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_test_ring()
1829 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v6_0_ring_emit_vgt_flush()
1840 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_emit_fence()
1843 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in gfx_v6_0_ring_emit_fence()
1852 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v6_0_ring_emit_fence()
1872 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v6_0_ring_emit_ib()
1877 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v6_0_ring_emit_ib()
1879 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v6_0_ring_emit_ib()
1922 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); in gfx_v6_0_ring_test_ib()
2032 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in gfx_v6_0_cp_gfx_start()
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Dgfx_v8_0.c853 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v8_0_ring_test_ring()
896 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v8_0_ring_test_ib()
1255 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_get_csb_buffer()
1258 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v8_0_get_csb_buffer()
1266 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v8_0_get_csb_buffer()
1277 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v8_0_get_csb_buffer()
1283 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_get_csb_buffer()
1286 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v8_0_get_csb_buffer()
1575 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1581 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v8_0_do_edc_gpr_workarounds()
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Dgfx_v9_0.c815 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v9_0_kiq_set_resources()
838 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v9_0_kiq_map_queues()
868 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); in gfx_v9_0_kiq_unmap_queues()
895 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); in gfx_v9_0_kiq_query_status()
914 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); in gfx_v9_0_kiq_invalidate_tlbs()
1008 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_0_write_data_to_reg()
1022 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v9_0_wait_reg_mem()
1056 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v9_0_ring_test_ring()
1099 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v9_0_ring_test_ib()
1722 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v9_0_get_csb_buffer()
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Dsi_enums.h168 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
171 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Dsoc15d.h50 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
54 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Dnvd.h48 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
52 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Dvid.h105 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
109 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Dcikd.h223 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
227 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Dgfx_v10_0.c3222 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx10_kiq_set_resources()
3241 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx10_kiq_map_queues()
3267 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); in gfx10_kiq_unmap_queues()
3294 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); in gfx10_kiq_query_status()
3312 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); in gfx10_kiq_invalidate_tlbs()
3418 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v10_0_write_data_to_reg()
3431 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v10_0_wait_reg_mem()
3472 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v10_0_ring_test_ring()
3517 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v10_0_ring_test_ib()
3989 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v10_0_get_csb_buffer()
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Damdgpu_amdkfd_gfx_v10.c332 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in kgd_hiq_mqd_load()
Dsid.h1658 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
1662 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Damdgpu_amdkfd_gfx_v9.c341 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in kgd_gfx_v9_hiq_mqd_load()
Damdgpu_amdkfd_gfx_v10_3.c317 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in hiq_mqd_load_v10_3()
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Dni.c1411 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_fence_ring_emit()
1417 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cayman_fence_ring_emit()
1433 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in cayman_ring_ib_execute()
1438 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in cayman_ring_ib_execute()
1444 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in cayman_ring_ib_execute()
1454 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_ring_ib_execute()
1560 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in cayman_cp_start()
1578 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1584 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1588 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cayman_cp_start()
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Dcik.c3474 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in cik_ring_test()
3530 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_hdp_flush_cp_ring_emit()
3559 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3571 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3598 radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in cik_fence_compute_ring_emit()
3629 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in cik_semaphore_ring_emit()
3635 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cik_semaphore_ring_emit()
3690 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in cik_copy_cpdma()
3737 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in cik_ring_ib_execute()
3740 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in cik_ring_ib_execute()
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Dsi.c3381 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_fence_ring_emit()
3384 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in si_fence_ring_emit()
3393 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in si_fence_ring_emit()
3412 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in si_ring_ib_execute()
3415 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in si_ring_ib_execute()
3420 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_ring_ib_execute()
3426 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_ring_ib_execute()
3433 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in si_ring_ib_execute()
3447 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_ring_ib_execute()
3450 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in si_ring_ib_execute()
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Dr600.c2696 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in r600_cp_start()
2841 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_test()
2879 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2885 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in r600_fence_ring_emit()
2893 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2898 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in r600_fence_ring_emit()
2901 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2905 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2936 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in r600_semaphore_ring_emit()
2943 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in r600_semaphore_ring_emit()
[all …]
Dr300d.h64 #define PACKET3(op, n) (CP_PACKET3 | \ macro
Devergreen.c2936 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in evergreen_ring_ib_execute()
2941 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in evergreen_ring_ib_execute()
2947 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); in evergreen_ring_ib_execute()
2954 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in evergreen_ring_ib_execute()
3008 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in evergreen_cp_start()
3027 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in evergreen_cp_start()
3033 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in evergreen_cp_start()
3037 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in evergreen_cp_start()
Dsid.h1595 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
1599 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Dcikd.h1691 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
1695 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Drv515d.h204 #define PACKET3(op, n) (CP_PACKET3 | \ macro
Drv770d.h988 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
Dnid.h1157 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro

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