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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Dbrcm,cygnus-audio.txt13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
36 assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
40 assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;
41 assigned-clock-rates = <1769470191>,
Dmt2701-afe-pcm.txt47 - assigned-clocks: list of input clocks and dividers for the audio system.
49 - assigned-clocks-parents: parent of input clocks of assigned clocks.
50 - assigned-clock-rates: list of clock frequencies of assigned clocks.
138 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
142 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
144 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx7ulp.dtsi154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
156 assigned-clock-rates = <24000000>;
166 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
168 assigned-clock-rates = <48000000>;
175 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
261 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
262 assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
[all …]
Dexynos4412-odroid-common.dtsi125 assigned-clocks = <&clock CLK_FOUT_EPLL>;
126 assigned-clock-rates = <45158401>;
130 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
136 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
139 assigned-clock-rates = <0>, <0>,
207 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
209 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
210 assigned-clock-rates = <0>, <176000000>;
215 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
217 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
[all …]
Dimx7d-pico.dtsi105 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
107 assigned-clock-parents = <&clks IMX7D_CKIL>;
108 assigned-clock-rates = <0>, <32768>;
121 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
123 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
124 assigned-clock-rates = <0>, <100000000>;
278 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
280 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
281 assigned-clock-rates = <0>, <24576000>;
313 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
[all …]
Dimx7d-cl-som-imx7.dts47 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
49 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
50 assigned-clock-rates = <0>, <100000000>;
75 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
77 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
78 assigned-clock-rates = <0>, <100000000>;
197 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
198 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
212 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
213 assigned-clock-rates = <400000000>;
Dimx7d-zii-rpu2.dts189 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
190 assigned-clock-rates = <884736000>;
211 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
213 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
214 assigned-clock-rates = <0>, <100000000>;
294 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
296 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
297 assigned-clock-rates = <0>, <100000000>;
457 assigned-clocks = <&cs2000>;
458 assigned-clock-rates = <24000000>;
[all …]
Dimx7d-sdb.dts215 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
217 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
218 assigned-clock-rates = <0>, <100000000>;
242 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
244 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
245 assigned-clock-rates = <0>, <100000000>;
386 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
389 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
390 assigned-clock-rates = <0>, <884736000>, <12288000>;
422 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
[all …]
Dimx7s-warp.dts84 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
85 assigned-clock-rates = <884736000>;
268 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
270 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
271 assigned-clock-rates = <0>, <36864000>;
278 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
279 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
286 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
287 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
295 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
[all …]
Dexynos4412-itop-elite.dts130 assigned-clocks = <&clock CLK_MOUT_CAM0>;
131 assigned-clock-parents = <&clock CLK_XUSBXTI>;
135 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
139 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
141 assigned-clock-rates = <0>, <0>, <112896000>, <11289600>;
159 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
161 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
162 assigned-clock-rates = <0>, <176000000>;
Dimx7d-nitrogen7.dts114 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
116 assigned-clock-parents = <&clks IMX7D_CKIL>;
117 assigned-clock-rates = <0>, <32768>;
131 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
133 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
134 assigned-clock-rates = <0>, <100000000>;
322 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
323 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
330 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
331 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
[all …]
Dstih407.dtsi16 assigned-clocks = <&clk_s_d2_quadfs 0>,
28 assigned-clock-parents = <0>,
40 assigned-clock-rates = <297000000>,
88 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
95 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
/kernel/linux/linux-5.10/arch/mips/boot/dts/img/
Dpistachio.dtsi51 assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
53 assigned-clock-rates = <100000000>, <33333334>;
69 assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
71 assigned-clock-rates = <100000000>, <33333334>;
87 assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
89 assigned-clock-rates = <100000000>, <33333334>;
105 assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
107 assigned-clock-rates = <100000000>, <33333334>;
141 assigned-clocks = <&clk_core CLK_I2S_DIV>;
142 assigned-clock-rates = <12288000>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/msm/
Ddpu.txt38 - assigned-clocks: list of clock specifiers for clocks needing rate assignment
39 - assigned-clock-rates: list of clock frequencies sorted in the same order as
40 the assigned-clocks property.
70 - assigned-clocks: list of clock specifiers for clocks needing rate assignment
71 - assigned-clock-rates: list of clock frequencies sorted in the same order as
72 the assigned-clocks property.
87 assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
88 assigned-clock-rates = <300000000>;
116 assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
118 assigned-clock-rates = <0 0 300000000 19200000>;
/kernel/linux/linux-5.10/drivers/s390/char/
Dsclp_cmd.c241 u16 assigned; member
264 for (i = 0; i < sccb->assigned; i++) { in sclp_attach_storage()
425 static void __init insert_increment(u16 rn, int standby, int assigned) in insert_increment() argument
439 if (assigned && incr->rn > rn) in insert_increment()
441 if (!assigned && incr->rn - last_rn > 1) in insert_increment()
446 if (!assigned) in insert_increment()
478 int i, id, assigned, rc; in sclp_detect_standby_memory() local
488 assigned = 0; in sclp_detect_standby_memory()
498 for (i = 0; i < sccb->assigned; i++) { in sclp_detect_standby_memory()
501 assigned++; in sclp_detect_standby_memory()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dphy-rockchip-typec.txt11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
46 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
47 assigned-clock-rates = <50000000>;
70 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
71 assigned-clock-rates = <50000000>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dspi-slave-mt27xx.txt13 - assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>.
14 - assigned-clock-parents: parent of mux clock.
30 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
31 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mq-sr-som.dtsi163 assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
164 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
165 assigned-clock-rates = <25000000>;
172 assigned-clocks = <&clk IMX8MQ_CLK_UART4>;
173 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
174 assigned-clock-rates = <80000000>;
179 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
180 assigned-clock-rates = <400000000>;
Dimx8mq.dtsi517 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
521 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
524 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
607 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
610 assigned-clock-rates = <0>, <0>,
612 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
918 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
921 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
923 assigned-clock-rates = <80000000>, <266000000>, <20000000>;
957 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/
Dk3-j721e-main.dtsi393 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
394 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
402 assigned-clocks = <&wiz0_pll0_refclk>;
403 assigned-clock-parents = <&k3_clks 292 11>;
409 assigned-clocks = <&wiz0_pll1_refclk>;
410 assigned-clock-parents = <&k3_clks 292 0>;
416 assigned-clocks = <&wiz0_refclk_dig>;
417 assigned-clock-parents = <&k3_clks 292 11>;
450 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
451 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pwm/
Dpwm-sprd.txt16 - assigned-clocks: Reference to the PWM clock entries.
17 - assigned-clock-parents: The phandle of the parent clock of PWM clock.
31 assigned-clocks = <&aon_clk CLK_PWM0>,
35 assigned-clock-parents = <&ext_26m>,
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/ata/
Dqcom-sata.txt22 - assigned-clocks : Shall be:
25 - assigned-clock-rates : Shall be:
43 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
44 assigned-clock-rates = <100000000>, <100000000>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dsdhci-atmel.txt15 - assigned-clocks: The same with "multclk".
16 - assigned-clock-rates The rate of "multclk" in order to not rely on the
31 assigned-clocks = <&sdmmc0_gclk>;
32 assigned-clock-rates = <480000000>;
/kernel/linux/linux-5.10/arch/arm64/boot/dts/nvidia/
Dtegra186.dtsi149 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
150 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
209 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
210 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
211 assigned-clock-rates = <1536000>;
223 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
224 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
225 assigned-clock-rates = <1536000>;
237 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
238 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/hisilicon/
Dhisi-ade.txt20 - assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
22 - assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
54 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
56 assigned-clock-rates = <360000000>, <288000000>;

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