| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/ |
| D | opregion.c | 267 gvt_vgpu_err("fail to get MFN from VA\n"); in map_vgpu_opregion()
274 gvt_vgpu_err("fail to map GFN to MFN, errno: %d\n", in map_vgpu_opregion()
321 gvt_vgpu_err("not supported hypervisor\n"); in intel_vgpu_opregion_base_write_handler()
489 gvt_vgpu_err("guest opregion read error %d, gpa 0x%llx, len %lu\n", in intel_vgpu_emulate_opregion_request()
497 gvt_vgpu_err("guest opregion read error %d, gpa 0x%llx, len %lu\n", in intel_vgpu_emulate_opregion_request()
504 gvt_vgpu_err("not supported hypervisor\n"); in intel_vgpu_emulate_opregion_request()
509 gvt_vgpu_err("requesting SMI service\n"); in intel_vgpu_emulate_opregion_request()
522 gvt_vgpu_err("requesting runtime service: func \"%s\"," in intel_vgpu_emulate_opregion_request()
549 gvt_vgpu_err("guest opregion write error %d, gpa 0x%llx, len %lu\n", in intel_vgpu_emulate_opregion_request()
557 gvt_vgpu_err("guest opregion write error %d, gpa 0x%llx, len %lu\n", in intel_vgpu_emulate_opregion_request()
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| D | dmabuf.c | 303 gvt_vgpu_err("invalid tiling mode: %x\n", p.tiled); in vgpu_get_plane_info()
327 gvt_vgpu_err("invalid plane id:%d\n", plane_id); in vgpu_get_plane_info()
333 gvt_vgpu_err("fb size is zero\n"); in vgpu_get_plane_info()
338 gvt_vgpu_err("Not aligned fb address:0x%llx\n", info->start); in vgpu_get_plane_info()
343 gvt_vgpu_err("invalid gma addr\n"); in vgpu_get_plane_info()
467 gvt_vgpu_err("alloc dmabuf_obj failed\n"); in intel_vgpu_query_plane()
475 gvt_vgpu_err("allocate intel vgpu fb info failed\n"); in intel_vgpu_query_plane()
497 gvt_vgpu_err("get vfio device failed\n"); in intel_vgpu_query_plane()
538 gvt_vgpu_err("invalid dmabuf id:%d\n", dmabuf_id); in intel_vgpu_get_dmabuf()
545 gvt_vgpu_err("create gvt gem obj failed\n"); in intel_vgpu_get_dmabuf()
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| D | fb_decoder.c | 227 gvt_vgpu_err("Out-of-bounds pixel format index\n"); in intel_vgpu_decode_primary_plane()
241 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt); in intel_vgpu_decode_primary_plane()
253 gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n", in intel_vgpu_decode_primary_plane()
353 gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode); in intel_vgpu_decode_cursor_plane()
376 gvt_vgpu_err("Translate cursor plane gma 0x%x to gpa fail\n", in intel_vgpu_decode_cursor_plane()
435 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt); in intel_vgpu_decode_sprite_plane()
480 gvt_vgpu_err("Translate sprite plane gma 0x%x to gpa fail\n", in intel_vgpu_decode_sprite_plane()
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| D | cmd_parser.c | 907 gvt_vgpu_err("failed to get the 4-level shadow vm\n"); in cmd_pdp_mmio_update_handler()
920 gvt_vgpu_err("invalid shared shadow vm type\n"); in cmd_pdp_mmio_update_handler()
934 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n", in cmd_reg_handler()
940 gvt_vgpu_err("%s access to non-render register (%x)\n", in cmd_reg_handler()
946 gvt_vgpu_err("found access of shadowed MMIO %x\n", offset); in cmd_reg_handler()
1336 gvt_vgpu_err("unknown plane code %d\n", plane); in skl_decode_mi_display_flip()
1454 gvt_vgpu_err("fail to decode MI display flip command\n"); in cmd_handler_mi_display_flip()
1460 gvt_vgpu_err("invalid MI display flip command\n"); in cmd_handler_mi_display_flip()
1466 gvt_vgpu_err("fail to update plane mmio\n"); in cmd_handler_mi_display_flip()
1504 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes); in get_gma_bb_from_cmd()
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| D | scheduler.c | 217 gvt_vgpu_err("Invalid guest context descriptor\n"); in populate_shadow_context()
367 gvt_vgpu_err("fail to emit init breadcrumb\n"); in copy_workload_to_ring_buffer()
375 gvt_vgpu_err("fail to alloc size =%ld shadow ring buffer\n", in copy_workload_to_ring_buffer()
450 gvt_vgpu_err("fail to allocate gem request\n"); in intel_gvt_workload_req_alloc()
644 gvt_vgpu_err("fail to vgpu pin mm\n"); in intel_vgpu_shadow_mm_pin()
650 gvt_vgpu_err("workload shadow ppgtt isn't ready\n"); in intel_vgpu_shadow_mm_pin()
663 gvt_vgpu_err("LRI shadow ppgtt fail to pin\n"); in intel_vgpu_shadow_mm_pin()
696 gvt_vgpu_err("fail to pin shadow mm\n"); in prepare_workload()
706 gvt_vgpu_err("fail to vgpu sync oos pages\n"); in prepare_workload()
712 gvt_vgpu_err("fail to flush post shadow\n"); in prepare_workload()
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| D | execlist.c | 196 gvt_vgpu_err("schedule out context is not running context," in emulate_execlist_ctx_schedule_out()
266 gvt_vgpu_err("virtual execlist slots are full\n"); in get_next_execlist_slot()
287 gvt_vgpu_err("no available execlist slot\n"); in emulate_execlist_schedule_in()
386 gvt_vgpu_err("fail to emulate execlist schedule in\n"); in prepare_execlist_workload()
468 gvt_vgpu_err("invalid elsp submission, desc0 is invalid\n"); in intel_vgpu_submit_execlist()
476 gvt_vgpu_err("unexpected GGTT elsp submission\n"); in intel_vgpu_submit_execlist()
487 gvt_vgpu_err("failed to submit desc %d\n", i); in intel_vgpu_submit_execlist()
495 gvt_vgpu_err("descriptors content: desc0 %08x %08x desc1 %08x %08x\n", in intel_vgpu_submit_execlist()
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| D | edid.c | 55 gvt_vgpu_err("Driver tries to read EDID without proper sequence!\n"); in edid_get_byte()
59 gvt_vgpu_err("edid_get_byte() exceeds the size of EDID!\n"); in edid_get_byte()
64 gvt_vgpu_err("Reading EDID but EDID is not available!\n"); in edid_get_byte()
75 gvt_vgpu_err("No EDID available during the reading?\n"); in edid_get_byte()
262 gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n"); in gmbus1_mmio_write()
333 gvt_vgpu_err("warning: gmbus3 read with nothing returned\n"); in gmbus3_mmio_read()
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| D | kvmgt.c | 192 gvt_vgpu_err("vfio_pin_pages failed for gfn 0x%lx, ret %d\n", in gvt_pin_guest_page()
198 gvt_vgpu_err("pfn 0x%lx is not mem backed\n", pfn); in gvt_pin_guest_page()
207 gvt_vgpu_err("The pages are not continuous\n"); in gvt_pin_guest_page()
235 gvt_vgpu_err("DMA mapping failed for pfn 0x%lx, ret %d\n", in gvt_dma_map_page()
460 gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n"); in intel_vgpu_reg_rw_opregion()
502 gvt_vgpu_err("invalid EDID blob\n"); in handle_edid_regs()
509 gvt_vgpu_err("invalid EDID link state %d\n", in handle_edid_regs()
517 gvt_vgpu_err("EDID size is bigger than %d!\n", in handle_edid_regs()
525 gvt_vgpu_err("write read-only EDID region at offset %d\n", in handle_edid_regs()
568 gvt_vgpu_err("failed to access EDID region\n"); in intel_vgpu_reg_rw_edid()
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| D | gtt.c | 836 gvt_vgpu_err("fail to allocate ppgtt shadow page\n"); in ppgtt_alloc_spt()
851 gvt_vgpu_err("fail to map dma addr\n"); in ppgtt_alloc_spt()
973 gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n", in ppgtt_invalidate_spt_by_shadow_entry()
1046 gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n", in ppgtt_invalidate_spt()
1128 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n", in ppgtt_populate_spt_by_guest_entry()
1296 gvt_vgpu_err("GVT doesn't support 1GB entry\n"); in ppgtt_populate_shadow_entry()
1351 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n", in ppgtt_populate_spt()
1380 gvt_vgpu_err("fail to find guest page\n"); in ppgtt_handle_guest_entry_removal()
1396 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n", in ppgtt_handle_guest_entry_removal()
1431 gvt_vgpu_err("fail: spt %p guest entry 0x%llx type %d\n", in ppgtt_handle_guest_entry_add()
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| D | debug.h | 30 #define gvt_vgpu_err(fmt, args...) \ macro
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| D | mmio.c | 160 gvt_vgpu_err("fail to emulate MMIO read %08x len %d\n", in intel_vgpu_emulate_mmio_read()
227 gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset, in intel_vgpu_emulate_mmio_write()
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| D | aperture_gm.c | 218 gvt_vgpu_err("Failed to alloc fences\n"); in alloc_vgpu_fence()
249 gvt_vgpu_err("Invalid vGPU creation params\n"); in alloc_resource()
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| D | handlers.c | 200 gvt_vgpu_err("access oob fence reg %d/%d\n", in sanitize_fence_mmio_access()
232 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n", in gamw_echo_dev_rw_ia_write()
301 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); in mul_force_wake_write()
605 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); in check_fdi_rx_train_status()
663 gvt_vgpu_err("Unsupport registers %x\n", offset); in update_fdi_rx_iir_status()
921 gvt_vgpu_err("Unsupported DP port access!\n"); in dp_aux_ch_ctl_mmio_write()
979 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); in dp_aux_ch_ctl_mmio_write()
1046 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); in dp_aux_ch_ctl_mmio_write()
1132 gvt_vgpu_err("SBI caching meets maximum limits\n"); in write_virtual_sbi_register()
1212 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", in pvinfo_mmio_read()
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| D | mmio_context.c | 383 gvt_vgpu_err("timeout in invalidate ring %s tlb\n", in handle_tlb_pending_event()
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