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Searched refs:rb_bufsz (Results 1 – 25 of 38) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Damdgpu_ih.c44 u32 rb_bufsz; in amdgpu_ih_ring_init() local
48 rb_bufsz = order_base_2(ring_size / 4); in amdgpu_ih_ring_init()
49 ring_size = (1 << rb_bufsz) * 4; in amdgpu_ih_ring_init()
Dcik_ih.c109 int rb_bufsz; in cik_ih_irq_init() local
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cik_ih_irq_init()
131 (rb_bufsz << 1)); in cik_ih_irq_init()
Dsi_ih.c65 int rb_bufsz; in si_ih_irq_init() local
77 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in si_ih_irq_init()
81 (rb_bufsz << 1) | in si_ih_irq_init()
Duvd_v3_1.c319 uint32_t rb_bufsz; in uvd_v3_1_start() local
429 rb_bufsz = order_base_2(ring->ring_size); in uvd_v3_1_start()
430 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v3_1_start()
431 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v3_1_start()
Duvd_v4_2.c255 uint32_t rb_bufsz; in uvd_v4_2_start() local
365 rb_bufsz = order_base_2(ring->ring_size); in uvd_v4_2_start()
366 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v4_2_start()
367 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v4_2_start()
Dcz_ih.c110 int rb_bufsz; in cz_ih_irq_init() local
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cz_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
Diceland_ih.c109 int rb_bufsz; in iceland_ih_irq_init() local
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in iceland_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
Dtonga_ih.c106 int rb_bufsz; in tonga_ih_irq_init() local
125 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in tonga_ih_irq_init()
127 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in tonga_ih_irq_init()
Dvcn_v2_5.c775 uint32_t rb_bufsz, tmp; in vcn_v2_5_start_dpg_mode() local
871 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_start_dpg_mode()
872 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start_dpg_mode()
918 uint32_t rb_bufsz, tmp; in vcn_v2_5_start() local
1063 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_start()
1064 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start()
1167 uint32_t offset, size, tmp, i, rb_bufsz; in vcn_v2_5_sriov_start() local
1282 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_sriov_start()
1283 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_sriov_start()
Duvd_v5_0.c293 uint32_t rb_bufsz, tmp; in uvd_v5_0_start() local
390 rb_bufsz = order_base_2(ring->ring_size); in uvd_v5_0_start()
392 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v5_0_start()
Dsi_dma.c133 u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; in si_dma_start() local
144 rb_bufsz = order_base_2(ring->ring_size / 4); in si_dma_start()
145 rb_cntl = rb_bufsz << 1; in si_dma_start()
Dvcn_v1_0.c791 uint32_t rb_bufsz, tmp; in vcn_v1_0_start_spg_mode() local
910 rb_bufsz = order_base_2(ring->ring_size); in vcn_v1_0_start_spg_mode()
911 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start_spg_mode()
965 uint32_t rb_bufsz, tmp; in vcn_v1_0_start_dpg_mode() local
1068 rb_bufsz = order_base_2(ring->ring_size); in vcn_v1_0_start_dpg_mode()
1069 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start_dpg_mode()
Dvcn_v2_0.c798 uint32_t rb_bufsz, tmp; in vcn_v2_0_start_dpg_mode() local
888 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_0_start_dpg_mode()
889 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start_dpg_mode()
935 uint32_t rb_bufsz, tmp; in vcn_v2_0_start() local
1060 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_0_start()
1061 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start()
Dvcn_v3_0.c899 uint32_t rb_bufsz, tmp; in vcn_v3_0_start_dpg_mode() local
999 rb_bufsz = order_base_2(ring->ring_size); in vcn_v3_0_start_dpg_mode()
1000 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v3_0_start_dpg_mode()
1044 uint32_t rb_bufsz, tmp; in vcn_v3_0_start() local
1177 rb_bufsz = order_base_2(ring->ring_size); in vcn_v3_0_start()
1178 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v3_0_start()
Dsdma_v2_4.c412 u32 rb_bufsz; in sdma_v2_4_gfx_resume() local
436 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v2_4_gfx_resume()
438 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v2_4_gfx_resume()
Dvega10_ih.c168 int rb_bufsz = order_base_2(ih->ring_size / 4); in vega10_ih_rb_cntl() local
176 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in vega10_ih_rb_cntl()
Dcik_sdma.c434 u32 rb_bufsz; in cik_sdma_gfx_resume() local
460 rb_bufsz = order_base_2(ring->ring_size / 4); in cik_sdma_gfx_resume()
461 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
Dnavi10_ih.c213 int rb_bufsz = order_base_2(ih->ring_size / 4); in navi10_ih_rb_cntl() local
221 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in navi10_ih_rb_cntl()
Dgfx_v6_0.c2089 u32 rb_bufsz; in gfx_v6_0_cp_gfx_resume() local
2105 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v6_0_cp_gfx_resume()
2106 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in gfx_v6_0_cp_gfx_resume()
2186 u32 rb_bufsz; in gfx_v6_0_cp_compute_resume() local
2194 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v6_0_cp_compute_resume()
2195 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in gfx_v6_0_cp_compute_resume()
2214 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v6_0_cp_compute_resume()
2215 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in gfx_v6_0_cp_compute_resume()
Dsdma_v3_0.c647 u32 rb_bufsz; in sdma_v3_0_gfx_resume() local
674 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v3_0_gfx_resume()
676 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v3_0_gfx_resume()
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Duvd_v1_0.c266 uint32_t rb_bufsz; in uvd_v1_0_start() local
377 rb_bufsz = order_base_2(ring->ring_size); in uvd_v1_0_start()
378 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v1_0_start()
379 WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v1_0_start()
Dni_dma.c191 u32 rb_bufsz; in cayman_dma_resume() local
210 rb_bufsz = order_base_2(ring->ring_size / 4); in cayman_dma_resume()
211 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
Dr600_dma.c124 u32 rb_bufsz; in r600_dma_resume() local
131 rb_bufsz = order_base_2(ring->ring_size / 4); in r600_dma_resume()
132 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
Dcik_sdma.c369 u32 rb_bufsz; in cik_sdma_gfx_resume() local
388 rb_bufsz = order_base_2(ring->ring_size / 4); in cik_sdma_gfx_resume()
389 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
Dr600.c2719 u32 rb_bufsz; in r600_cp_resume() local
2729 rb_bufsz = order_base_2(ring->ring_size / 8); in r600_cp_resume()
2730 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in r600_cp_resume()
2781 u32 rb_bufsz; in r600_ring_init() local
2785 rb_bufsz = order_base_2(ring_size / 8); in r600_ring_init()
2786 ring_size = (1 << (rb_bufsz + 1)) * 4; in r600_ring_init()
3471 u32 rb_bufsz; in r600_ih_ring_init() local
3474 rb_bufsz = order_base_2(ring_size / 4); in r600_ih_ring_init()
3475 ring_size = (1 << rb_bufsz) * 4; in r600_ih_ring_init()
3677 int rb_bufsz; in r600_irq_init() local
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