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Searched refs:GFX10 (Results 1 – 25 of 142) sorted by relevance

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/third_party/mesa3d/src/amd/compiler/tests/
Dtest_assembler.cpp29 for (unsigned i = GFX6; i <= GFX10; i++) {
44 if (!setup_cs(NULL, (chip_class)GFX10))
63 if (!setup_cs(NULL, (chip_class)GFX10))
93 if (!setup_cs(NULL, (chip_class)GFX10))
126 if (!setup_cs(NULL, (chip_class)GFX10))
154 if (!setup_cs(NULL, (chip_class)GFX10))
183 if (!setup_cs(NULL, (chip_class)GFX10))
208 if (!setup_cs(NULL, (chip_class)GFX10))
234 for (unsigned i = GFX9; i <= GFX10; i++) {
252 for (unsigned i = GFX9; i <= GFX10; i++) {
Dtest_regalloc.cpp64 if (!setup_cs("v1", GFX10))
83 if (!setup_cs("s2", GFX10))
102 if (!setup_cs("s2 s1", GFX10))
119 if (!setup_cs("s2 s1 s1", GFX10))
136 if (!setup_cs("s2 s1 s1", GFX10))
190 if (!setup_cs("", GFX10))
211 if (!setup_cs("", GFX10))
242 if (!setup_cs("", GFX10))
267 if (!setup_cs("", GFX10))
Dtest_sdwa.cpp30 for (unsigned i = GFX8; i <= GFX10; i++) {
51 for (unsigned i = GFX7; i <= GFX10; i++) {
67 for (unsigned i = GFX8; i <= GFX10; i++) {
96 for (unsigned i = GFX8; i <= GFX10; i++) {
117 for (unsigned i = GFX8; i <= GFX10; i++) {
133 for (unsigned i = GFX8; i <= GFX10; i++) {
154 for (unsigned i = GFX7; i <= GFX10; i++) {
278 for (unsigned i = GFX8; i <= GFX10; i++) {
335 for (unsigned i = GFX8; i <= GFX10; i++) {
379 for (unsigned i = GFX8; i <= GFX10; i++) {
[all …]
Dtest_hard_clause.cpp99 if (!setup_cs(NULL, GFX10))
167 if (!setup_cs(NULL, GFX10))
206 for (unsigned i = GFX10; i <= GFX10_3; i++) {
239 if (!setup_cs(NULL, GFX10))
330 if (!setup_cs(NULL, GFX10))
Dtest_insert_nops.cpp53 if (!setup_cs(NULL, GFX10))
117 if (!setup_cs(NULL, GFX10))
Dtest_isel.cpp85 for (unsigned i = GFX8; i <= GFX10; i++) {
114 for (unsigned i = GFX8; i <= GFX10; i++) {
/third_party/mesa3d/src/amd/vulkan/winsys/null/
Dradv_null_winsys.c89 info->chip_class = GFX10; in radv_null_winsys_query_info()
111 else if (info->chip_class >= GFX10) in radv_null_winsys_query_info()
118 if (info->chip_class >= GFX10) in radv_null_winsys_query_info()
125 info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256; in radv_null_winsys_query_info()
126 info->num_simd_per_compute_unit = info->chip_class >= GFX10 ? 2 : 4; in radv_null_winsys_query_info()
127 info->lds_size_per_workgroup = info->chip_class >= GFX10 ? 128 * 1024 : 64 * 1024; in radv_null_winsys_query_info()
/third_party/mesa3d/src/amd/compiler/
Daco_print_asm.cpp89 case GFX10: in to_clrx_device_name()
157 (chip >= GFX10 && (binary[pos] & 0xffff8000) == 0xd7610000)) { in disasm_instr()
165 if (chip >= GFX10 && l == 8 && ((binary[pos] & 0xffff0000) == 0xd7610000) && in disasm_instr()
175 (chip >= GFX10 && (binary[pos] & 0xffff8000) == 0xd7038000) || /* v_add_u16_e64 + clamp */ in disasm_instr()
177 (chip >= GFX10 && (binary[pos] & 0xffff8000) == 0xd76d8000) || /* v_add3_u32 + clamp */ in disasm_instr()
180 bool has_literal = chip >= GFX10 && (((binary[pos + 1] & 0x1ff) == 0xff) || in disasm_instr()
183 } else if (chip >= GFX10 && l == 4 && ((binary[pos] & 0xfe0001ff) == 0x020000f9)) { in disasm_instr()
222 if (program->chip_class >= GFX10 && program->wave_size == 64) { in print_asm_llvm()
Daco_assembler.cpp57 else if (chip_class >= GFX10) in asm_context()
124 assert(ctx.chip_class >= GFX10); in emit_instruction()
128 assert(ctx.chip_class >= GFX10); in emit_instruction()
242 uint32_t soffset = ctx.chip_class >= GFX10 in emit_instruction()
312 } else if (ctx.chip_class >= GFX10) { in emit_instruction()
394 } else if (ctx.chip_class >= GFX10) { in emit_instruction()
400 if (ctx.chip_class <= GFX7 || ctx.chip_class >= GFX10) { in emit_instruction()
419 assert(!mtbuf.dlc || ctx.chip_class >= GFX10); in emit_instruction()
445 if (ctx.chip_class >= GFX10) { in emit_instruction()
454 assert(!nsa_dwords || ctx.chip_class >= GFX10); in emit_instruction()
[all …]
Daco_insert_waitcnt.cpp197 max_lgkm_cnt(program_->chip_class >= GFX10 ? 62 : 14), in wait_ctx()
198 max_vs_cnt(program_->chip_class >= GFX10 ? 62 : 0), in wait_ctx()
199 unordered_events(event_smem | (program_->chip_class < GFX10 ? event_flat : 0)) in wait_ctx()
342 if (ctx.chip_class >= GFX10) { in force_waitcnt()
369 if (ctx.chip_class >= GFX10 && instr->isSMEM()) { in kill()
550 assert(ctx.chip_class < GFX10); in update_counters_for_flat_load()
637 if (ctx.chip_class < GFX10 && !instr->definitions.empty()) in gen()
652 else if (ctx.chip_class >= GFX10 && !smem.sync.can_reorder()) in gen()
678 !instr->definitions.empty() || ctx.chip_class < GFX10 ? event_vmem : event_vmem_store; in gen()
712 assert(ctx.chip_class >= GFX10); in emit_waitcnt()
Daco_ir.cpp82 case GFX10: program->family = CHIP_NAVI10; break; in init_program()
102 if (chip_class >= GFX10) { in init_program()
127 else if (program->chip_class == GFX10) in init_program()
132 program->dev.simd_per_cu = program->chip_class >= GFX10 ? 2 : 4; in init_program()
458 case aco_opcode::v_cos_f16: return chip >= GFX10; in instr_is_16bit()
466 default: return chip >= GFX10 && can_use_opsel(chip, op, -1, false); in instr_is_16bit()
747 if (chip >= GFX10) in wait_imm()
757 case GFX10: in pack()
777 if (chip < GFX10 && lgkm == wait_imm::unset_counter) in pack()
Daco_statistics.cpp115 if (program->chip_class >= GFX10) { in get_perf_info()
268 unsigned max_lgkm_cnt = program->chip_class >= GFX10 ? 62 : 14; in get_wait_imm()
309 } else if (program->chip_class >= GFX10) { in get_dependency_cost()
318 if (program->chip_class < GFX10) in get_dependency_cost()
360 bool dual_issue = program->chip_class >= GFX10 && program->wave_size == 64 && in add()
369 cur_cycle += program->chip_class >= GFX10 ? 1 : perf.latency; in add()
Daco_reduce_assign.cpp133 if (program->chip_class >= GFX10 && cluster_size == 64) in setup_reduce_temp()
135 if (program->chip_class >= GFX10 && gfx10_need_vtmp) in setup_reduce_temp()
DREADME-ISA.md200 ## RDNA / GFX10 hazards
207 This is not mentioned by LLVM among the other GFX10 bugs, but LLVM doesn't use
242 ACO doesn't use FLAT load/store on GFX10, so is unaffected.
249 ACO doesn't use FLAT load/store on GFX10, so is unaffected.
280 "MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
284 NSA MIMG instructions should be limited to 3 dwords before GFX10.3 to avoid
/third_party/mesa3d/src/amd/common/
Dac_surface_test_common.h99 info->chip_class = GFX10; in init_navi10()
114 info->chip_class = GFX10; in init_navi14()
198 case GFX10: in get_radeon_info()
Dac_gpu_info.c638 info->chip_class = GFX10; in ac_query_gpu_info()
747 if (info->chip_class >= GFX10) { in ac_query_gpu_info()
814 info->lds_size_per_workgroup = info->chip_class >= GFX10 ? 128 * 1024 : 64 * 1024; in ac_query_gpu_info()
852 info->chip_class >= GFX10 || (info->chip_class >= GFX8 && info->max_se >= 2); in ac_query_gpu_info()
855 info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR || info->chip_class >= GFX10; in ac_query_gpu_info()
897 info->has_zero_index_buffer_bug = info->chip_class == GFX10; in ac_query_gpu_info()
909 info->has_two_planes_iterate256_bug = info->chip_class == GFX10; in ac_query_gpu_info()
912 info->has_vgt_flush_ngg_legacy_bug = info->chip_class == GFX10 || in ac_query_gpu_info()
930 info->has_32bit_predication = (info->chip_class >= GFX10 && in ac_query_gpu_info()
959 unsigned cu_group = info->chip_class >= GFX10 ? 2 : 1; in ac_query_gpu_info()
[all …]
Dac_sqtt.c70 if (rad_info->chip_class >= GFX10) { in ac_is_thread_trace_complete()
93 if (rad_info->chip_class >= GFX10) { in ac_get_expected_buffer_size()
Dac_shader_util.c117 if (chip_class >= GFX10) { in ac_get_tbuffer_format()
470 if (info->chip_class >= GFX10) { in ac_compute_late_alloc()
480 if (info->chip_class == GFX10 && ngg) in ac_compute_late_alloc()
488 *cu_mask &= info->chip_class == GFX10 ? ~BITFIELD_RANGE(2, 2) : in ac_compute_late_alloc()
Dac_shadowed_regs.c836 else if (chip_class == GFX10) in ac_get_reg_ranges()
844 else if (chip_class == GFX10) in ac_get_reg_ranges()
850 if (chip_class == GFX10_3 || chip_class == GFX10) in ac_get_reg_ranges()
858 if (chip_class == GFX10_3 || chip_class == GFX10) in ac_get_reg_ranges()
868 else if (chip_class == GFX10) in ac_get_reg_ranges()
2940 } else if (info->chip_class == GFX10) { in ac_emulate_clear_state()
Dac_rgp.c379 case GFX10: in ac_chip_class_to_sqtt_gfxip_level()
441 bool has_wave32 = rad_info->chip_class >= GFX10; in ac_sqtt_fill_asic_info()
501 if (rad_info->chip_class >= GFX10) { in ac_sqtt_fill_asic_info()
511 if (rad_info->chip_class == GFX10) in ac_sqtt_fill_asic_info()
743 case GFX10: in ac_chip_class_to_sqtt_version()
819 case GFX10: in ac_chip_class_to_elf_gfxip_level()
Dac_surface.c128 if (chip_class < GFX10) in ac_surface_supports_dcc_image_stores()
216 case GFX10: in ac_is_modifier_supported()
337 case GFX10: in ac_get_supported_modifiers()
1408 if (info->chip_class >= GFX10 && in->resourceType == ADDR_RSRC_TEX_3D && in->numSlices > 1) { in gfx9_get_preferred_swizzle_mode()
1435 if (info->chip_class >= GFX10) in is_dcc_supported_by_CB()
1478 assert(info->chip_class >= GFX10); in gfx10_DCN_requires_independent_64B_blocks()
1494 if (info->chip_class >= GFX10 && !independent_64B_blocks) { in ac_modifier_max_extent()
1539 case GFX10: in is_dcc_supported_by_DCN()
1542 if (info->chip_class == GFX10 && surf->u.gfx9.color.dcc.independent_128B_blocks) in is_dcc_supported_by_DCN()
1562 if (info->chip_class >= GFX10) { in ac_copy_dcc_equation()
[all …]
/third_party/mesa3d/src/amd/vulkan/
Dradv_sqtt.c82 if (device->physical_device->rad_info.chip_class >= GFX10) { in radv_emit_thread_trace_start()
213 if (device->physical_device->rad_info.chip_class >= GFX10) { in radv_copy_thread_trace_info_regs()
265 if (device->physical_device->rad_info.chip_class >= GFX10) { in radv_emit_thread_trace_stop()
327 if (device->physical_device->rad_info.chip_class >= GFX10) in radv_emit_thread_trace_userdata()
346 if (device->physical_device->rad_info.chip_class >= GFX10) in radv_emit_spi_config_cntl()
361 if (device->physical_device->rad_info.chip_class >= GFX10) { in radv_emit_inhibit_clockgating()
655 thread_trace_se.compute_unit = device->physical_device->rad_info.chip_class >= GFX10 in radv_get_thread_trace()
Dradv_shader.c1309 return chip >= GFX10; in radv_should_use_wgp_mode()
1311 return chip == GFX10 || (chip >= GFX10_3 && !info->is_ngg); in radv_should_use_wgp_mode()
1314 return chip == GFX10 && info->is_ngg; in radv_should_use_wgp_mode()
1340 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0) || in radv_postprocess_config()
1341 (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0)); in radv_postprocess_config()
1370 if (pdevice->rad_info.chip_class >= GFX10) { in radv_postprocess_config()
1382 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); in radv_postprocess_config()
1393 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); in radv_postprocess_config()
1404 if (pdevice->rad_info.chip_class >= GFX10) { in radv_postprocess_config()
1417 S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) | S_00B428_WGP_MODE(wgp_mode); in radv_postprocess_config()
[all …]
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_build_pm4.h37 #define SI_CHECK_SHADOWED_REGS(reg_offset, count) ac_check_shadowed_regs(GFX10, CHIP_NAVI14, reg_of…
292 if (chip_class >= GFX10) { in si_get_user_data_base()
299 } else if (chip_class >= GFX10) { in si_get_user_data_base()
321 if (chip_class >= GFX10) { in si_get_user_data_base()
/third_party/mesa3d/src/intel/compiler/
Dbrw_gfx_ver_enum.h36 GFX10 = (1 << 8), enumerator

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