| /third_party/jerryscript/jerry-libm/ |
| D | expm1.c | 137 #define Q5 -2.01099218183624371326e-07 /* BE8AFDB7 6E09C32D */ macro
233 r1 = one + hxs * (Q1 + hxs * (Q2 + hxs * (Q3 + hxs * (Q4 + hxs * Q5)))); in expm1()
305 #undef Q5
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.td | 104 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
106 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
108 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
111 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
113 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
146 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
148 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
150 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
153 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
155 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
[all …]
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| D | AArch64CallingConvention.cpp | 36 AArch64::Q3, AArch64::Q4, AArch64::Q5,
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| D | AArch64PBQPRegAlloc.cpp | 81 case AArch64::Q5: in isOdd()
|
| D | AArch64SchedPredicates.td | 175 CheckRegOperand<0, Q5>,
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| D | AArch64RegisterInfo.td | 393 def Q5 : AArch64Reg<5, "q5", [D5], ["v5", ""]>, DwarfRegAlias<B5>;
754 def Z5 : AArch64Reg<5, "z5", [Q5, Z5_HI]>, DwarfRegNum<[101]>;
|
| /third_party/boost/libs/mp11/test/ |
| D | mp_invoke_q.cpp | 38 struct Q5 struct
60 BOOST_TEST_TRAIT_TRUE((std::is_same<mp_invoke_q<Q5, int, float>, float>)); in main() argument
|
| /third_party/boost/boost/move/detail/ |
| D | fwd_macros.hpp | 103 #define BOOST_MOVE_FWDQ6 BOOST_MOVE_FWDQ5, ::boost::forward<Q5>(q5)
199 #define BOOST_MOVE_DECLVALQ6 BOOST_MOVE_DECLVALQ5, ::boost::move_detail::declval<Q5>()
310 #define BOOST_MOVE_FWD_INITQ6 BOOST_MOVE_FWD_INITQ5, m_q5(::boost::forward<Q5>(q5))
358 #define BOOST_MOVE_UREFQ6 BOOST_MOVE_UREFQ5, BOOST_FWD_REF(Q5) q5
382 #define BOOST_MOVE_VALQ6 BOOST_MOVE_VALQ5, BOOST_FWD_REF(Q5) q5
408 #define BOOST_MOVE_CREFQ6 BOOST_MOVE_CREFQ5, BOOST_MOVE_UNVOIDCREF(Q5) q5
432 #define BOOST_MOVE_CLASSQ6 BOOST_MOVE_CLASSQ5, class Q5
456 #define BOOST_MOVE_CLASSDFLTQ6 BOOST_MOVE_CLASSDFLTQ5, class Q5 = void
480 #define BOOST_MOVE_LAST_TARGQ6 Q5
505 #define BOOST_MOVE_TARGQ6 BOOST_MOVE_TARGQ5, Q5
[all …]
|
| /third_party/musl/porting/liteos_a/kernel/src/math/ |
| D | expm1.c | 119 Q5 = -2.01099218183624371326e-07; /* BE8AFDB7 6E09C32D */ variable
170 r1 = 1.0+hxs*(Q1+hxs*(Q2+hxs*(Q3+hxs*(Q4+hxs*Q5)))); in expm1()
|
| /third_party/musl/src/math/ |
| D | expm1.c | 119 Q5 = -2.01099218183624371326e-07; /* BE8AFDB7 6E09C32D */ variable
170 r1 = 1.0+hxs*(Q1+hxs*(Q2+hxs*(Q3+hxs*(Q4+hxs*Q5)))); in expm1()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenCallingConv.inc | 271 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
284 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
297 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
316 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
333 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
515 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
528 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
541 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
560 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
576 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
[all …]
|
| /third_party/skia/third_party/externals/microhttpd/src/testcurl/https/ |
| D | host2.key | 9 u5E0q1YdAkEA09FPcmzVvIR0+sMWca8QJ/tJUxD6qYo8vLOpO4wt4iTPhGBEU+Q5
|
| /third_party/ffmpeg/libavcodec/x86/ |
| D | vp9lpf.asm | 331 %define Q5 dst2q + strideq + %1
351 %define Q5 rsp + 13*mmsize + %1
|
| D | vp9lpf_16bpp.asm | 580 PRELOAD 8, %%q5, Q5
|
| /third_party/mesa3d/src/mesa/main/ |
| D | texcompress_astc.cpp | 180 uint8_t Q5 = (in >> (3*n+5)) & 0x1; in unpack_quint_block() local
189 if (CAT_BITS_4(Q6, Q5, Q2, Q1) == 0x3) { in unpack_quint_block()
196 C = CAT_BITS_5(Q4, Q3, 0x1 & ~Q6, 0x1 & ~Q5, Q0); in unpack_quint_block()
198 q2 = CAT_BITS_2(Q6, Q5); in unpack_quint_block()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCTargetDesc.cpp | 200 {codeview::RegisterId::ARM64_Q5, AArch64::Q5}, in initLLVMToCVRegMapping()
|
| D | AArch64InstPrinter.cpp | 1169 case AArch64::Q4: Reg = AArch64::Q5; break; in getNextVectorRegister()
1170 case AArch64::Q5: Reg = AArch64::Q6; break; in getNextVectorRegister()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.td | 114 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 96 SP::Q5, SP::Q13, ~0U, ~0U,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 271 def Q5 : Rq<20, "F20", [D10, D11]>;
|
| /third_party/flutter/skia/third_party/externals/icu/source/data/locales/ |
| D | sd.txt | 732 "Q5",
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 306 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
630 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenRegisterInfo.inc | 81 Q5 = 61,
2087 …3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::…
2097 …3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::…
2107 …ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10…
2117 …3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::…
2137 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
2147 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
6245 …Q13, ARM::Q14, ARM::Q15, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, A…
6246 …static const MCPhysReg AltOrder2[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::…
6263 …static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::…
[all …]
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| /third_party/skia/third_party/externals/icu/source/data/locales/ |
| D | sd.txt | 787 "Q5",
|
| /third_party/icu/icu4c/source/data/locales/ |
| D | sd.txt | 787 "Q5",
|