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Searched refs:SHCSR (Results 1 – 17 of 17) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
Dmpu_armv8.h135 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Enable()
147 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Disable()
163 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Enable_NS()
175 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Disable_NS()
Dmpu_armv7.h196 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Enable()
208 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Disable()
Dcore_cm0.h351 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_sc000.h362 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm1.h351 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm0plus.h369 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_sc300.h388 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm3.h388 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm4.h454 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm23.h397 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_armv8mbl.h397 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm7.h469 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_armv8mml.h513 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm35p.h513 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm33.h513 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm55.h520 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_armv81mml.h520 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member