Searched refs:__OM (Results 1 – 15 of 15) sorted by relevance
246 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro440 …__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…488 …__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Regi…494 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */496 …__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU …497 …__OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC …498 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */499 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */500 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */501 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */[all …]
287 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro484 …__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…532 …__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Regi…538 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */540 …__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU …541 …__OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC …542 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */543 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */544 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */545 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */[all …]
294 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro491 …__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…539 …__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Regi…546 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */548 …__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU …549 …__OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC …550 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */551 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */552 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */553 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */[all …]
179 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro359 …__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…745 __OM union747 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */748 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */749 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */759 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */1237 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…
179 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro359 …__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…760 __OM union762 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */763 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */764 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */774 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */1254 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…
231 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro425 …__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…818 __OM union820 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */821 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */822 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */832 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */1424 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…
202 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro740 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */994 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…1095 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…1206 …__OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register…
202 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro1069 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…1170 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…1281 …__OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register…
169 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
179 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro