Home
last modified time | relevance | path

Searched refs:alu (Results 1 – 25 of 179) sorted by relevance

12345678

/third_party/mesa3d/src/gallium/drivers/r600/
Dr700_asm.c37 int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id) in r700_bytecode_alu_build() argument
39 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) | in r700_bytecode_alu_build()
40 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) | in r700_bytecode_alu_build()
41 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) | in r700_bytecode_alu_build()
42 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) | in r700_bytecode_alu_build()
43 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) | in r700_bytecode_alu_build()
44 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) | in r700_bytecode_alu_build()
45 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) | in r700_bytecode_alu_build()
46 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) | in r700_bytecode_alu_build()
47 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) | in r700_bytecode_alu_build()
[all …]
Dr600_shader.c591 struct r600_bytecode_alu alu; in evergreen_interp_alu() local
600 memset(&alu, 0, sizeof(struct r600_bytecode_alu)); in evergreen_interp_alu()
603 alu.op = ALU_OP2_INTERP_ZW; in evergreen_interp_alu()
605 alu.op = ALU_OP2_INTERP_XY; in evergreen_interp_alu()
608 alu.dst.sel = ctx->shader->input[input].gpr; in evergreen_interp_alu()
609 alu.dst.write = 1; in evergreen_interp_alu()
612 alu.dst.chan = i % 4; in evergreen_interp_alu()
614 alu.src[0].sel = gpr; in evergreen_interp_alu()
615 alu.src[0].chan = (base_chan - (i % 2)); in evergreen_interp_alu()
617 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos; in evergreen_interp_alu()
[all …]
Deg_asm.c179 struct r600_bytecode_alu alu; in egcm_load_index_reg() local
189 memset(&alu, 0, sizeof(alu)); in egcm_load_index_reg()
190 alu.op = ALU_OP1_MOVA_INT; in egcm_load_index_reg()
191 alu.src[0].sel = bc->index_reg[id]; in egcm_load_index_reg()
192 alu.src[0].chan = bc->index_reg_chan[id]; in egcm_load_index_reg()
194 alu.dst.sel = id == 0 ? CM_V_SQ_MOVA_DST_CF_IDX0 : CM_V_SQ_MOVA_DST_CF_IDX1; in egcm_load_index_reg()
196 alu.last = 1; in egcm_load_index_reg()
197 r = r600_bytecode_add_alu(bc, &alu); in egcm_load_index_reg()
204 memset(&alu, 0, sizeof(alu)); in egcm_load_index_reg()
205 alu.op = id == 0 ? ALU_OP0_SET_CF_IDX0 : ALU_OP0_SET_CF_IDX1; in egcm_load_index_reg()
[all …]
Dr600_asm.c41 static inline bool alu_writes(struct r600_bytecode_alu *alu) in alu_writes() argument
43 return alu->dst.write || alu->is_op3; in alu_writes()
46 static inline unsigned int r600_bytecode_get_num_operands(const struct r600_bytecode_alu *alu) in r600_bytecode_get_num_operands() argument
48 return r600_isa_alu(alu->op)->src_count; in r600_bytecode_get_num_operands()
58 list_inithead(&cf->alu); in r600_bytecode_cf()
67 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu); in r600_bytecode_alu() local
69 if (!alu) in r600_bytecode_alu()
71 list_inithead(&alu->list); in r600_bytecode_alu()
72 return alu; in r600_bytecode_alu()
254 static int is_alu_once_inst(struct r600_bytecode_alu *alu) in is_alu_once_inst() argument
[all …]
/third_party/mesa3d/src/compiler/nir/
Dnir_lower_flrp.c37 append_flrp_to_dead_list(struct u_vector *dead_flrp, struct nir_alu_instr *alu) in append_flrp_to_dead_list() argument
40 *tail = alu; in append_flrp_to_dead_list()
48 struct nir_alu_instr *alu) in replace_with_strict_ffma() argument
50 nir_ssa_def *const a = nir_ssa_for_alu_src(bld, alu, 0); in replace_with_strict_ffma()
51 nir_ssa_def *const b = nir_ssa_for_alu_src(bld, alu, 1); in replace_with_strict_ffma()
52 nir_ssa_def *const c = nir_ssa_for_alu_src(bld, alu, 2); in replace_with_strict_ffma()
55 nir_instr_as_alu(neg_a->parent_instr)->exact = alu->exact; in replace_with_strict_ffma()
58 nir_instr_as_alu(inner_ffma->parent_instr)->exact = alu->exact; in replace_with_strict_ffma()
61 nir_instr_as_alu(outer_ffma->parent_instr)->exact = alu->exact; in replace_with_strict_ffma()
63 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, outer_ffma); in replace_with_strict_ffma()
[all …]
Dnir_lower_bool_to_float.c46 lower_alu_instr(nir_builder *b, nir_alu_instr *alu) in lower_alu_instr() argument
48 const nir_op_info *op_info = &nir_op_infos[alu->op]; in lower_alu_instr()
50 b->cursor = nir_before_instr(&alu->instr); in lower_alu_instr()
54 switch (alu->op) { in lower_alu_instr()
62 if (alu->dest.dest.ssa.bit_size != 1) in lower_alu_instr()
67 case nir_op_b2f32: alu->op = nir_op_mov; break; in lower_alu_instr()
68 case nir_op_b2i32: alu->op = nir_op_mov; break; in lower_alu_instr()
71 rep = nir_sne(b, nir_ssa_for_alu_src(b, alu, 0), in lower_alu_instr()
74 case nir_op_b2b1: alu->op = nir_op_mov; break; in lower_alu_instr()
76 case nir_op_flt: alu->op = nir_op_slt; break; in lower_alu_instr()
[all …]
Dnir_lower_bool_to_int32.c45 lower_alu_instr(nir_alu_instr *alu) in lower_alu_instr() argument
47 const nir_op_info *op_info = &nir_op_infos[alu->op]; in lower_alu_instr()
49 assert(alu->dest.dest.is_ssa); in lower_alu_instr()
51 switch (alu->op) { in lower_alu_instr()
63 if (alu->dest.dest.ssa.bit_size != 1) in lower_alu_instr()
68 case nir_op_f2b1: alu->op = nir_op_f2b32; break; in lower_alu_instr()
69 case nir_op_i2b1: alu->op = nir_op_i2b32; break; in lower_alu_instr()
76 assert(nir_src_bit_size(alu->src[0].src) == 32); in lower_alu_instr()
77 alu->op = nir_op_mov; in lower_alu_instr()
80 case nir_op_flt: alu->op = nir_op_flt32; break; in lower_alu_instr()
[all …]
Dnir_lower_int_to_float.c37 lower_alu_instr(nir_builder *b, nir_alu_instr *alu) in lower_alu_instr() argument
39 const nir_op_info *info = &nir_op_infos[alu->op]; in lower_alu_instr()
41 bool is_bool_only = alu->dest.dest.ssa.bit_size == 1; in lower_alu_instr()
43 if (alu->src[i].src.ssa->bit_size != 1) in lower_alu_instr()
52 b->cursor = nir_before_instr(&alu->instr); in lower_alu_instr()
56 switch (alu->op) { in lower_alu_instr()
65 case nir_op_b2i32: alu->op = nir_op_b2f32; break; in lower_alu_instr()
66 case nir_op_i2f32: alu->op = nir_op_mov; break; in lower_alu_instr()
67 case nir_op_u2f32: alu->op = nir_op_mov; break; in lower_alu_instr()
68 case nir_op_f2i32: alu->op = nir_op_ftrunc; break; in lower_alu_instr()
[all …]
Dnir_lower_alu_to_scalar.c44 nir_alu_instr *alu = nir_instr_as_alu(instr); in inst_is_vector_alu() local
49 assert(alu->dest.dest.is_ssa); in inst_is_vector_alu()
50 assert(alu->src[0].src.is_ssa); in inst_is_vector_alu()
51 return alu->dest.dest.ssa.num_components > 1 || in inst_is_vector_alu()
52 nir_op_infos[alu->op].input_sizes[0] > 1; in inst_is_vector_alu()
56 nir_alu_ssa_dest_init(nir_alu_instr *alu, unsigned num_components, in nir_alu_ssa_dest_init() argument
59 nir_ssa_dest_init(&alu->instr, &alu->dest.dest, num_components, in nir_alu_ssa_dest_init()
61 alu->dest.write_mask = (1 << num_components) - 1; in nir_alu_ssa_dest_init()
65 lower_reduction(nir_alu_instr *alu, nir_op chan_op, nir_op merge_op, in lower_reduction() argument
68 unsigned num_components = nir_op_infos[alu->op].input_sizes[0]; in lower_reduction()
[all …]
Dnir_opt_intrinsics.c56 try_opt_bcsel_of_shuffle(nir_builder *b, nir_alu_instr *alu, in try_opt_bcsel_of_shuffle() argument
59 assert(alu->op == nir_op_bcsel); in try_opt_bcsel_of_shuffle()
69 if (!nir_alu_src_is_trivial_ssa(alu, 0)) in try_opt_bcsel_of_shuffle()
73 if (!nir_alu_src_is_trivial_ssa(alu, 1) || in try_opt_bcsel_of_shuffle()
74 alu->src[1].src.ssa->parent_instr->block != alu->instr.block || in try_opt_bcsel_of_shuffle()
75 !src_is_single_use_shuffle(alu->src[1].src, &data1, &index1)) in try_opt_bcsel_of_shuffle()
79 if (!nir_alu_src_is_trivial_ssa(alu, 2) || in try_opt_bcsel_of_shuffle()
80 alu->src[2].src.ssa->parent_instr->block != alu->instr.block || in try_opt_bcsel_of_shuffle()
81 !src_is_single_use_shuffle(alu->src[2].src, &data2, &index2)) in try_opt_bcsel_of_shuffle()
87 nir_ssa_def *index = nir_bcsel(b, alu->src[0].src.ssa, index1, index2); in try_opt_bcsel_of_shuffle()
[all …]
Dnir_lower_to_source_mods.c60 nir_alu_instr *alu = nir_instr_as_alu(instr); in nir_lower_to_source_mods_block() local
62 bool lower_abs = (nir_op_infos[alu->op].num_inputs < 3) || in nir_lower_to_source_mods_block()
65 for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) { in nir_lower_to_source_mods_block()
66 if (!alu->src[i].src.is_ssa) in nir_lower_to_source_mods_block()
69 if (alu->src[i].src.ssa->parent_instr->type != nir_instr_type_alu) in nir_lower_to_source_mods_block()
72 nir_alu_instr *parent = nir_instr_as_alu(alu->src[i].src.ssa->parent_instr); in nir_lower_to_source_mods_block()
77 switch (nir_alu_type_get_base_type(nir_op_infos[alu->op].input_types[i])) { in nir_lower_to_source_mods_block()
94 if (nir_src_bit_size(alu->src[i].src) == 64 && in nir_lower_to_source_mods_block()
110 nir_instr_rewrite_src(instr, &alu->src[i].src, parent->src[0].src); in nir_lower_to_source_mods_block()
114 alu_src_consume_negate(&alu->src[i]); in nir_lower_to_source_mods_block()
[all …]
Dnir_opt_undef.c77 opt_undef_vecN(nir_builder *b, nir_alu_instr *alu) in opt_undef_vecN() argument
79 if (!nir_op_is_vec(alu->op)) in opt_undef_vecN()
82 assert(alu->dest.dest.is_ssa); in opt_undef_vecN()
84 for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) { in opt_undef_vecN()
85 if (!alu->src[i].src.is_ssa || in opt_undef_vecN()
86 alu->src[i].src.ssa->parent_instr->type != nir_instr_type_ssa_undef) in opt_undef_vecN()
90 b->cursor = nir_before_instr(&alu->instr); in opt_undef_vecN()
91 nir_ssa_def *undef = nir_ssa_undef(b, alu->dest.dest.ssa.num_components, in opt_undef_vecN()
92 nir_dest_bit_size(alu->dest.dest)); in opt_undef_vecN()
93 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, undef); in opt_undef_vecN()
[all …]
/third_party/mesa3d/src/compiler/nir/tests/
Dssa_def_bits_used_tests.cpp66 nir_alu_instr *alu = nir_instr_as_alu(def->parent_instr); in build_alu_instr() local
68 if (alu == NULL) in build_alu_instr()
71 alu->dest.write_mask = 1; in build_alu_instr()
72 alu->dest.dest.ssa.num_components = 1; in build_alu_instr()
74 return alu; in build_alu_instr()
86 nir_alu_instr *alu = build_alu_instr(nir_op_iand, src0, src1); in TEST_F() local
88 ASSERT_NE((void *) 0, alu); in TEST_F()
97 alu->src[0].swizzle[0] = i; in TEST_F()
99 const uint64_t bits_used = nir_ssa_def_bits_used(alu->src[1].src.ssa); in TEST_F()
115 nir_alu_instr *alu = build_alu_instr(nir_op_ior, src0, src1); in TEST_F() local
[all …]
/third_party/mesa3d/src/gallium/drivers/lima/ir/pp/
Dlower.c89 ppir_alu_node *alu = ppir_node_to_alu(node); in ppir_lower_swap_args() local
90 assert(alu->num_src == 2); in ppir_lower_swap_args()
92 ppir_src tmp = alu->src[0]; in ppir_lower_swap_args()
93 alu->src[0] = alu->src[1]; in ppir_lower_swap_args()
94 alu->src[1] = tmp; in ppir_lower_swap_args()
146 ppir_alu_node *alu = ppir_node_to_alu(node); in ppir_lower_ddxy() local
148 alu->src[1] = alu->src[0]; in ppir_lower_ddxy()
150 alu->src[1].negate = !alu->src[1].negate; in ppir_lower_ddxy()
152 alu->src[0].negate = !alu->src[0].negate; in ppir_lower_ddxy()
156 alu->num_src = 2; in ppir_lower_ddxy()
[all …]
/third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/
Dir2_assemble.c70 switch (instr->alu.vector_opc) { in alu_swizzle()
83 if (instr->alu.write_mask & 1 << j) { in alu_swizzle()
109 if (instr->alu.write_mask & 1 << i) in alu_write_mask()
145 return instr->alu.export; in dst_to_reg()
260 bc->alu.vector_opc = instr_v->alu.vector_opc; in fill_instr()
261 bc->alu.vector_write_mask = alu_write_mask(ctx, instr_v); in fill_instr()
262 bc->alu.vector_dest = dst_to_reg(ctx, instr_v); in fill_instr()
263 bc->alu.vector_clamp = instr_v->alu.saturate; in fill_instr()
264 bc->alu.export_data = instr_v->alu.export >= 0; in fill_instr()
268 (bc->alu.vector_opc == SETEv || bc->alu.vector_opc == SETNEv || in fill_instr()
[all …]
/third_party/mesa3d/src/broadcom/qpu/
Dqpu_pack.c766 instr->alu.add.op = desc->op; in v3d_qpu_add_unpack()
772 if (instr->alu.add.op == V3D_QPU_A_FMIN) in v3d_qpu_add_unpack()
773 instr->alu.add.op = V3D_QPU_A_FMAX; in v3d_qpu_add_unpack()
774 if (instr->alu.add.op == V3D_QPU_A_FADD) in v3d_qpu_add_unpack()
775 instr->alu.add.op = V3D_QPU_A_FADDNF; in v3d_qpu_add_unpack()
781 switch (instr->alu.add.op) { in v3d_qpu_add_unpack()
787 instr->alu.add.op = V3D_QPU_A_STVPMV; in v3d_qpu_add_unpack()
790 instr->alu.add.op = V3D_QPU_A_STVPMD; in v3d_qpu_add_unpack()
793 instr->alu.add.op = V3D_QPU_A_STVPMP; in v3d_qpu_add_unpack()
803 switch (instr->alu.add.op) { in v3d_qpu_add_unpack()
[all …]
Dqpu_instr.c567 inst->alu.add.op == V3D_QPU_A_TMUWT)); in v3d_qpu_waits_on_tmu()
646 if (inst->alu.add.magic_write && in v3d_qpu_uses_tlb()
647 v3d_qpu_magic_waddr_is_tlb(inst->alu.add.waddr)) { in v3d_qpu_uses_tlb()
651 if (inst->alu.mul.magic_write && in v3d_qpu_uses_tlb()
652 v3d_qpu_magic_waddr_is_tlb(inst->alu.mul.waddr)) { in v3d_qpu_uses_tlb()
667 if (inst->alu.add.magic_write && in v3d_qpu_uses_sfu()
668 v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr)) { in v3d_qpu_uses_sfu()
672 if (inst->alu.mul.magic_write && in v3d_qpu_uses_sfu()
673 v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr)) { in v3d_qpu_uses_sfu()
685 switch (inst->alu.add.op) { in v3d_qpu_instr_is_sfu()
[all …]
/third_party/mesa3d/src/intel/compiler/
Dbrw_nir_lower_conversions.c54 split_conversion(nir_builder *b, nir_alu_instr *alu, nir_op op1, nir_op op2) in split_conversion() argument
56 b->cursor = nir_before_instr(&alu->instr); in split_conversion()
57 assert(alu->dest.write_mask == 1); in split_conversion()
58 nir_ssa_def *src = nir_ssa_for_alu_src(b, alu, 0); in split_conversion()
61 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, res); in split_conversion()
62 nir_instr_remove(&alu->instr); in split_conversion()
66 lower_alu_instr(nir_builder *b, nir_alu_instr *alu) in lower_alu_instr() argument
68 unsigned src_bit_size = nir_src_bit_size(alu->src[0].src); in lower_alu_instr()
69 nir_alu_type src_type = nir_op_infos[alu->op].input_types[0]; in lower_alu_instr()
72 unsigned dst_bit_size = nir_dest_bit_size(alu->dest.dest); in lower_alu_instr()
[all …]
/third_party/mesa3d/src/gallium/drivers/lima/ir/
Dlima_nir_split_load_input.c37 nir_alu_instr *alu = nir_instr_as_alu(instr); in lima_nir_split_load_input_instr() local
38 if (alu->op != nir_op_mov) in lima_nir_split_load_input_instr()
41 if (!alu->dest.dest.is_ssa) in lima_nir_split_load_input_instr()
44 if (!alu->src[0].src.is_ssa) in lima_nir_split_load_input_instr()
47 nir_ssa_def *ssa = alu->src[0].src.ssa; in lima_nir_split_load_input_instr()
55 uint8_t swizzle = alu->src[0].swizzle[0]; in lima_nir_split_load_input_instr()
58 for (i = 1; i < nir_dest_num_components(alu->dest.dest); i++) in lima_nir_split_load_input_instr()
59 if (alu->src[0].swizzle[i] != (swizzle + i)) in lima_nir_split_load_input_instr()
62 if (i != nir_dest_num_components(alu->dest.dest)) in lima_nir_split_load_input_instr()
66 if (nir_dest_num_components(alu->dest.dest) == 3 && swizzle > 0) in lima_nir_split_load_input_instr()
[all …]
/third_party/mesa3d/src/gallium/drivers/r300/compiler/
Dr300_fragprog.c136 int regc = code->alu.inst[i].rgb_addr >> (j * 6); in r300FragmentProgramDump()
137 int rega = code->alu.inst[i].alpha_addr >> (j * 6); in r300FragmentProgramDump()
139 code->alu.inst[i].r400_ext_addr); in r300FragmentProgramDump()
141 code->alu.inst[i].r400_ext_addr); in r300FragmentProgramDump()
151 (code->alu.inst[i]. in r300FragmentProgramDump()
153 (code->alu.inst[i]. in r300FragmentProgramDump()
155 (code->alu.inst[i]. in r300FragmentProgramDump()
160 code->alu.inst[i].r400_ext_addr); in r300FragmentProgramDump()
163 ((code->alu.inst[i]. in r300FragmentProgramDump()
169 (code->alu.inst[i]. in r300FragmentProgramDump()
[all …]
/third_party/mesa3d/src/broadcom/compiler/
Dqpu_validate.c96 if (inst->alu.add.op != V3D_QPU_A_NOP && in qpu_magic_waddr_matches()
97 inst->alu.add.magic_write && in qpu_magic_waddr_matches()
98 predicate(inst->alu.add.waddr)) in qpu_magic_waddr_matches()
101 if (inst->alu.mul.op != V3D_QPU_M_NOP && in qpu_magic_waddr_matches()
102 inst->alu.mul.magic_write && in qpu_magic_waddr_matches()
103 predicate(inst->alu.mul.waddr)) in qpu_magic_waddr_matches()
154 if (inst->alu.add.op != V3D_QPU_A_NOP) { in qpu_validate_inst()
155 if (inst->alu.add.magic_write) { in qpu_validate_inst()
157 inst->alu.add.waddr)) { in qpu_validate_inst()
160 if (v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr)) in qpu_validate_inst()
[all …]
Dvir_to_qpu.c53 .alu = { in v3d_qpu_nop()
109 if (instr->alu.add.a != V3D_QPU_MUX_A && in set_src()
110 instr->alu.add.b != V3D_QPU_MUX_A && in set_src()
111 instr->alu.mul.a != V3D_QPU_MUX_A && in set_src()
112 instr->alu.mul.b != V3D_QPU_MUX_A) { in set_src()
119 assert(!(instr->alu.add.a == V3D_QPU_MUX_B && in set_src()
120 instr->alu.add.b == V3D_QPU_MUX_B && in set_src()
121 instr->alu.mul.a == V3D_QPU_MUX_B && in set_src()
122 instr->alu.mul.b == V3D_QPU_MUX_B) || in set_src()
138 qinst->qpu.alu.mul.op != V3D_QPU_M_MOV || in is_no_op_mov()
[all …]
Dqpu_schedule.c139 if (inst->alu.add.magic_write && in qpu_inst_is_tlb()
140 (inst->alu.add.waddr == V3D_QPU_WADDR_TLB || in qpu_inst_is_tlb()
141 inst->alu.add.waddr == V3D_QPU_WADDR_TLBU)) in qpu_inst_is_tlb()
144 if (inst->alu.mul.magic_write && in qpu_inst_is_tlb()
145 (inst->alu.mul.waddr == V3D_QPU_WADDR_TLB || in qpu_inst_is_tlb()
146 inst->alu.mul.waddr == V3D_QPU_WADDR_TLBU)) in qpu_inst_is_tlb()
306 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 0) in calculate_deps()
307 process_mux_deps(state, n, inst->alu.add.a); in calculate_deps()
308 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 1) in calculate_deps()
309 process_mux_deps(state, n, inst->alu.add.b); in calculate_deps()
[all …]
/third_party/mesa3d/src/gallium/drivers/r600/sfn/
Dsfn_nir_lower_alu.cpp17 auto alu = nir_instr_as_alu(instr); in filter() local
18 switch (alu->op) { in filter()
29 nir_alu_instr *alu = nir_instr_as_alu(instr); in lower() local
31 switch (alu->op) { in lower()
33 nir_ssa_def *packed = nir_ssa_for_alu_src(b, alu, 0); in lower()
39 nir_ssa_def *src_vec2 = nir_ssa_for_alu_src(b, alu, 0); in lower()
59 auto alu = nir_instr_as_alu(instr); in filter() local
60 switch (alu->op) { in filter()
71 auto alu = nir_instr_as_alu(instr); in lower() local
73 assert(alu->op == nir_op_fsin || in lower()
[all …]
/third_party/mesa3d/src/freedreno/ir2/
Ddisasm-a2xx.c233 instr_alu_t *alu = (instr_alu_t *)dwords; in disasm_alu() local
243 printf("%s", vector_instructions[alu->vector_opc].name); in disasm_alu()
245 if (alu->pred_select & 0x2) { in disasm_alu()
249 printf((alu->pred_select & 0x1) ? "EQ" : "NE"); in disasm_alu()
254 print_dstreg(alu->vector_dest, alu->vector_write_mask, alu->export_data); in disasm_alu()
256 if (vector_instructions[alu->vector_opc].num_srcs == 3) { in disasm_alu()
257 print_srcreg(alu->src3_reg, alu->src3_sel, alu->src3_swiz, in disasm_alu()
258 alu->src3_reg_negate, alu->src3_reg_abs); in disasm_alu()
261 print_srcreg(alu->src1_reg, alu->src1_sel, alu->src1_swiz, in disasm_alu()
262 alu->src1_reg_negate, alu->src1_reg_abs); in disasm_alu()
[all …]

12345678