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Searched refs:chip_class (Results 1 – 25 of 184) sorted by relevance

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/third_party/mesa3d/src/amd/common/
Dac_debug.c70 enum chip_class chip_class; member
112 static const struct si_reg *find_register(enum chip_class chip_class, unsigned offset) in find_register() argument
117 switch (chip_class) { in find_register()
153 const char *ac_get_register_name(enum chip_class chip_class, unsigned offset) in ac_get_register_name() argument
155 const struct si_reg *reg = find_register(chip_class, offset); in ac_get_register_name()
160 void ac_dump_reg(FILE *file, enum chip_class chip_class, unsigned offset, uint32_t value, in ac_dump_reg() argument
163 const struct si_reg *reg = find_register(chip_class, offset); in ac_dump_reg()
251 ac_dump_reg(f, ib->chip_class, reg + i * 4, ac_ib_get(ib), ~0); in ac_parse_set_reg_packet()
295 ac_dump_reg(f, ib->chip_class, R_0301F0_CP_COHER_CNTL, ac_ib_get(ib), ~0); in ac_parse_packet3()
296 ac_dump_reg(f, ib->chip_class, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0); in ac_parse_packet3()
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Dac_debug.h59 const char *ac_get_register_name(enum chip_class chip_class, unsigned offset);
60 void ac_dump_reg(FILE *file, enum chip_class chip_class, unsigned offset, uint32_t value,
63 unsigned trace_id_count, enum chip_class chip_class,
66 const char *name, enum chip_class chip_class, ac_debug_addr_callback addr_callback,
69 bool ac_vm_fault_occured(enum chip_class chip_class, uint64_t *old_dmesg_timestamp,
72 unsigned ac_get_wave_info(enum chip_class chip_class,
Dac_shader_util.h86 uint32_t ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class);
88 unsigned ac_get_tbuffer_format(enum chip_class chip_class, unsigned dfmt, unsigned nfmt);
92 enum ac_image_dim ac_get_sampler_dim(enum chip_class chip_class, enum glsl_sampler_dim dim,
95 enum ac_image_dim ac_get_image_dim(enum chip_class chip_class, enum glsl_sampler_dim sdim,
110 unsigned ac_compute_lshs_workgroup_size(enum chip_class chip_class, gl_shader_stage stage,
115 unsigned ac_compute_esgs_workgroup_size(enum chip_class chip_class, unsigned wave_size,
Dac_shader_util.c88 uint32_t ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class) in ac_vgt_gs_mode() argument
104 S_028A40_ES_WRITE_OPTIMIZE(chip_class <= GFX8) | S_028A40_GS_WRITE_OPTIMIZE(1) | in ac_vgt_gs_mode()
105 S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0); in ac_vgt_gs_mode()
110 unsigned ac_get_tbuffer_format(enum chip_class chip_class, unsigned dfmt, unsigned nfmt) in ac_get_tbuffer_format() argument
117 if (chip_class >= GFX10) { in ac_get_tbuffer_format()
223 enum ac_image_dim ac_get_sampler_dim(enum chip_class chip_class, enum glsl_sampler_dim dim, in ac_get_sampler_dim() argument
228 if (chip_class == GFX9) in ac_get_sampler_dim()
250 enum ac_image_dim ac_get_image_dim(enum chip_class chip_class, enum glsl_sampler_dim sdim, in ac_get_image_dim() argument
253 enum ac_image_dim dim = ac_get_sampler_dim(chip_class, sdim, is_array); in ac_get_image_dim()
256 if (dim == ac_image_cube || (chip_class <= GFX8 && dim == ac_image_3d)) in ac_get_image_dim()
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Dac_nir.h55 enum chip_class chip_class,
82 enum chip_class chip_class,
87 enum chip_class chip_class,
92 enum chip_class chip_class);
Dac_shadowed_regs.c819 void ac_get_reg_ranges(enum chip_class chip_class, enum radeon_family family, in ac_get_reg_ranges() argument
834 if (chip_class == GFX10_3) in ac_get_reg_ranges()
836 else if (chip_class == GFX10) in ac_get_reg_ranges()
838 else if (chip_class == GFX9) in ac_get_reg_ranges()
842 if (chip_class == GFX10_3) in ac_get_reg_ranges()
844 else if (chip_class == GFX10) in ac_get_reg_ranges()
846 else if (chip_class == GFX9) in ac_get_reg_ranges()
850 if (chip_class == GFX10_3 || chip_class == GFX10) in ac_get_reg_ranges()
854 else if (chip_class == GFX9) in ac_get_reg_ranges()
858 if (chip_class == GFX10_3 || chip_class == GFX10) in ac_get_reg_ranges()
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Dac_nir_lower_esgs_io_to_mem.c45 enum chip_class chip_class; member
130 if (st->chip_class <= GFX8) { in lower_es_output_store()
196 nir_ssa_def *vertex_offset = st->chip_class >= GFX9 in gs_per_vertex_input_offset()
200 unsigned base_stride = st->chip_class >= GFX9 ? 1 : 64 /* Wave size on GFX6-8 */; in gs_per_vertex_input_offset()
215 if (st->chip_class >= GFX9) in lower_gs_per_vertex_input_load()
233 enum chip_class chip_class, in ac_nir_lower_es_outputs_to_mem() argument
237 .chip_class = chip_class, in ac_nir_lower_es_outputs_to_mem()
249 enum chip_class chip_class, in ac_nir_lower_gs_inputs_to_mem() argument
253 .chip_class = chip_class, in ac_nir_lower_gs_inputs_to_mem()
Dac_gpu_info.c315 if (info->chip_class < GFX9) in has_tmz_support()
636 info->chip_class = GFX10_3; in ac_query_gpu_info()
638 info->chip_class = GFX10; in ac_query_gpu_info()
640 info->chip_class = GFX9; in ac_query_gpu_info()
642 info->chip_class = GFX8; in ac_query_gpu_info()
644 info->chip_class = GFX7; in ac_query_gpu_info()
646 info->chip_class = GFX6; in ac_query_gpu_info()
653 info->chip_class >= GFX10_3 && in ac_query_gpu_info()
680 info->has_l2_uncached = info->chip_class >= GFX9; in ac_query_gpu_info()
712 info->kernel_flushes_tc_l2_after_ib = info->chip_class != GFX8 || info->drm_minor >= 2; in ac_query_gpu_info()
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Dac_surface_test_common.h38 info->chip_class = GFX9; in init_vega10()
53 info->chip_class = GFX9; in init_vega20()
69 info->chip_class = GFX9; in init_raven()
84 info->chip_class = GFX9; in init_raven2()
99 info->chip_class = GFX10; in init_navi10()
114 info->chip_class = GFX10; in init_navi14()
129 info->chip_class = GFX10_3; in init_sienna_cichlid()
146 info->chip_class = GFX10_3; in init_navy_flounder()
195 switch(info.chip_class) { in get_radeon_info()
Dac_shadowed_regs.h57 void ac_get_reg_ranges(enum chip_class chip_class, enum radeon_family family,
62 void ac_check_shadowed_regs(enum chip_class chip_class, enum radeon_family family,
/third_party/mesa3d/src/amd/vulkan/winsys/null/
Dradv_null_winsys.c77 info->chip_class = CLASS_UNKNOWN; in radv_null_winsys_query_info()
87 info->chip_class = GFX10_3; in radv_null_winsys_query_info()
89 info->chip_class = GFX10; in radv_null_winsys_query_info()
91 info->chip_class = GFX9; in radv_null_winsys_query_info()
93 info->chip_class = GFX8; in radv_null_winsys_query_info()
95 info->chip_class = GFX7; in radv_null_winsys_query_info()
97 info->chip_class = GFX6; in radv_null_winsys_query_info()
109 if (info->chip_class >= GFX10_3) in radv_null_winsys_query_info()
111 else if (info->chip_class >= GFX10) in radv_null_winsys_query_info()
118 if (info->chip_class >= GFX10) in radv_null_winsys_query_info()
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/third_party/mesa3d/src/amd/compiler/
Daco_assembler.cpp45 enum chip_class chip_class; member
51 asm_context(Program* program_) : program(program_), chip_class(program->chip_class) in asm_context()
53 if (chip_class <= GFX7) in asm_context()
55 else if (chip_class <= GFX9) in asm_context()
57 else if (chip_class >= GFX10) in asm_context()
124 assert(ctx.chip_class >= GFX10); in emit_instruction()
128 assert(ctx.chip_class >= GFX10); in emit_instruction()
150 if (opcode >= 55 && ctx.chip_class <= GFX9) { in emit_instruction()
151 assert(ctx.chip_class == GFX9 && opcode < 60); in emit_instruction()
186 if (ctx.chip_class <= GFX7) { in emit_instruction()
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Daco_print_asm.cpp49 to_clrx_device_name(chip_class cc, radeon_family family) in to_clrx_device_name()
112 const char* gpu_type = to_clrx_device_name(program->chip_class, program->family); in print_asm_clrx()
152 disasm_instr(chip_class chip, LLVMDisasmContextRef disasm, uint32_t* binary, unsigned exec_size, in disasm_instr()
222 if (program->chip_class >= GFX10 && program->wave_size == 64) { in print_asm_llvm()
258 std::pair<bool, size_t> res = disasm_instr(program->chip_class, disasm, binary.data(), in print_asm_llvm()
301 if (program->chip_class >= GFX8) { in check_print_asm_support()
309 return to_clrx_device_name(program->chip_class, program->family) && in check_print_asm_support()
321 if (program->chip_class >= GFX8) { in print_asm()
Daco_ir.cpp69 enum chip_class chip_class, enum radeon_family family, bool wgp_mode, in init_program() argument
75 program->chip_class = chip_class; in init_program()
77 switch (chip_class) { in init_program()
91 program->dev.lds_encoding_granule = chip_class >= GFX7 ? 512 : 256; in init_program()
93 chip_class >= GFX10_3 ? 1024 : program->dev.lds_encoding_granule; in init_program()
94 program->dev.lds_limit = chip_class >= GFX7 ? 65536 : 32768; in init_program()
102 if (chip_class >= GFX10) { in init_program()
108 if (chip_class >= GFX10_3) in init_program()
112 } else if (program->chip_class >= GFX8) { in init_program()
125 if (program->chip_class >= GFX10_3) in init_program()
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/third_party/mesa3d/src/amd/vulkan/
Dsi_cmd_buffer.c49 if (physical_device->rad_info.chip_class < GFX7) in si_write_harvested_raster_configs()
61 if (physical_device->rad_info.chip_class < GFX7) in si_write_harvested_raster_configs()
70 if (physical_device->rad_info.chip_class >= GFX7) in si_write_harvested_raster_configs()
91 if (device->physical_device->rad_info.chip_class >= GFX7) { in si_emit_compute()
106 if (device->physical_device->rad_info.chip_class >= GFX9) { in si_emit_compute()
108 device->physical_device->rad_info.chip_class >= GFX10 ? 0x20 : 0); in si_emit_compute()
111 if (device->physical_device->rad_info.chip_class >= GFX10) { in si_emit_compute()
125 if (device->physical_device->rad_info.chip_class <= GFX6) { in si_emit_compute()
140 assert(device->physical_device->rad_info.chip_class == GFX8); in si_emit_compute()
174 if (physical_device->rad_info.chip_class >= GFX7) in si_set_raster_config()
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Dradv_debug.c85 ac_vm_fault_occured(device->physical_device->rad_info.chip_class, &device->dmesg_timestamp, in radv_init_trace()
116 ac_dump_reg(f, device->physical_device->rad_info.chip_class, offset, value, ~0); in radv_dump_mmapped_reg()
134 if (info->chip_class <= GFX8) { in radv_dump_debug_registers()
153 radv_dump_buffer_descriptor(enum chip_class chip_class, const uint32_t *desc, FILE *f) in radv_dump_buffer_descriptor() argument
157 ac_dump_reg(f, chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, desc[j], 0xffffffff); in radv_dump_buffer_descriptor()
161 radv_dump_image_descriptor(enum chip_class chip_class, const uint32_t *desc, FILE *f) in radv_dump_image_descriptor() argument
164 chip_class >= GFX10 ? R_00A000_SQ_IMG_RSRC_WORD0 : R_008F10_SQ_IMG_RSRC_WORD0; in radv_dump_image_descriptor()
168 ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4, desc[j], 0xffffffff); in radv_dump_image_descriptor()
172 ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4, desc[8 + j], 0xffffffff); in radv_dump_image_descriptor()
176 radv_dump_sampler_descriptor(enum chip_class chip_class, const uint32_t *desc, FILE *f) in radv_dump_sampler_descriptor() argument
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Dradv_sqtt.c54 if (device->physical_device->rad_info.chip_class == GFX10_3) in gfx10_get_thread_trace_ctrl()
82 if (device->physical_device->rad_info.chip_class >= GFX10) { in radv_emit_thread_trace_start()
134 if (device->physical_device->rad_info.chip_class < GFX9) { in radv_emit_thread_trace_start()
153 if (device->physical_device->rad_info.chip_class == GFX9) { in radv_emit_thread_trace_start()
165 if (device->physical_device->rad_info.chip_class == GFX9) { in radv_emit_thread_trace_start()
181 device->physical_device->rad_info.chip_class >= GFX7) { in radv_emit_thread_trace_start()
213 if (device->physical_device->rad_info.chip_class >= GFX10) { in radv_copy_thread_trace_info_regs()
215 } else if (device->physical_device->rad_info.chip_class == GFX9) { in radv_copy_thread_trace_info_regs()
218 assert(device->physical_device->rad_info.chip_class == GFX8); in radv_copy_thread_trace_info_regs()
246 device->physical_device->rad_info.chip_class >= GFX7) { in radv_emit_thread_trace_stop()
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Dradv_image.c59 device->physical_device->rad_info.chip_class <= GFX8) { in radv_choose_tiling()
77 if (device->physical_device->rad_info.chip_class < GFX8) in radv_use_tc_compat_htile_for_image()
93 if (device->physical_device->rad_info.chip_class < GFX9) { in radv_use_tc_compat_htile_for_image()
117 if (device->physical_device->rad_info.chip_class >= GFX9) in radv_surface_has_scanout()
237 if (device->physical_device->rad_info.chip_class < GFX8) in radv_use_dcc_for_image_early()
254 (device->physical_device->rad_info.chip_class < GFX10 || in radv_use_dcc_for_image_early()
276 if (device->physical_device->rad_info.chip_class < GFX10) { in radv_use_dcc_for_image_early()
283 device->physical_device->rad_info.chip_class == GFX9) in radv_use_dcc_for_image_early()
324 return ac_surface_supports_dcc_image_stores(device->physical_device->rad_info.chip_class, in radv_image_use_dcc_image_stores()
353 image->info.array_size == 1 && device->physical_device->rad_info.chip_class >= GFX10; in radv_use_htile_for_image()
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/third_party/mesa3d/src/amd/compiler/tests/
Dtest_isel.cpp63 if (!set_variant((chip_class)i))
78 PipelineBuilder pbld(get_vk_device((chip_class)i));
86 if (!set_variant((chip_class)i))
103 PipelineBuilder pbld(get_vk_device((chip_class)i));
115 if (!set_variant((chip_class)i))
129 PipelineBuilder pbld(get_vk_device((chip_class)i));
141 if (!set_variant((chip_class)i))
182 PipelineBuilder pbld(get_vk_device((chip_class)i));
Dtest_assembler.cpp30 if (!setup_cs(NULL, (chip_class)i))
44 if (!setup_cs(NULL, (chip_class)GFX10))
63 if (!setup_cs(NULL, (chip_class)GFX10))
93 if (!setup_cs(NULL, (chip_class)GFX10))
126 if (!setup_cs(NULL, (chip_class)GFX10))
154 if (!setup_cs(NULL, (chip_class)GFX10))
183 if (!setup_cs(NULL, (chip_class)GFX10))
208 if (!setup_cs(NULL, (chip_class)GFX10))
235 if (!setup_cs(NULL, (chip_class)i))
253 if (!setup_cs(NULL, (chip_class)i))
Dhelpers.h73 void create_program(enum chip_class chip_class, aco::Stage stage,
75 bool setup_cs(const char *input_spec, enum chip_class chip_class,
98 VkDevice get_vk_device(enum chip_class chip_class);
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_build_pm4.h142 #define radeon_set_uconfig_reg_idx(screen, chip_class, reg, idx, value) do { \ argument
147 if ((chip_class) < GFX9 || \
148 ((chip_class) == GFX9 && (screen)->info.me_fw_version < 26)) \
284 si_get_user_data_base(enum chip_class chip_class, enum si_has_tess has_tess, in si_get_user_data_base() argument
292 if (chip_class >= GFX10) { in si_get_user_data_base()
294 } else if (chip_class == GFX9) { in si_get_user_data_base()
299 } else if (chip_class >= GFX10) { in si_get_user_data_base()
312 if (chip_class == GFX9) { in si_get_user_data_base()
321 if (chip_class >= GFX10) { in si_get_user_data_base()
337 if (chip_class == GFX9) { in si_get_user_data_base()
Dsi_debug.c300 ac_dump_reg(f, sctx->chip_class, offset, value, ~0); in si_dump_mmapped_reg()
324 if (sctx->chip_class <= GFX8) { in si_dump_debug_registers()
358 enum chip_class chip_class) in si_parse_current_ib() argument
371 trace_id_count, chip_class, NULL, NULL); in si_parse_current_ib()
387 chip_class, NULL, NULL); in si_parse_current_ib()
395 NULL, 0, "GFX", sctx->chip_class); in si_print_current_ib()
418 "IB2: Init config", ctx->chip_class, NULL, NULL); in si_log_chunk_type_cs_print()
422 "IB2: Init GS rings", ctx->chip_class, NULL, NULL); in si_log_chunk_type_cs_print()
427 &last_trace_id, map ? 1 : 0, "IB", ctx->chip_class, NULL, NULL); in si_log_chunk_type_cs_print()
430 map ? 1 : 0, "IB", ctx->chip_class); in si_log_chunk_type_cs_print()
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Dsi_pipe.c140 !sscreen->info.has_dedicated_vram && sscreen->info.chip_class <= GFX8; in si_init_compiler()
197 if (sctx->chip_class >= GFX10 && sctx->has_graphics) in si_destroy_context()
465 sctx->has_graphics = sscreen->info.chip_class == GFX6 || !(flags & PIPE_CONTEXT_COMPUTE_ONLY); in si_create_context()
482 sctx->chip_class = sscreen->info.chip_class; in si_create_context()
484 if (sctx->chip_class == GFX7 || sctx->chip_class == GFX8 || sctx->chip_class == GFX9) { in si_create_context()
559 if (sctx->chip_class >= GFX10) in si_create_context()
586 if (sctx->chip_class >= GFX10) in si_create_context()
613 switch (sctx->chip_class) { in si_create_context()
652 if (sctx->chip_class >= GFX9) { in si_create_context()
675 if (sctx->chip_class == GFX7) { in si_create_context()
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/third_party/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_winsys.c216 ws->info.chip_class = R300; in do_winsys_init()
227 ws->info.chip_class = R400; in do_winsys_init()
235 ws->info.chip_class = R500; in do_winsys_init()
245 ws->info.chip_class = R600; in do_winsys_init()
251 ws->info.chip_class = R700; in do_winsys_init()
264 ws->info.chip_class = EVERGREEN; in do_winsys_init()
268 ws->info.chip_class = CAYMAN; in do_winsys_init()
275 ws->info.chip_class = GFX6; in do_winsys_init()
281 ws->info.chip_class = GFX7; in do_winsys_init()
312 if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) { in do_winsys_init()
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