| /third_party/mesa3d/src/freedreno/vulkan/ |
| D | tu_cs.c | 30 tu_cs_init(struct tu_cs *cs, in tu_cs_init() argument
37 memset(cs, 0, sizeof(*cs)); in tu_cs_init()
39 cs->device = device; in tu_cs_init()
40 cs->mode = mode; in tu_cs_init()
41 cs->next_bo_size = initial_size; in tu_cs_init()
48 tu_cs_init_external(struct tu_cs *cs, struct tu_device *device, in tu_cs_init_external() argument
51 memset(cs, 0, sizeof(*cs)); in tu_cs_init_external()
53 cs->device = device; in tu_cs_init_external()
54 cs->mode = TU_CS_MODE_EXTERNAL; in tu_cs_init_external()
55 cs->start = cs->reserved_end = cs->cur = start; in tu_cs_init_external()
[all …]
|
| D | tu_cs.h | 33 tu_cs_init(struct tu_cs *cs,
39 tu_cs_init_external(struct tu_cs *cs, struct tu_device *device,
43 tu_cs_finish(struct tu_cs *cs);
46 tu_cs_begin(struct tu_cs *cs);
49 tu_cs_end(struct tu_cs *cs);
52 tu_cs_begin_sub_stream(struct tu_cs *cs, uint32_t size, struct tu_cs *sub_cs);
55 tu_cs_alloc(struct tu_cs *cs,
61 tu_cs_end_sub_stream(struct tu_cs *cs, struct tu_cs *sub_cs);
64 tu_cs_end_draw_state(struct tu_cs *cs, struct tu_cs *sub_cs) in tu_cs_end_draw_state() argument
66 struct tu_cs_entry entry = tu_cs_end_sub_stream(cs, sub_cs); in tu_cs_end_draw_state()
[all …]
|
| D | tu_cmd_buffer.c | 42 struct tu_cs *cs, in tu6_emit_event_write() argument
59 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1); in tu6_emit_event_write()
60 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event)); in tu6_emit_event_write()
62 tu_cs_emit_qw(cs, global_iova(cmd, seqno_dummy)); in tu6_emit_event_write()
63 tu_cs_emit(cs, 0); in tu6_emit_event_write()
69 struct tu_cs *cs, in tu6_emit_flushes() argument
87 tu6_emit_event_write(cmd_buffer, cs, PC_CCU_FLUSH_COLOR_TS); in tu6_emit_flushes()
90 tu6_emit_event_write(cmd_buffer, cs, PC_CCU_FLUSH_DEPTH_TS); in tu6_emit_flushes()
92 tu6_emit_event_write(cmd_buffer, cs, PC_CCU_INVALIDATE_COLOR); in tu6_emit_flushes()
94 tu6_emit_event_write(cmd_buffer, cs, PC_CCU_INVALIDATE_DEPTH); in tu6_emit_flushes()
[all …]
|
| D | tu_query.c | 564 struct tu_cs *cs, in copy_query_value_gpu() argument
573 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 5); in copy_query_value_gpu()
576 tu_cs_emit(cs, mem_to_mem_flags); in copy_query_value_gpu()
577 tu_cs_emit_qw(cs, write_iova); in copy_query_value_gpu()
578 tu_cs_emit_qw(cs, src_iova); in copy_query_value_gpu()
583 struct tu_cs *cs, in emit_copy_query_pool_results() argument
601 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0); in emit_copy_query_pool_results()
613 tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6); in emit_copy_query_pool_results()
614 tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) | in emit_copy_query_pool_results()
616 tu_cs_emit_qw(cs, available_iova); in emit_copy_query_pool_results()
[all …]
|
| D | tu_clear_blit.c | 65 r2d_coords(struct tu_cs *cs, in r2d_coords() argument
70 tu_cs_emit_regs(cs, in r2d_coords()
77 tu_cs_emit_regs(cs, in r2d_coords()
85 r2d_clear_value(struct tu_cs *cs, VkFormat format, const VkClearValue *val) in r2d_clear_value() argument
140 tu_cs_emit_pkt4(cs, REG_A6XX_RB_2D_SRC_SOLID_C0, 4); in r2d_clear_value()
141 tu_cs_emit_array(cs, clear_value, 4); in r2d_clear_value()
146 struct tu_cs *cs, in r2d_src() argument
155 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PS_2D_SRC_INFO, 5); in r2d_src()
156 tu_cs_emit(cs, src_info); in r2d_src()
157 tu_cs_emit(cs, iview->SP_PS_2D_SRC_SIZE); in r2d_src()
[all …]
|
| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_cs.h | 35 radeon_check_space(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, unsigned needed) in radeon_check_space() argument
37 if (cs->max_dw - cs->cdw < needed) in radeon_check_space()
38 ws->cs_grow(cs, needed); in radeon_check_space()
39 return cs->cdw + needed; in radeon_check_space()
43 radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_config_reg_seq() argument
46 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_config_reg_seq()
48 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
49 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2); in radeon_set_config_reg_seq()
53 radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg() argument
55 radeon_set_config_reg_seq(cs, reg, 1); in radeon_set_config_reg()
[all …]
|
| D | si_cmd_buffer.c | 37 struct radeon_cmdbuf *cs, unsigned raster_config, in si_write_harvested_raster_configs() argument
50 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
54 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
57 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]); in si_write_harvested_raster_configs()
62 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
66 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
71 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); in si_write_harvested_raster_configs()
75 si_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs) in si_emit_compute() argument
77 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3); in si_emit_compute()
78 radeon_emit(cs, 0); in si_emit_compute()
[all …]
|
| D | radv_sqtt.c | 61 radv_emit_thread_trace_start(struct radv_device *device, struct radeon_cmdbuf *cs, in radv_emit_thread_trace_start() argument
79 cs, R_030800_GRBM_GFX_INDEX, in radv_emit_thread_trace_start()
85 cs, R_008D04_SQ_THREAD_TRACE_BUF0_SIZE, in radv_emit_thread_trace_start()
88 radeon_set_privileged_config_reg(cs, R_008D00_SQ_THREAD_TRACE_BUF0_BASE, shifted_va); in radv_emit_thread_trace_start()
91 cs, R_008D14_SQ_THREAD_TRACE_MASK, in radv_emit_thread_trace_start()
112 radeon_set_privileged_config_reg(cs, R_008D18_SQ_THREAD_TRACE_TOKEN_MASK, in radv_emit_thread_trace_start()
116 radeon_set_privileged_config_reg(cs, R_008D1C_SQ_THREAD_TRACE_CTRL, in radv_emit_thread_trace_start()
120 radeon_set_uconfig_reg(cs, R_030CDC_SQ_THREAD_TRACE_BASE2, in radv_emit_thread_trace_start()
123 radeon_set_uconfig_reg(cs, R_030CC0_SQ_THREAD_TRACE_BASE, shifted_va); in radv_emit_thread_trace_start()
125 radeon_set_uconfig_reg(cs, R_030CC4_SQ_THREAD_TRACE_SIZE, S_030CC4_SIZE(shifted_size)); in radv_emit_thread_trace_start()
[all …]
|
| /third_party/flatbuffers/tests/FlatBuffers.Test/ |
| D | FlatBuffers.Core.Test.csproj | 9 <Compile Remove="Properties\AssemblyInfo.cs" />
23 <Compile Include="..\..\net\FlatBuffers\ByteBuffer.cs">
24 <Link>FlatBuffers\ByteBuffer.cs</Link>
26 <Compile Include="..\..\net\FlatBuffers\ByteBufferUtil.cs">
27 <Link>FlatBuffers\ByteBufferUtil.cs</Link>
29 <Compile Include="..\..\net\FlatBuffers\IFlatbufferObject.cs">
30 <Link>FlatBuffers\IFlatbufferObject.cs</Link>
32 <Compile Include="..\..\net\FlatBuffers\Offset.cs">
33 <Link>FlatBuffers\Offset.cs</Link>
35 <Compile Include="..\..\net\FlatBuffers\FlatBufferBuilder.cs">
[all …]
|
| /third_party/iptables/iptables/ |
| D | nft-ipv4.c | 31 struct iptables_command_state *cs = data; in nft_ipv4_add() local
36 if (cs->fw.ip.iniface[0] != '\0') { in nft_ipv4_add()
37 op = nft_invflags2cmp(cs->fw.ip.invflags, IPT_INV_VIA_IN); in nft_ipv4_add()
38 add_iniface(r, cs->fw.ip.iniface, op); in nft_ipv4_add()
41 if (cs->fw.ip.outiface[0] != '\0') { in nft_ipv4_add()
42 op = nft_invflags2cmp(cs->fw.ip.invflags, IPT_INV_VIA_OUT); in nft_ipv4_add()
43 add_outiface(r, cs->fw.ip.outiface, op); in nft_ipv4_add()
46 if (cs->fw.ip.proto != 0) { in nft_ipv4_add()
47 op = nft_invflags2cmp(cs->fw.ip.invflags, XT_INV_PROTO); in nft_ipv4_add()
48 add_l4proto(r, cs->fw.ip.proto, op); in nft_ipv4_add()
[all …]
|
| D | nft-ipv6.c | 30 struct iptables_command_state *cs = data; in nft_ipv6_add() local
35 if (cs->fw6.ipv6.iniface[0] != '\0') { in nft_ipv6_add()
36 op = nft_invflags2cmp(cs->fw6.ipv6.invflags, IPT_INV_VIA_IN); in nft_ipv6_add()
37 add_iniface(r, cs->fw6.ipv6.iniface, op); in nft_ipv6_add()
40 if (cs->fw6.ipv6.outiface[0] != '\0') { in nft_ipv6_add()
41 op = nft_invflags2cmp(cs->fw6.ipv6.invflags, IPT_INV_VIA_OUT); in nft_ipv6_add()
42 add_outiface(r, cs->fw6.ipv6.outiface, op); in nft_ipv6_add()
45 if (cs->fw6.ipv6.proto != 0) { in nft_ipv6_add()
46 op = nft_invflags2cmp(cs->fw6.ipv6.invflags, XT_INV_PROTO); in nft_ipv6_add()
47 add_l4proto(r, cs->fw6.ipv6.proto, op); in nft_ipv6_add()
[all …]
|
| D | xtables.c | 265 struct iptables_command_state *cs, in add_entry() argument
276 cs->fw.ip.src.s_addr = s.addr.v4[i].s_addr; in add_entry()
277 cs->fw.ip.smsk.s_addr = s.mask.v4[i].s_addr; in add_entry()
279 cs->fw.ip.dst.s_addr = d.addr.v4[j].s_addr; in add_entry()
280 cs->fw.ip.dmsk.s_addr = d.mask.v4[j].s_addr; in add_entry()
284 cs, NULL, in add_entry()
288 cs, rulenum, in add_entry()
293 memcpy(&cs->fw6.ipv6.src, in add_entry()
295 memcpy(&cs->fw6.ipv6.smsk, in add_entry()
298 memcpy(&cs->fw6.ipv6.dst, in add_entry()
[all …]
|
| D | nft-bridge.c | 27 void ebt_cs_clean(struct iptables_command_state *cs) in ebt_cs_clean() argument
31 xtables_rule_matches_free(&cs->matches); in ebt_cs_clean()
33 for (m = cs->match_list; m;) { in ebt_cs_clean()
50 if (cs->target) { in ebt_cs_clean()
51 free(cs->target->t); in ebt_cs_clean()
52 cs->target->t = NULL; in ebt_cs_clean()
54 if (cs->target == cs->target->next) { in ebt_cs_clean()
55 free(cs->target); in ebt_cs_clean()
56 cs->target = NULL; in ebt_cs_clean()
94 static int _add_action(struct nftnl_rule *r, struct iptables_command_state *cs) in _add_action() argument
[all …]
|
| /third_party/mesa3d/src/gallium/drivers/r600/ |
| D | r600_cs.h | 45 struct radeon_cmdbuf *cs, in radeon_cs_memory_below_limit() argument
48 vram += (uint64_t)cs->used_vram_kb * 1024; in radeon_cs_memory_below_limit()
49 gtt += (uint64_t)cs->used_gart_kb * 1024; in radeon_cs_memory_below_limit()
77 &ring->cs, rbo->buf, in radeon_add_to_buffer_list()
108 !radeon_cs_memory_below_limit(rctx->screen, &ring->cs, in radeon_add_to_buffer_list_check_mem()
121 struct radeon_cmdbuf *cs = &ring->cs; in r600_emit_reloc() local
126 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_reloc()
127 radeon_emit(cs, reloc); in r600_emit_reloc()
131 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_config_reg_seq() argument
134 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_config_reg_seq()
[all …]
|
| D | cayman_msaa.c | 144 static void cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples) in cayman_emit_msaa_sample_locs() argument
149 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0); in cayman_emit_msaa_sample_locs()
150 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0); in cayman_emit_msaa_sample_locs()
151 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0); in cayman_emit_msaa_sample_locs()
152 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0); in cayman_emit_msaa_sample_locs()
155 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]); in cayman_emit_msaa_sample_locs()
156 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]); in cayman_emit_msaa_sample_locs()
157 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]); in cayman_emit_msaa_sample_locs()
158 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]); in cayman_emit_msaa_sample_locs()
161 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]); in cayman_emit_msaa_sample_locs()
[all …]
|
| /third_party/ffmpeg/libavutil/ |
| D | camellia.c | 184 static void generate_round_keys(AVCAMELLIA *cs, uint64_t Kl[2], uint64_t Kr[2], uint64_t Ka[2], uin… in generate_round_keys() argument
192 cs->Kw[0] = Kl[0]; in generate_round_keys()
193 cs->Kw[1] = Kl[1]; in generate_round_keys()
194 if (cs->key_bits == 128) { in generate_round_keys()
197 cs->K[2*i] = d[0]; in generate_round_keys()
198 cs->K[2*i+1] = d[1]; in generate_round_keys()
201 cs->K[9] = d[1]; in generate_round_keys()
203 cs->Ke[0] = d[0]; in generate_round_keys()
204 cs->Ke[1] = d[1]; in generate_round_keys()
206 cs->Ke[2] = d[0]; in generate_round_keys()
[all …]
|
| D | twofish.c | 187 static uint32_t MDS_mul(AVTWOFISH *cs, uint32_t X) in MDS_mul() argument
189 …return cs->MDS1[(X) & 0xff] ^ cs->MDS2[((X) >> 8) & 0xff] ^ cs->MDS3[((X) >> 16) & 0xff] ^ cs->MDS… in MDS_mul()
192 static void precomputeMDS(AVTWOFISH *cs) in precomputeMDS() argument
198 tf_h0(y, cs->S, cs->ksize); in precomputeMDS()
199 …cs->MDS1[i] = ((uint32_t)y[0]) ^ ((uint32_t)MD1[y[0]] << 8) ^ ((uint32_t)MD2[y[0]] << 16) ^ ((uint… in precomputeMDS()
200 …cs->MDS2[i] = ((uint32_t)MD2[y[1]]) ^ ((uint32_t)MD2[y[1]] << 8) ^ ((uint32_t)MD1[y[1]] << 16) ^ (… in precomputeMDS()
201 …cs->MDS3[i] = ((uint32_t)MD1[y[2]]) ^ ((uint32_t)MD2[y[2]] << 8) ^ ((uint32_t)y[2] << 16) ^ ((uint… in precomputeMDS()
202 …cs->MDS4[i] = ((uint32_t)MD1[y[3]]) ^ ((uint32_t)y[3] << 8) ^ ((uint32_t)MD2[y[3]] << 16) ^ ((uint… in precomputeMDS()
206 static void twofish_encrypt(AVTWOFISH *cs, uint8_t *dst, const uint8_t *src) in twofish_encrypt() argument
210 P[0] = AV_RL32(src) ^ cs->K[0]; in twofish_encrypt()
[all …]
|
| /third_party/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| D | amdgpu_cs.c | 257 struct amdgpu_cs *cs = amdgpu_cs(rcs); in amdgpu_cs_get_next_fence() local
260 if (cs->noop) in amdgpu_cs_get_next_fence()
263 if (cs->next_fence) { in amdgpu_cs_get_next_fence()
264 amdgpu_fence_reference(&fence, cs->next_fence); in amdgpu_cs_get_next_fence()
268 fence = amdgpu_fence_create(cs->ctx, in amdgpu_cs_get_next_fence()
269 cs->csc->ib[IB_MAIN].ip_type, in amdgpu_cs_get_next_fence()
270 cs->csc->ib[IB_MAIN].ip_instance, in amdgpu_cs_get_next_fence()
271 cs->csc->ib[IB_MAIN].ring); in amdgpu_cs_get_next_fence()
275 amdgpu_fence_reference(&cs->next_fence, fence); in amdgpu_cs_get_next_fence()
407 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context *cs) in amdgpu_cs_has_user_fence() argument
[all …]
|
| /third_party/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_cs.c | 131 csc->cs.chunks = (uint64_t)(uintptr_t)csc->chunk_array; in radeon_init_cs_context()
182 struct radeon_drm_cs *cs; in radeon_drm_cs_create() local
184 cs = CALLOC_STRUCT(radeon_drm_cs); in radeon_drm_cs_create()
185 if (!cs) { in radeon_drm_cs_create()
188 util_queue_fence_init(&cs->flush_completed); in radeon_drm_cs_create()
190 cs->ws = ws; in radeon_drm_cs_create()
191 cs->flush_cs = flush; in radeon_drm_cs_create()
192 cs->flush_data = flush_ctx; in radeon_drm_cs_create()
194 if (!radeon_init_cs_context(&cs->csc1, cs->ws)) { in radeon_drm_cs_create()
195 FREE(cs); in radeon_drm_cs_create()
[all …]
|
| /third_party/libdrm/radeon/ |
| D | radeon_cs.h | 68 extern int radeon_cs_begin(struct radeon_cs *cs,
72 extern int radeon_cs_end(struct radeon_cs *cs,
76 extern int radeon_cs_emit(struct radeon_cs *cs);
77 extern int radeon_cs_destroy(struct radeon_cs *cs);
78 extern int radeon_cs_erase(struct radeon_cs *cs);
79 extern int radeon_cs_need_flush(struct radeon_cs *cs);
80 extern void radeon_cs_print(struct radeon_cs *cs, FILE *file);
81 extern void radeon_cs_set_limit(struct radeon_cs *cs, uint32_t domain, uint32_t limit);
82 extern void radeon_cs_space_set_flush(struct radeon_cs *cs, void (*fn)(void *), void *data);
83 extern int radeon_cs_write_reloc(struct radeon_cs *cs,
[all …]
|
| D | radeon_cs_gem.c | 74 struct drm_radeon_cs cs; member
172 static int cs_gem_write_reloc(struct radeon_cs_int *cs, in cs_gem_write_reloc() argument
179 struct cs_gem *csg = (struct cs_gem*)cs; in cs_gem_write_reloc()
201 if ((atomic_read((atomic_t *)radeon_gem_get_reloc_in_cs(bo)) & cs->id)) { in cs_gem_write_reloc()
205 for(i = cs->crelocs; i != 0;) { in cs_gem_write_reloc()
234 radeon_cs_write_dword((struct radeon_cs *)cs, 0xc0001000); in cs_gem_write_reloc()
235 radeon_cs_write_dword((struct radeon_cs *)cs, idx); in cs_gem_write_reloc()
255 cs->relocs = csg->relocs = tmp; in cs_gem_write_reloc()
269 atomic_add((atomic_t *)radeon_gem_get_reloc_in_cs(bo), cs->id); in cs_gem_write_reloc()
270 cs->relocs_total_size += boi->size; in cs_gem_write_reloc()
[all …]
|
| /third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| D | radv_amdgpu_cs.c | 155 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(rcs); in radv_amdgpu_cs_destroy() local
157 if (cs->ib_buffer) in radv_amdgpu_cs_destroy()
158 cs->ws->base.buffer_destroy(&cs->ws->base, cs->ib_buffer); in radv_amdgpu_cs_destroy()
160 free(cs->base.buf); in radv_amdgpu_cs_destroy()
162 for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i) in radv_amdgpu_cs_destroy()
163 cs->ws->base.buffer_destroy(&cs->ws->base, cs->old_ib_buffers[i].bo); in radv_amdgpu_cs_destroy()
165 for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) { in radv_amdgpu_cs_destroy()
166 free(cs->old_cs_buffers[i].buf); in radv_amdgpu_cs_destroy()
169 free(cs->old_cs_buffers); in radv_amdgpu_cs_destroy()
170 free(cs->old_ib_buffers); in radv_amdgpu_cs_destroy()
[all …]
|
| /third_party/boost/libs/test/test/utils-ts/ |
| D | algorithm-test.cpp | 73 const_string cs( "test_string" ); in BOOST_AUTO_TEST_CASE() local
76 …ST_SURROUND_EXPRESSION(utu::find_first_not_of( cs.begin(), cs.end(), another.begin(), another.end(… in BOOST_AUTO_TEST_CASE()
80 …_EXPRESSION(utu::find_first_not_of( cs.begin(), cs.end(), another.begin(), another.end(), REF_FUN(… in BOOST_AUTO_TEST_CASE()
83 …BOOST_TEST( utu::find_last_not_of( cs.begin(), cs.end(), another.begin(), another.end() ) == cs.en… in BOOST_AUTO_TEST_CASE()
90 const_string cs( "test_string" ); in BOOST_AUTO_TEST_CASE() local
93 …T( TEST_SURROUND_EXPRESSION(utu::find_last_of( cs.begin(), cs.end(), another.begin(), another.end(… in BOOST_AUTO_TEST_CASE()
96 …ROUND_EXPRESSION(utu::find_last_of( cs.begin(), cs.end(), another.begin(), another.end(), REF_FUN(… in BOOST_AUTO_TEST_CASE()
99 …BOOST_TEST( utu::find_last_of( cs.begin(), cs.end(), another.begin(), another.end() ) == cs.end() … in BOOST_AUTO_TEST_CASE()
101 cs = "qerty"; in BOOST_AUTO_TEST_CASE()
102 …T( TEST_SURROUND_EXPRESSION(utu::find_last_of( cs.begin(), cs.end(), another.begin(), another.end(… in BOOST_AUTO_TEST_CASE()
[all …]
|
| /third_party/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_state.c | 54 struct compiled_stencil_ref *cs = &ctx->stencil_ref; in etna_set_stencil_ref() local
59 cs->PE_STENCIL_CONFIG[i] = in etna_set_stencil_ref()
61 cs->PE_STENCIL_CONFIG_EXT[i] = in etna_set_stencil_ref()
135 struct compiled_framebuffer_state *cs = &ctx->framebuffer; in etna_set_framebuffer_state() local
154 cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT_EXT(fmt) | in etna_set_framebuffer_state()
157 cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT(fmt); in etna_set_framebuffer_state()
159 cs->PE_COLOR_FORMAT |= in etna_set_framebuffer_state()
180 cs->PE_COLOR_ADDR = cbuf->reloc[0]; in etna_set_framebuffer_state()
181 cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; in etna_set_framebuffer_state()
186 cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i]; in etna_set_framebuffer_state()
[all …]
|
| /third_party/boost/libs/geometry/test/core/ |
| D | coordinate_system.cpp | 27 BOOST_GEOMETRY_REGISTER_C_ARRAY_CS(cs::cartesian)
28 BOOST_GEOMETRY_REGISTER_BOOST_TUPLE_CS(cs::cartesian) in BOOST_GEOMETRY_REGISTER_BOOST_TUPLE_CS()
60 test_geometry<int[2], bg::cs::cartesian>(); in test_main()
61 test_geometry<float[2], bg::cs::cartesian>(); in test_main()
62 test_geometry<double[2], bg::cs::cartesian>(); in test_main()
64 test_geometry<int[3], bg::cs::cartesian>(); in test_main()
65 test_geometry<float[3], bg::cs::cartesian>(); in test_main()
66 test_geometry<double[3], bg::cs::cartesian>(); in test_main()
69 test_geometry<boost::tuple<double, double>, bg::cs::cartesian>(); in test_main()
70 test_geometry<boost::tuple<double, double, double>, bg::cs::cartesian>(); in test_main()
[all …]
|