Home
last modified time | relevance | path

Searched refs:gfx_cs (Results 1 – 25 of 25) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_cp_dma.c160 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(dst), RADEON_USAGE_WRITE, in si_cp_dma_prepare()
163 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(src), RADEON_USAGE_READ, in si_cp_dma_prepare()
170 sctx->emit_cache_flush(sctx, &sctx->gfx_cs); in si_cp_dma_prepare()
271 si_emit_cp_dma(sctx, &sctx->gfx_cs, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags, cache_policy); in si_cp_dma_realign_engine()
334 if (secure != sctx->ws->cs_is_secure(&sctx->gfx_cs)) { in si_cp_dma_copy_buffer()
360 si_emit_cp_dma(sctx, &sctx->gfx_cs, main_dst_offset, main_src_offset, byte_count, dma_flags, in si_cp_dma_copy_buffer()
375 si_emit_cp_dma(sctx, &sctx->gfx_cs, dst_offset, src_offset, skipped_size, dma_flags, in si_cp_dma_copy_buffer()
420 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_cp_dma_prefetch()
441 si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, src, 0, 4, 0xabcdef01, SI_OP_SYNC_BEFORE_AFTER, in si_test_gds()
443 si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, src, 4, 4, 0x23456789, SI_OP_SYNC_BEFORE_AFTER, in si_test_gds()
[all …]
Dsi_fence.c91 struct si_resource *scratch = unlikely(ctx->ws->cs_is_secure(&ctx->gfx_cs)) ? in si_cp_release_mem()
100 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, scratch, RADEON_USAGE_WRITE, in si_cp_release_mem()
129 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, scratch, RADEON_USAGE_WRITE, in si_cp_release_mem()
144 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, buf, RADEON_USAGE_WRITE, RADEON_PRIO_QUERY); in si_cp_release_mem()
176 ws->cs_add_fence_dependency(&sctx->gfx_cs, fence, 0); in si_add_fence_dependency()
181 sctx->ws->cs_add_syncobj_signal(&sctx->gfx_cs, fence); in si_add_syncobj_signal()
257 … radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, fine->buf, RADEON_USAGE_WRITE, RADEON_PRIO_QUERY); in si_fine_fence_set()
258 si_cp_release_mem(ctx, &ctx->gfx_cs, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, in si_fine_fence_set()
468 if (!radeon_emitted(&sctx->gfx_cs, sctx->initial_gfx_cs_size)) { in si_flush_all_queues()
472 ws->cs_sync_flush(&sctx->gfx_cs); in si_flush_all_queues()
[all …]
Dsi_gfx_cs.c36 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in si_flush_gfx_cs()
116 si_cp_dma_wait_for_idle(ctx, &ctx->gfx_cs); in si_flush_gfx_cs()
121 ctx->emit_cache_flush(ctx, &ctx->gfx_cs); in si_flush_gfx_cs()
163 si_handle_thread_trace(ctx, &ctx->gfx_cs); in si_flush_gfx_cs()
198 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->current_saved_cs->trace_buf, in si_begin_gfx_cs_debug()
205 sctx->ws->cs_add_buffer(&sctx->gfx_cs, sctx->gds, RADEON_USAGE_READWRITE, 0, 0); in si_add_gds_to_buffer_list()
207 sctx->ws->cs_add_buffer(&sctx->gfx_cs, sctx->gds_oa, RADEON_USAGE_READWRITE, 0, 0); in si_add_gds_to_buffer_list()
322 if (secure != sctx->ws->cs_is_secure(&sctx->gfx_cs)) { in si_tmz_preamble()
357 is_secure = ctx->ws->cs_is_secure(&ctx->gfx_cs); in si_begin_new_gfx_cs()
389 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->border_color_buffer, in si_begin_new_gfx_cs()
[all …]
Dsi_state_streamout.c211 sctx->emit_cache_flush(sctx, &sctx->gfx_cs); in si_set_streamout_targets()
217 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in gfx10_emit_streamout_begin()
237 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size, RADEON_USAGE_READ, in gfx10_emit_streamout_begin()
267 si_cp_release_mem(sctx, &sctx->gfx_cs, V_028A90_PS_DONE, 0, EOP_DST_SEL_TC_L2, in gfx10_emit_streamout_end()
279 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_flush_vgt_streamout()
308 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_streamout_begin()
342 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size, RADEON_USAGE_READ, in si_emit_streamout_begin()
367 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_streamout_end()
389 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size, RADEON_USAGE_WRITE, in si_emit_streamout_end()
416 radeon_begin(&sctx->gfx_cs); in si_emit_streamout_enable()
Dsi_compute.c403 if (cs != &sctx->gfx_cs || !sctx->screen->info.has_graphics) { in si_emit_initial_compute_regs()
423 (cs != &sctx->gfx_cs || !sctx->screen->info.has_graphics)) { in si_emit_initial_compute_regs()
479 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_switch_compute_shader()
526 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, shader->scratch_bo, RADEON_USAGE_READWRITE, in si_switch_compute_shader()
537 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, shader->bo, RADEON_USAGE_READ, in si_switch_compute_shader()
571 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in setup_scratch_rsrc_user_sgprs()
610 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_setup_user_sgprs_co_v2()
657 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, dispatch_buf, RADEON_USAGE_READ, in si_setup_user_sgprs_co_v2()
714 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, input_buffer, RADEON_USAGE_READ, in si_upload_compute_input()
726 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_setup_nir_user_data()
[all …]
Dsi_cp_reg_shadowing.c168 si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, &sctx->shadowed_regs->b.b, in si_init_cp_reg_shadowing()
177 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->shadowed_regs, in si_init_cp_reg_shadowing()
180 ac_emulate_clear_state(&sctx->screen->info, &sctx->gfx_cs, si_set_context_reg_array); in si_init_cp_reg_shadowing()
192 sctx->ws->cs_setup_preemption(&sctx->gfx_cs, shadowing_preamble->pm4, in si_init_cp_reg_shadowing()
Dsi_perfcounter.c63 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_instance()
90 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_shaders()
103 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_select()
129 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_start()
131 si_cp_copy_data(sctx, &sctx->gfx_cs, COPY_DATA_DST_MEM, buffer, va - buffer->gpu_address, in si_pc_emit_start()
148 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_stop()
169 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_read()
225 radeon_begin(&sctx->gfx_cs); in si_inhibit_clockgating()
253 si_inhibit_clockgating(sctx, &sctx->gfx_cs, true); in si_pc_query_resume()
307 si_inhibit_clockgating(sctx, &sctx->gfx_cs, false); in si_pc_query_suspend()
Dsi_state_viewport.c104 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->small_prim_cull_info_buf, in si_emit_cull_state()
106 radeon_begin(&sctx->gfx_cs); in si_emit_cull_state()
359 radeon_begin(&ctx->gfx_cs); in si_emit_guardband()
376 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in si_emit_scissors()
472 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in si_emit_one_viewport()
486 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in si_emit_viewports()
523 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in si_emit_depth_ranges()
614 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_window_rectangles()
Dsi_pm4.c118 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pm4_emit()
121 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, ((struct si_shader*)state)->bo, in si_pm4_emit()
Dsi_state_draw.cpp102 radeon_begin(&sctx->gfx_cs); in si_emit_spi_map()
678 uint64_t ring_va = (unlikely(sctx->ws->cs_is_secure(&sctx->gfx_cs)) ? in si_emit_derived_tess_state()
710 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_derived_tess_state()
1059 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_rasterizer_prim_state()
1123 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_vs_state()
1169 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_ia_multi_vgt_param()
1235 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in gfx10_emit_ge_cntl()
1252 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_draw_registers()
1299 radeon_begin(&sctx->gfx_cs); \
1318 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_draw_packets()
[all …]
Dsi_test_dma_perf.c175 sctx->emit_cache_flush(sctx, &sctx->gfx_cs); in si_test_dma_perf()
188 si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, dst, 0, size, clear_value, in si_test_dma_perf()
239 sctx->emit_cache_flush(sctx, &sctx->gfx_cs); in si_test_dma_perf()
Dsi_buffer.c36 return sctx->ws->cs_is_buffer_referenced(&sctx->gfx_cs, buf, usage); in si_cs_is_buffer_referenced()
42 return sctx->ws->buffer_map(sctx->ws, resource->buf, &sctx->gfx_cs, usage); in si_buffer_map()
709 if (radeon_emitted(&ctx->gfx_cs, ctx->initial_gfx_cs_size) && in si_resource_commit()
710 ctx->ws->cs_is_buffer_referenced(&ctx->gfx_cs, res->buf, RADEON_USAGE_READWRITE)) { in si_resource_commit()
713 ctx->ws->cs_sync_flush(&ctx->gfx_cs); in si_resource_commit()
Dsi_debug.c394 si_parse_current_ib(f, &sctx->gfx_cs, 0, sctx->gfx_cs.prev_dw + sctx->gfx_cs.current.cdw, in si_print_current_ib()
429 si_parse_current_ib(f, &ctx->gfx_cs, chunk->gfx_begin, chunk->gfx_end, &last_trace_id, in si_log_chunk_type_cs_print()
452 unsigned gfx_cur = ctx->gfx_cs.prev_dw + ctx->gfx_cs.current.cdw; in si_log_cs()
Dsi_state_binning.c407 radeon_begin(&sctx->gfx_cs); in si_emit_dpbb_disable()
505 radeon_begin(&sctx->gfx_cs); in si_emit_dpbb_state()
Dsi_query.c771 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_query_hw_do_emit_start()
811 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, query->buffer.buf, RADEON_USAGE_WRITE, in si_query_hw_do_emit_start()
837 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_query_hw_do_emit_stop()
892 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, query->buffer.buf, RADEON_USAGE_WRITE, in si_query_hw_do_emit_stop()
934 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in emit_set_predicate()
950 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, buf, RADEON_USAGE_READ, RADEON_PRIO_QUERY); in emit_set_predicate()
1554 si_cp_wait_mem(sctx, &sctx->gfx_cs, va, 0x80000000, 0x80000000, WAIT_REG_MEM_EQUAL); in si_query_hw_get_result_resource()
Dsi_pipe.c304 sctx->ws->cs_destroy(&sctx->gfx_cs); in si_destroy_context()
398 si_write_user_event(sctx, &sctx->gfx_cs, UserEventTrigger, string, len); in si_emit_string_marker()
501 ws->cs_create(&sctx->gfx_cs, sctx->ctx, sctx->has_graphics ? RING_GFX : RING_COMPUTE, in si_create_context()
733 assert(sctx->gfx_cs.current.cdw == 0); in si_create_context()
757 assert(sctx->gfx_cs.current.cdw == sctx->initial_gfx_cs_size); in si_create_context()
809 sctx->initial_gfx_cs_size = sctx->gfx_cs.current.cdw; in si_create_context()
Dsi_state_shaders.c610 radeon_begin(&sctx->gfx_cs); in si_emit_shader_es()
771 radeon_begin(&sctx->gfx_cs); in si_emit_shader_gs()
824 radeon_begin_again(&sctx->gfx_cs); in si_emit_shader_gs()
1003 radeon_begin(&sctx->gfx_cs); in gfx10_emit_shader_ngg_tail()
1031 radeon_begin_again(&sctx->gfx_cs); in gfx10_emit_shader_ngg_tail()
1058 radeon_begin(&sctx->gfx_cs); in gfx10_emit_shader_ngg_tess_nogs()
1072 radeon_begin(&sctx->gfx_cs); in gfx10_emit_shader_ngg_notess_gs()
1087 radeon_begin(&sctx->gfx_cs); in gfx10_emit_shader_ngg_tess_gs()
1354 radeon_begin(&sctx->gfx_cs); in si_emit_shader_vs()
1397 radeon_begin_again(&sctx->gfx_cs); in si_emit_shader_vs()
[all …]
Dsi_descriptors.c166 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, desc->buffer, RADEON_USAGE_READ, in si_upload_descriptors()
185 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, desc->buffer, RADEON_USAGE_READ, in si_add_descriptors_to_bo_list()
966 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READ, in si_update_ps_colorbuf0_slot()
1080 sctx, &sctx->gfx_cs, si_resource(buffers->buffers[i]), in si_buffer_resources_begin_new_cs()
1137 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, in si_vertex_buffers_begin_new_cs()
1144 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->vb_descriptors_buffer, RADEON_USAGE_READ, in si_vertex_buffers_begin_new_cs()
1482 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(buffer), RADEON_USAGE_READWRITE, in si_set_ring_buffer()
1821 sctx->emit_cache_flush(sctx, &sctx->gfx_cs); in si_upload_bindless_descriptors()
2077 radeon_begin(&sctx->gfx_cs); in si_emit_global_shader_pointers()
2119 radeon_begin(&sctx->gfx_cs); in si_emit_graphics_shader_pointers()
[all …]
Dgfx10_query.c179 si_cp_release_mem(sctx, &sctx->gfx_cs, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, in gfx10_sh_query_end()
402 si_cp_wait_mem(sctx, &sctx->gfx_cs, va, 0x00000001, 0x00000001, 0); in gfx10_sh_query_get_result_resource()
Dsi_pipe.h905 struct radeon_cmdbuf gfx_cs; /* compute IB if graphics is disabled */ member
1892 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in si_need_gfx_cs_space()
1901 if (radeon_cs_memory_below_limit(ctx->screen, &ctx->gfx_cs, kb) && in si_need_gfx_cs_space()
1949 …!radeon_cs_memory_below_limit(sctx->screen, &sctx->gfx_cs, sctx->memory_usage_kb + bo->memory_usag… in radeon_add_to_gfx_buffer_list_check_mem()
1952 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, bo, usage, priority); in radeon_add_to_gfx_buffer_list_check_mem()
Dsi_state.c73 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_cb_render_state()
787 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_blend_color()
821 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_clip_state()
855 radeon_begin(&sctx->gfx_cs); in si_emit_clip_regs()
1176 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_stencil_ref()
1493 radeon_begin(&sctx->gfx_cs); in si_emit_db_render_state()
3040 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_framebuffer_state()
3066 … sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE | RADEON_USAGE_NEEDS_IMPLICIT_SYNC, in si_emit_framebuffer_state()
3070 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, tex->cmask_buffer, in si_emit_framebuffer_state()
3276 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE, in si_emit_framebuffer_state()
[all …]
Dsi_sqtt.c1057 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_sqtt_describe_pipeline_bind()
Dsi_compute_blit.c358 si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, dst, offset, aligned_size, *clear_value, in si_clear_buffer()
/third_party/mesa3d/docs/relnotes/
D21.0.0.rst2199 - radeonsi: initialize ctx and gfx_cs first, then allocators
D21.3.0.rst2613 - radeonsi: correctly use cs instead of gfx_cs in build pm4 helpers