| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_cp_reg_shadowing.c | 30 static void si_build_load_reg(struct si_screen *sscreen, struct si_pm4_state *pm4, in si_build_load_reg() argument
59 si_pm4_cmd_add(pm4, PKT3(packet, 1 + num_ranges * 2, 0)); in si_build_load_reg()
60 si_pm4_cmd_add(pm4, gpu_address); in si_build_load_reg()
61 si_pm4_cmd_add(pm4, gpu_address >> 32); in si_build_load_reg()
63 si_pm4_cmd_add(pm4, (ranges[i].offset - offset) / 4); in si_build_load_reg()
64 si_pm4_cmd_add(pm4, ranges[i].size / 4); in si_build_load_reg()
71 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); in si_create_shadowing_ib_preamble() local
74 si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_create_shadowing_ib_preamble()
75 si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0)); in si_create_shadowing_ib_preamble()
79 si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_create_shadowing_ib_preamble()
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| D | si_state.c | 438 struct si_pm4_state *pm4 = &blend->pm4; in si_create_blend_state_mode() local
470 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, in si_create_blend_state_mode()
476 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, in si_create_blend_state_mode()
512 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
522 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
532 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
588 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
624 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4, sx_mrt_blend_opt[i]); in si_create_blend_state_mode()
631 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control); in si_create_blend_state_mode()
915 struct si_pm4_state *pm4 = &rs->pm4; in si_create_rs_state() local
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| D | si_pm4.c | 40 state->pm4[state->ndw++] = dw; in si_pm4_cmd_add()
48 state->pm4[state->last_pm4] = PKT3(state->last_opcode, count, predicate); in si_pm4_cmd_end()
84 state->pm4[state->ndw++] = reg; in si_pm4_set_reg()
88 state->pm4[state->ndw++] = val; in si_pm4_set_reg()
126 radeon_emit_array(state->pm4, state->ndw); in si_pm4_emit()
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| D | si_state_shaders.c | 473 si_pm4_clear_state(&shader->pm4); in si_get_shader_pm4_state()
474 shader->pm4.is_shader = true; in si_get_shader_pm4_state()
475 return &shader->pm4; in si_get_shader_pm4_state()
530 struct si_pm4_state *pm4; in si_shader_ls() local
535 pm4 = si_get_shader_pm4_state(shader); in si_shader_ls()
536 if (!pm4) in si_shader_ls()
540 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8); in si_shader_ls()
553 struct si_pm4_state *pm4; in si_shader_hs() local
556 pm4 = si_get_shader_pm4_state(shader); in si_shader_hs()
557 if (!pm4) in si_shader_hs()
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| D | si_pm4.h | 54 uint32_t pm4[SI_PM4_MAX_DW]; member
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| D | si_state.h | 54 struct si_pm4_state pm4; member
72 struct si_pm4_state pm4; member
125 struct si_pm4_state pm4; member
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| D | si_shader.h | 766 struct si_pm4_state pm4; /* base class */ member
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| D | si_debug.c | 417 ac_parse_ib(f, ctx->cs_preamble_state->pm4, ctx->cs_preamble_state->ndw, NULL, 0, in si_log_chunk_type_cs_print()
421 ac_parse_ib(f, ctx->cs_preamble_gs_rings->pm4, ctx->cs_preamble_gs_rings->ndw, NULL, 0, in si_log_chunk_type_cs_print()
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| D | si_state_draw.cpp | 239 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index]; in si_update_shaders() local
240 if (unlikely(!*pm4)) in si_update_shaders()
241 *pm4 = si_build_vgt_shader_config(sctx->screen, key); in si_update_shaders()
242 si_pm4_bind_state(sctx, vgt_shader_config, *pm4); in si_update_shaders()
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| /third_party/ltp/testcases/kernel/mem/mem/ |
| D | mem02.c | 77 char *pm1, *pm2, *pm3, *pm4; in main() local
159 pm4 = pm3 = malloc(10); in main()
161 *pm4++ = 'X'; in main()
164 pm4 = realloc(pm3, 5); in main()
165 pm3 = pm4; in main()
168 if (*pm4++ != 'X') { in main()
177 pm4 = realloc(pm3, 15); in main()
178 pm3 = pm4; in main()
188 free(pm4); in main()
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| /third_party/libdrm/tests/amdgpu/ |
| D | basic_tests.c | 830 uint32_t *pm4; in amdgpu_bo_eviction_test() local
840 pm4 = calloc(pm4_dw, sizeof(*pm4)); in amdgpu_bo_eviction_test()
841 CU_ASSERT_NOT_EQUAL(pm4, NULL); in amdgpu_bo_eviction_test()
916 pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, 0, 0, 0, in amdgpu_bo_eviction_test()
918 pm4[i++] = 0xffffffff & bo2_mc; in amdgpu_bo_eviction_test()
919 pm4[i++] = 0xffffffff & bo1_mc; in amdgpu_bo_eviction_test()
920 pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; in amdgpu_bo_eviction_test()
921 pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; in amdgpu_bo_eviction_test()
923 pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); in amdgpu_bo_eviction_test()
925 pm4[i++] = sdma_write_length - 1; in amdgpu_bo_eviction_test()
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| /third_party/mesa3d/src/freedreno/registers/adreno/ |
| D | meson.build | 66 'adreno-pm4-pack.xml.h',
68 output: 'adreno-pm4-pack.xml.h',
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| /third_party/mesa3d/src/freedreno/vulkan/ |
| D | msm_kgsl.h | 373 unsigned int pm4; member
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| /third_party/mesa3d/docs/relnotes/ |
| D | 21.3.0.rst | 2613 - radeonsi: correctly use cs instead of gfx_cs in build pm4 helpers
2675 - radeonsi: unset SI_PREFETCH_* only when we unbind pm4 shader states
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| D | 20.2.0.rst | 3447 - freedreno: android: add adreno-pm4-pack.xml.h generation to android build
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| D | 21.2.0.rst | 4559 - freedreno/tu+drm: Extract out pm4 pkt header helpers
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