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Searched refs:si_resource (Results 1 – 25 of 27) sorted by relevance

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/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_buffer.c39 void *si_buffer_map(struct si_context *sctx, struct si_resource *resource, in si_buffer_map()
45 void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, uint64_t size, in si_init_resource_fields()
165 bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res) in si_alloc_resource()
215 struct si_resource *buffer = si_resource(buf); in si_resource_destroy()
229 struct si_resource *resource = &tex->buffer; in si_resource_destroy()
247 static bool si_invalidate_buffer(struct si_context *sctx, struct si_resource *buf) in si_invalidate_buffer()
282 struct si_resource *sdst = si_resource(dst); in si_replace_buffer_storage()
283 struct si_resource *ssrc = si_resource(src); in si_replace_buffer_storage()
303 struct si_resource *buf = si_resource(resource); in si_invalidate_resource()
313 struct si_resource *staging, unsigned offset) in si_buffer_get_transfer()
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Dsi_cp_dma.c160 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(dst), RADEON_USAGE_WRITE, in si_cp_dma_prepare()
163 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(src), RADEON_USAGE_READ, in si_cp_dma_prepare()
193 struct si_resource *sdst = si_resource(dst); in si_cp_dma_clear_buffer()
299 util_range_add(dst, &si_resource(dst)->valid_buffer_range, dst_offset, dst_offset + size); in si_cp_dma_copy_buffer()
302 dst_offset += si_resource(dst)->gpu_address; in si_cp_dma_copy_buffer()
305 src_offset += si_resource(src)->gpu_address; in si_cp_dma_copy_buffer()
332 bool secure = src && (si_resource(src)->flags & RADEON_FLAG_ENCRYPTED); in si_cp_dma_copy_buffer()
333 assert(!secure || (!dst || (si_resource(dst)->flags & RADEON_FLAG_ENCRYPTED))); in si_cp_dma_copy_buffer()
385 si_resource(dst)->TC_L2_dirty = true; in si_cp_dma_copy_buffer()
395 uint64_t address = si_resource(buf)->gpu_address + offset; in si_cp_dma_prefetch()
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Dsi_query.h41 struct si_resource;
168 void (*emit_start)(struct si_context *, struct si_query_hw *, struct si_resource *buffer,
170 void (*emit_stop)(struct si_context *, struct si_query_hw *, struct si_resource *buffer,
179 struct si_resource *buf;
209 struct si_resource *workaround_buf;
233 struct si_resource *buf;
Dsi_pipe.h283 struct si_resource { struct
331 struct si_resource *staging; argument
335 struct si_resource buffer;
349 struct si_resource *cmask_buffer;
770 struct si_resource *buf_filled_size;
865 struct si_resource *trace_buf;
908 struct si_resource *eop_bug_scratch;
909 struct si_resource *eop_bug_scratch_tmz;
919 struct si_resource *shadowed_regs;
954 struct si_resource *wait_mem_scratch;
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Dsi_descriptors.c191 static inline enum radeon_bo_priority si_get_sampler_view_priority(struct si_resource *res) in si_get_sampler_view_priority()
260 struct si_resource *res = si_resource(sview->base.texture); in si_sampler_views_check_encrypted()
268 static void si_set_buf_desc_address(struct si_resource *buf, uint64_t offset, uint32_t *state) in si_set_buf_desc_address()
719 struct si_resource *res = si_resource(view->resource); in si_mark_image_range_valid()
732 struct si_resource *res; in si_set_shader_image_desc()
734 res = si_resource(view->resource); in si_set_shader_image_desc()
804 struct si_resource *res; in si_set_shader_image()
811 res = si_resource(view->resource); in si_set_shader_image()
1080 sctx, &sctx->gfx_cs, si_resource(buffers->buffers[i]), in si_buffer_resources_begin_new_cs()
1094 if (si_resource(buffers->buffers[i])->flags & RADEON_FLAG_ENCRYPTED) in si_buffer_resources_check_encrypted()
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Dsi_compute.c359 va = si_resource(resources[i])->gpu_address; in si_set_global_binding()
631 struct si_resource *dispatch_buf = NULL; in si_setup_user_sgprs_co_v2()
692 struct si_resource *input_buffer = NULL; in si_upload_compute_input()
741 COPY_DATA_SRC_MEM, si_resource(info->indirect), in si_setup_nir_user_data()
824 uint64_t base_va = si_resource(info->indirect)->gpu_address; in si_emit_dispatch_packets()
826 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(info->indirect), RADEON_USAGE_READ, in si_emit_dispatch_packets()
874 struct si_resource *res = si_resource(sview->base.texture); in si_check_needs_implicit_sync()
887 struct si_resource *res = si_resource(sview->resource); in si_check_needs_implicit_sync()
933 if (sctx->chip_class <= GFX8 && si_resource(info->indirect)->TC_L2_dirty) { in si_launch_grid()
935 si_resource(info->indirect)->TC_L2_dirty = false; in si_launch_grid()
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Dsi_state_streamout.c43 struct si_resource *buf = si_resource(buffer); in si_create_so_target()
99 si_resource(sctx->streamout.targets[i]->b.buffer)->TC_L2_dirty = true; in si_set_streamout_targets()
202 si_resource(targets[i]->buffer)->bind_history |= PIPE_BIND_STREAM_OUTPUT; in si_set_streamout_targets()
Dsi_fence.c35 struct si_resource *buf;
69 struct si_resource *buf, uint64_t va, uint32_t new_fence, in si_cp_release_mem()
91 struct si_resource *scratch = unlikely(ctx->ws->cs_is_secure(&ctx->gfx_cs)) ? in si_cp_release_mem()
115 struct si_resource *scratch = ctx->eop_bug_scratch; in si_cp_release_mem()
Dsi_state_draw.cpp679 si_resource(sctx->tess_rings_tmz) : si_resource(sctx->tess_rings))->gpu_address; in si_emit_derived_tess_state()
1387 index_va = si_resource(indexbuf)->gpu_address + index_offset; in si_emit_draw_packets()
1389 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(indexbuf), RADEON_USAGE_READ, in si_emit_draw_packets()
1404 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address; in si_emit_draw_packets()
1415 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(indirect->buffer), in si_emit_draw_packets()
1442 struct si_resource *params_buf = si_resource(indirect->indirect_draw_count); in si_emit_draw_packets()
1660 struct si_resource *buf = si_resource(vb->buffer.resource); in si_set_vb_descriptor()
1834 si_resource(vstate->b.input.vbuffer.buffer.resource), in si_upload_and_prefetch_VB_descriptors()
1856 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(vb->buffer.resource), in si_upload_and_prefetch_VB_descriptors()
2184 } else if (GFX_VERSION <= GFX7 && si_resource(indexbuf)->TC_L2_dirty) { in si_draw()
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Dsi_state.h145 struct si_resource *instance_divisor_factor_buffer;
431 struct si_resource *buffer;
528 void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
Dsi_gfx_cs.c185 si_resource(pipe_buffer_create(ctx->b.screen, 0, PIPE_USAGE_STAGING, 4)); in si_begin_gfx_cs_debug()
412 … unlikely(is_secure) ? si_resource(ctx->tess_rings_tmz) : si_resource(ctx->tess_rings), in si_begin_new_gfx_cs()
706 struct si_resource* wait_mem_scratch = unlikely(ctx->ws->cs_is_secure(cs)) ? in gfx10_emit_cache_flush()
946 struct si_resource* wait_mem_scratch = unlikely(sctx->ws->cs_is_secure(cs)) ? in si_emit_cache_flush()
Dsi_query.c578 buffer->buf = si_resource(pipe_buffer_create(&screen->b, 0, PIPE_USAGE_STAGING, buf_size)); in si_query_buffer_alloc()
646 struct si_resource *buffer, uint64_t va);
648 struct si_resource *buffer, uint64_t va);
769 struct si_resource *buffer, uint64_t va) in si_query_hw_do_emit_start()
835 struct si_resource *buffer, uint64_t va) in si_query_hw_do_emit_stop()
931 static void emit_set_predicate(struct si_context *ctx, struct si_resource *buf, uint64_t va, in emit_set_predicate()
1541 si_resource(resource)->TC_L2_dirty = true; in si_query_hw_get_result_resource()
Dsi_shader.h778 struct si_resource *bo;
779 struct si_resource *scratch_bo;
Dsi_cp_reg_shadowing.c32 struct si_resource *shadow_regs) in si_build_load_reg()
Dsi_perfcounter.c127 static void si_pc_emit_start(struct si_context *sctx, struct si_resource *buffer, uint64_t va) in si_pc_emit_start()
146 static void si_pc_emit_stop(struct si_context *sctx, struct si_resource *buffer, uint64_t va) in si_pc_emit_stop()
Dsi_compute_blit.c149 si_resource(buffers[u_bit_scan(&writeable_bitmask)].buffer)->TC_L2_dirty = true; in si_launch_grid_internal_ssbos()
408 if (sctx->screen->info.has_dedicated_vram && si_resource(dst)->domains & RADEON_DOMAIN_VRAM && in si_copy_buffer()
409 si_resource(src)->domains & RADEON_DOMAIN_VRAM && size > compute_min_size && in si_copy_buffer()
Dsi_texture.c643 struct si_resource *res = si_resource(resource); in si_texture_get_handle()
662 res = si_resource(resource); in si_texture_get_handle()
888 struct si_resource *resource; in si_texture_create_object()
1742 struct si_resource *buf; in si_texture_transfer_map()
1880 struct si_resource *buf = stransfer->staging ? stransfer->staging : &tex->buffer; in si_texture_transfer_unmap()
Dsi_pipe.c544 sctx->border_color_buffer = si_resource(pipe_buffer_create( in si_create_context()
822 return !ws->buffer_wait(ws, si_resource(resource)->buf, 0, in si_is_resource_busy()
975 si_resource(buf)->gpu_address = 0; /* cause a VM fault */ in si_test_vmfault()
Dgfx10_query.c99 qbuf->buf = si_resource(pipe_buffer_create(&screen->b, 0, PIPE_USAGE_STAGING, buf_size)); in gfx10_alloc_query_buffer()
Dsi_state.c3695 void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf, in si_make_buffer_descriptor()
4341 si_make_buffer_descriptor(sctx->screen, si_resource(texture), state->format, in si_create_sampler_view_custom()
4881 v->instance_divisor_factor_buffer = (struct si_resource *)pipe_buffer_create( in si_create_vertex_elements()
4984 si_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER; in si_set_vertex_buffers()
5004 si_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER; in si_set_vertex_buffers()
Dsi_debug.c625 struct si_resource *buf;
Dsi_state_shaders.c3912 si_resource(sctx->tess_rings)->gpu_address + sctx->screen->tess_offchip_ring_size; in si_init_tess_factor_ring()
3921 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(sctx->tess_rings), in si_init_tess_factor_ring()
3972 si_resource(sctx->tess_rings_tmz)->gpu_address + sctx->screen->tess_offchip_ring_size; in si_init_tess_factor_ring()
/third_party/mesa3d/src/gallium/drivers/radeon/
Dradeon_video.c65 buffer->res = si_resource(pipe_buffer_create(screen, PIPE_BIND_SHARED, usage, size)); in si_vid_create_buffer()
76 buffer->res = si_resource(pipe_buffer_create(screen, PIPE_BIND_SHARED | PIPE_BIND_PROTECTED, in si_vid_create_tmz_buffer()
Dradeon_video.h42 struct si_resource *res;
Dradeon_vcn_dec.c1648 decode->dt_size = si_resource(((struct vl_video_buffer *)target)->resources[0])->buf->size + in rvcn_dec_message_decode()
1649 si_resource(((struct vl_video_buffer *)target)->resources[1])->buf->size; in rvcn_dec_message_decode()

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