Searched refs:tcs_in_out_eq (Results 1 – 10 of 10) sorted by relevance
| /third_party/mesa3d/src/amd/common/ |
| D | ac_nir_lower_tess_io_to_mem.c | 129 bool tcs_in_out_eq; member
231 if (!st->tcs_in_out_eq) in lower_ls_output_store()
249 if (!st->tcs_in_out_eq) in filter_load_tcs_per_vertex_input()
622 bool tcs_in_out_eq, in ac_nir_lower_ls_outputs_to_mem() argument
630 .tcs_in_out_eq = tcs_in_out_eq, in ac_nir_lower_ls_outputs_to_mem()
631 .tcs_temp_only_inputs = tcs_in_out_eq ? tcs_temp_only_inputs : 0, in ac_nir_lower_ls_outputs_to_mem()
642 bool tcs_in_out_eq, in ac_nir_lower_hs_inputs_to_mem() argument
648 .tcs_in_out_eq = tcs_in_out_eq, in ac_nir_lower_hs_inputs_to_mem()
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| D | ac_nir.h | 44 bool tcs_in_out_eq,
50 bool tcs_in_out_eq,
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| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_instruction_selection.h | 100 bool tcs_in_out_eq = false; member
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| D | aco_instruction_selection_setup.cpp | 304 ctx->tcs_in_out_eq = ctx->args->shader_info->vs.tcs_in_out_eq; in setup_tcs_info()
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| D | aco_instruction_selection.cpp | 4704 if (ctx->shader->info.stage != MESA_SHADER_TESS_CTRL || !ctx->tcs_in_out_eq) in load_input_from_temps()
11590 ctx.tcs_in_out_eq ? i == 0 : (shader_count >= 2 && !empty_shader && !(ngg_gs && i == 1)); in select_program()
11592 ctx.tcs_in_out_eq ? i == 1 : (check_merged_wave_info && !(ngg_gs && i == 1)); in select_program()
11651 if (i == 0 && ctx.stage == vertex_tess_control_hs && ctx.tcs_in_out_eq) { in select_program()
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| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_shader.h | 259 bool tcs_in_out_eq; member
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| D | radv_shader.c | 850 ac_nir_lower_ls_outputs_to_mem(nir, info->vs.tcs_in_out_eq, in radv_lower_io_to_mem()
860 ac_nir_lower_hs_inputs_to_mem(nir, info->vs.tcs_in_out_eq, info->tcs.num_linked_inputs); in radv_lower_io_to_mem()
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| D | radv_pipeline.c | 3086 infos[MESA_SHADER_VERTEX].vs.tcs_in_out_eq = in gather_tess_info()
3092 if (infos[MESA_SHADER_VERTEX].vs.tcs_in_out_eq) in gather_tess_info()
3101 infos[MESA_SHADER_TESS_CTRL].vs.tcs_in_out_eq = infos[MESA_SHADER_VERTEX].vs.tcs_in_out_eq; in gather_tess_info()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 20.2.0.rst | 3892 - aco: set tcs_in_out_eq=false if float controls of VS and TCS stages differ
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| D | 21.1.0.rst | 5388 - radv: Determine tcs_in_out_eq in radv_pipeline instead of the compiler.
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