Searched refs:u8 (Results 1 – 25 of 6647) sorted by relevance
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312 u8 outer_dmac[0x1];313 u8 outer_smac[0x1];314 u8 outer_ether_type[0x1];315 u8 outer_ip_version[0x1];316 u8 outer_first_prio[0x1];317 u8 outer_first_cfi[0x1];318 u8 outer_first_vid[0x1];319 u8 outer_ipv4_ttl[0x1];320 u8 outer_second_prio[0x1];321 u8 outer_second_cfi[0x1];[all …]
36 u8 reserved_at_0[0x60];38 u8 ipv4[0x20];42 u8 ipv6[16][0x8];48 u8 reserved_at_0[0x80];61 u8 max_num_qps[0x10];62 u8 reserved_at_10[0x8];63 u8 total_rcv_credits[0x8];65 u8 reserved_at_20[0xe];66 u8 qp_type[0x2];67 u8 reserved_at_30[0x5];[all …]
103 u8 entry_type[0x4];104 u8 reserved_at_4[0x4];105 u8 entry_sub_type[0x8];106 u8 byte_mask[0x10];108 u8 next_table_base_63_48[0x10];109 u8 next_lu_type[0x8];110 u8 next_table_base_39_32_size[0x8];112 u8 next_table_base_31_5_size[0x1b];113 u8 linear_hash_enable[0x1];114 u8 reserved_at_5c[0x2];[all …]
26 u8 raw;29 u8 CTL :8;32 u8 LDCERC_4e;33 u8 LDUERC_4f;34 u8 LD_BER0_65;35 u8 LD_BER1_66;36 u8 LD_BER2_67;37 u8 LD_BER3_68;40 u8 RESET :1;41 u8 IDLE :1;[all …]
195 u8 fis_type; /* 0x34 */196 u8 flags;197 u8 status;198 u8 error;200 u8 lbal;201 union { u8 lbam; u8 byte_count_low; };202 union { u8 lbah; u8 byte_count_high; };203 u8 device;205 u8 lbal_exp;206 u8 lbam_exp;[all …]
14 u8 link_up:1;15 u8 link_renegotiate:1;16 u8 minimal_link_speed:1;17 u8 internal_loopback:1;18 u8 external_loopback:1;19 u8 rate_10M_hd:1;20 u8 rate_100M_hd:1;21 u8 rate_1G_hd:1;23 u8 rate_10M:1;24 u8 rate_100M:1;[all …]
64 u8 reset_stat:1;65 u8 reset_all_int:1;66 u8 reserved1:6;67 u8 reserved2[3];83 u8 mib_data[];89 u8 mib_data[];97 u8 beacon:1;98 u8 probe_resp:1;99 u8 probe_req:1;100 u8 reserved1:5;[all …]
107 u8 mid;108 u8 reserved;371 u8 network_type;372 u8 dot11_auth_mode;373 u8 auth_mode;374 u8 pairwise_crypto_type;375 u8 pairwise_crypto_len;376 u8 group_crypto_type;377 u8 group_crypto_len;378 u8 ssid_len;[all …]
28 u8 AdvCoding:1;29 u8 ChlWidth:1;30 u8 MimoPwrSave:2;31 u8 GreenField:1;32 u8 ShortGI20Mhz:1;33 u8 ShortGI40Mhz:1;34 u8 TxSTBC:1;35 u8 RxSTBC:2;36 u8 DelayBA:1;37 u8 MaxAMSDUSize:1;[all …]
19 u8 ref_clock;20 u8 settling_time;21 u8 clk_valid_on_wakeup;22 u8 dc2dc_mode;23 u8 dual_mode_select;24 u8 tx_bip_fem_auto_detect;25 u8 tx_bip_fem_manufacturer;26 u8 general_settings;27 u8 sr_state;28 u8 srf1[WL1271_INI_MAX_SMART_REFLEX_PARAM];[all …]
42 u8 AdvCoding:1;43 u8 ChlWidth:1;44 u8 MimoPwrSave:2;45 u8 GreenField:1;46 u8 ShortGI20Mhz:1;47 u8 ShortGI40Mhz:1;48 u8 TxSTBC:1;49 u8 RxSTBC:2;50 u8 DelayBA:1;51 u8 MaxAMSDUSize:1;[all …]
274 u8 __iomem *csr_va; /* CSR */275 u8 __iomem *db_va; /* Door Bell */276 u8 __iomem *pci_va; /* PCI Config */350 u8 optic_state;362 u8 mac_address[ETH_ALEN];363 u8 port_name;364 u8 port_speed;430 u8 opcode[6]; /* opcode */431 u8 rsvd0[2]; /* should be 0 */432 u8 rsvd1[7];[all …]
89 u8 cr39_values[14];90 u8 reserved1[14];91 u8 bb_cr[14];92 u8 pidvid[4];93 u8 mac_addr[ETH_ALEN];94 u8 regulatory_domain;95 u8 reserved2[14];96 u8 cr15_values[14];97 u8 reserved3[3];101 u8 cr20_values[14];[all …]
13 u8 cid;14 u8 pkt_type;15 u8 set_query; /* FW don't care */16 u8 seq;18 u8 uc_d2b0_rev;19 u8 ext_cid;20 u8 s2d_index;21 u8 ext_cid_ack;63 u8 reserved;64 u8 pkt_type;[all …]
18 const u8 *input, *output, *assoc, *nonce, *key;30 static const u8 enc_input001[] __initconst = {66 static const u8 enc_output001[] __initconst = {104 static const u8 enc_assoc001[] __initconst = {108 static const u8 enc_nonce001[] __initconst = {111 static const u8 enc_key001[] __initconst = {118 static const u8 enc_input002[] __initconst = { };119 static const u8 enc_output002[] __initconst = {123 static const u8 enc_assoc002[] __initconst = { };124 static const u8 enc_nonce002[] __initconst = {[all …]
54 u8 signature[20];58 u8 vbt_checksum;59 u8 reserved0;72 u8 signature[16];128 u8 panel_fitting:2;129 u8 flexaim:1;130 u8 msg_enable:1;131 u8 clear_screen:3;132 u8 color_flip:1;135 u8 download_ext_vbt:1;[all …]
13 u8 cid;14 u8 pkt_type;15 u8 set_query; /* FW don't care */16 u8 seq;18 u8 uc_d2b0_rev;19 u8 ext_cid;20 u8 s2d_index;21 u8 ext_cid_ack;55 u8 eid;56 u8 seq;[all …]
222 u8 rsvd0[32]; /* dword 0 */223 u8 rsvd1[32]; /* dword 1 */224 u8 complete; /* dword 2 */225 u8 event;226 u8 crc;227 u8 forward;228 u8 lso6;229 u8 mgmt;230 u8 ipcs;231 u8 udpcs;[all …]
92 u8 DM_Type;96 u8 DMFlag;97 u8 InitDMFlag;113 u8 bDynamicTxPowerEnable;114 u8 LastDTPLvl;115 u8 DynamicTxHighPowerLvl;/* Add by Jacken Tx Power Control for Near/Far Range 2008/03/06 */118 u8 bTXPowerTracking;119 u8 TXPowercount;120 u8 bTXPowerTrackingInit;121 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */[all …]
14 u8 bLength;15 u8 bDescriptorType;16 u8 bDescriptorSubtype;20 u8 bCapabilities;34 u8 bLength;35 u8 bDescriptorType;36 u8 bDescriptorSubtype;37 u8 bFlags;38 u8 bInterfaceType;39 u8 bInterfaceId;[all …]
21 u8 res1[6];23 u8 res2[20];25 u8 sc_ppc_acr;26 u8 res3[3];29 u8 sc_lcl_acr;30 u8 res4[3];38 u8 sc_pdtem;39 u8 res5[3];41 u8 sc_ldtem;42 u8 res6[163];[all …]
11 u8 rfifo[0x20]; /* Receive FIFO */12 u8 star; /* Status Register */13 u8 __pad1;14 u8 mode; /* Mode Register */15 u8 timr; /* Timer Register */16 u8 xon; /* XON Character */17 u8 xoff; /* XOFF Character */18 u8 tcr; /* Termination Character Register */19 u8 dafo; /* Data Format */20 u8 rfc; /* RFIFO Control Register */[all …]
22 #define ACPI_READ_ONLY_MEMORY (u8) 0x0023 #define ACPI_READ_WRITE_MEMORY (u8) 0x0125 #define ACPI_NON_CACHEABLE_MEMORY (u8) 0x0026 #define ACPI_CACHABLE_MEMORY (u8) 0x0127 #define ACPI_WRITE_COMBINING_MEMORY (u8) 0x0228 #define ACPI_PREFETCHABLE_MEMORY (u8) 0x0338 #define ACPI_NON_ISA_ONLY_RANGES (u8) 0x0139 #define ACPI_ISA_ONLY_RANGES (u8) 0x0244 #define ACPI_SPARSE_TRANSLATION (u8) 0x0149 #define ACPI_DECODE_10 (u8) 0x00 /* 10-bit IO address decode */[all …]
7 u8 phys_id;8 u8 phys_ext_id;9 u8 connector;11 u8 e10g_base_er:1;12 u8 e10g_base_lrm:1;13 u8 e10g_base_lr:1;14 u8 e10g_base_sr:1;15 u8 if_1x_sx:1;16 u8 if_1x_lx:1;17 u8 if_1x_copper_active:1;[all …]
15 u8 signature[20]; /**< Always starts with 'VBT$' */19 u8 vbt_checksum;20 u8 reserved0;27 u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */35 u8 type; /* 0 == desktop, 1 == mobile */36 u8 relstage;37 u8 chipset;38 u8 lvds_present:1;39 u8 tv_present:1;40 u8 rsvd2:6; /* finish byte */[all …]