1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/imx25-clock.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Clock bindings for Freescale i.MX25 8 9maintainers: 10 - Sascha Hauer <s.hauer@pengutronix.de> 11 12description: | 13 The clock consumer should specify the desired clock by having the clock 14 ID in its "clocks" phandle cell. The following is a full list of i.MX25 15 clocks and IDs. 16 17 Clock ID 18 -------------------------- 19 dummy 0 20 osc 1 21 mpll 2 22 upll 3 23 mpll_cpu_3_4 4 24 cpu_sel 5 25 cpu 6 26 ahb 7 27 usb_div 8 28 ipg 9 29 per0_sel 10 30 per1_sel 11 31 per2_sel 12 32 per3_sel 13 33 per4_sel 14 34 per5_sel 15 35 per6_sel 16 36 per7_sel 17 37 per8_sel 18 38 per9_sel 19 39 per10_sel 20 40 per11_sel 21 41 per12_sel 22 42 per13_sel 23 43 per14_sel 24 44 per15_sel 25 45 per0 26 46 per1 27 47 per2 28 48 per3 29 49 per4 30 50 per5 31 51 per6 32 52 per7 33 53 per8 34 54 per9 35 55 per10 36 56 per11 37 57 per12 38 58 per13 39 59 per14 40 60 per15 41 61 csi_ipg_per 42 62 epit_ipg_per 43 63 esai_ipg_per 44 64 esdhc1_ipg_per 45 65 esdhc2_ipg_per 46 66 gpt_ipg_per 47 67 i2c_ipg_per 48 68 lcdc_ipg_per 49 69 nfc_ipg_per 50 70 owire_ipg_per 51 71 pwm_ipg_per 52 72 sim1_ipg_per 53 73 sim2_ipg_per 54 74 ssi1_ipg_per 55 75 ssi2_ipg_per 56 76 uart_ipg_per 57 77 ata_ahb 58 78 reserved 59 79 csi_ahb 60 80 emi_ahb 61 81 esai_ahb 62 82 esdhc1_ahb 63 83 esdhc2_ahb 64 84 fec_ahb 65 85 lcdc_ahb 66 86 rtic_ahb 67 87 sdma_ahb 68 88 slcdc_ahb 69 89 usbotg_ahb 70 90 reserved 71 91 reserved 72 92 reserved 73 93 reserved 74 94 can1_ipg 75 95 can2_ipg 76 96 csi_ipg 77 97 cspi1_ipg 78 98 cspi2_ipg 79 99 cspi3_ipg 80 100 dryice_ipg 81 101 ect_ipg 82 102 epit1_ipg 83 103 epit2_ipg 84 104 reserved 85 105 esdhc1_ipg 86 106 esdhc2_ipg 87 107 fec_ipg 88 108 reserved 89 109 reserved 90 110 reserved 91 111 gpt1_ipg 92 112 gpt2_ipg 93 113 gpt3_ipg 94 114 gpt4_ipg 95 115 reserved 96 116 reserved 97 117 reserved 98 118 iim_ipg 99 119 reserved 100 120 reserved 101 121 kpp_ipg 102 122 lcdc_ipg 103 123 reserved 104 124 pwm1_ipg 105 125 pwm2_ipg 106 126 pwm3_ipg 107 127 pwm4_ipg 108 128 rngb_ipg 109 129 reserved 110 130 scc_ipg 111 131 sdma_ipg 112 132 sim1_ipg 113 133 sim2_ipg 114 134 slcdc_ipg 115 135 spba_ipg 116 136 ssi1_ipg 117 137 ssi2_ipg 118 138 tsc_ipg 119 139 uart1_ipg 120 140 uart2_ipg 121 141 uart3_ipg 122 142 uart4_ipg 123 143 uart5_ipg 124 144 reserved 125 145 wdt_ipg 126 146 cko_div 127 147 cko_sel 128 148 cko 129 149 150properties: 151 compatible: 152 const: fsl,imx25-ccm 153 154 reg: 155 maxItems: 1 156 157 interrupts: 158 maxItems: 1 159 160 '#clock-cells': 161 const: 1 162 163required: 164 - compatible 165 - reg 166 - interrupts 167 - '#clock-cells' 168 169additionalProperties: false 170 171examples: 172 - | 173 clock-controller@53f80000 { 174 compatible = "fsl,imx25-ccm"; 175 reg = <0x53f80000 0x4000>; 176 interrupts = <31>; 177 #clock-cells = <1>; 178 }; 179 180 serial@43f90000 { 181 compatible = "fsl,imx25-uart", "fsl,imx21-uart"; 182 reg = <0x43f90000 0x4000>; 183 interrupts = <45>; 184 clocks = <&clks 79>, <&clks 50>; 185 clock-names = "ipg", "per"; 186 }; 187